JP2001005411A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently arrange pixels by placing adjoining pixels opposite to each other across a data line. SOLUTION: A gate line Xn, a gate line Xn+1 of the next row, auxiliary capacitance of a pixel, a data line Ym, and pixel capacitance (pixel electrode) CLC comprise a circuit having the auxiliary capacitance. Here, C is the auxiliary capacitance produced by overlapping of the gate line Xn and the pixel capacitance CLC. In this case, the pixels connected with the gate line Xn and the data line Ym are alternately arranged with those connected with the lower gate line Xn+1 and the same data line Ym. And, the pixel electrodes of the pixels cross the gate line Xn+1, and form the auxiliary capacitance C (diagonally shaded area) here. The feature of the auxiliary capacitance C thus formed is easiness in forming, different from the conventional case where it was formed in a difficult pattern. Moreover, there is no danger of destroying TFT, and further, it is convenient to arrange pixels in color as they are.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrostatic display device such as a liquid crystal display device, and more particularly to a display device having an active matrix.

[0002]

2. Description of the Related Art In recent years, active matrices for driving liquid crystal displays have been actively studied and put into practical use. In a conventional active matrix circuit, a capacitor having a liquid crystal interposed between a pixel electrode and a counter electrode is formed, and electric charges entering and exiting the capacitor are controlled by a thin film transistor (TFT). In order to display images stably, it was required that the voltage of both electrodes of the capacitor be kept constant, but there were difficulties for several reasons.

The biggest reason is that electric charges leak from the capacitor even when the TFT is off. In addition, there was also a leak inside the capacitor, but generally the former leak from the TFT was about one digit larger. When the leak is remarkable, a phenomenon called flicker occurs in which the brightness of the image changes at the same cycle as the frame frequency. In addition, a phenomenon (ΔV) in which the gate signal is capacitively coupled to the pixel potential due to the parasitic capacitance between the gate electrode and the pixel electrode of the TFT and the voltage fluctuates is also one of the causes.

In order to solve these problems, an auxiliary capacitor (also called an additional capacitor) has been provided in parallel with the pixel capacitor. This is shown in a circuit diagram of FIG. That is, such an auxiliary capacitance increases the time constant of discharging the charge of the pixel capacitance. Also, ΔV
Is, when the gate pulse (signal voltage) is V _G , the pixel capacitance is C _LC , the auxiliary capacitance is C, and the parasitic capacitance between the gate electrode and the pixel electrode is C ′, ΔV = C′V _G / (C _LC + C ′) + C) is represented by, C was able to reduce the ΔV greater than the C 'and C _LC.

[0005]

Conventionally, such an auxiliary capacitor has a circuit arrangement as shown in FIG. 1B or 1C. In the method of FIG. 1B, the gate line X
_In some cases, a ground line, for example, X _n ′ as shown in the figure is formed in parallel with _n (or Y _m ), and a capacitor C is formed on the ground line by overlapping pixel electrodes. A typical structure is shown in FIG. The storage capacitor C is indicated by a hatched portion. However, in this method, a new wiring must be formed, so that the aperture ratio is reduced and the screen becomes dark.

[0006] In contrast, with a part of the pixel connected to the gate line X _n are overlapped to the next gate line X _{n + 1} as shown in FIG. 1 (C), which shall be the storage capacitance C Has been proposed. In this case, since no new wiring is formed, the aperture ratio does not decrease. However, conventionally,
For the arrangement of pixels, connected to the same data line Y _m, pixel Z _n the gate line are adjacent to each _{other, m} and the pixel Z _{n + 1, m} is provided in the same direction with respect to the data lines, efficient pixel No particular consideration has been given to the arrangement of. That is, in this case, there is a danger that the pixels in the upper row will come into contact with the TFTs in the pixels in the lower row. The present invention has been made in view of such a point, and proposes an efficient pixel arrangement.

[0007]

In order to solve this problem, according to the present invention, adjacent pixels Zn _{, m} and pixels Zn _{+ 1, m} are arranged to be opposite to each other across a data line. It is characterized by. A typical example is shown in FIG. That is, the pixel Z is connected to the gate lines X _n and the data lines Y _m in the present invention
_{n and m} are the same data lines Y as the gate line X _{n + 1 in} the row below.
a pixel Z _{n + 1, m} to be connected to _m to staggered. The pixel electrode of the pixel _{Zn, m} traverses the gate line _{Xn + 1} and forms an auxiliary capacitance C (shaded portion) here.

The feature of the storage capacitor formed in this manner is that it is easy to manufacture, unlike the case where the storage capacitor is formed in a difficult pattern as in the prior art. As is clear from the figure, in the conventional method, the pixel electrode had to overlap the gate line adjacent to the TFT. In this case, there was a high risk of breaking the TFT. However, in the present invention, the portion where the auxiliary capacitance is provided is T T
There is no danger of destroying the TFT because the FT is not nearby. In addition, when the pixels are arranged one by one as described above, it is convenient to arrange the pixels in color as they are.

That is, conventionally, in order to improve the color mixing, the arrangement of the pixels has been made into a honeycomb shape or a hexagonal shape. In this case, the wiring is bent accordingly. This led to an increase in wiring resistance, and also caused an increase in defects due to difficulty in manufacturing. However, according to the present invention, an ideal hexagonal structure can be obtained without bothersomely bending the wiring.

In order to implement the present invention, no particular advanced technology is required, and the present invention can be carried out extremely simply because a conventional TFT manufacturing technology may be used. Hereinafter, a method for manufacturing a circuit having the structure of the present invention will be described as an example.

[0011]

FIG. 2B is a schematic view of a circuit having an auxiliary capacitor manufactured in this embodiment as viewed from above. In the figure,
_Xn is a gate wiring. X _{n + 1} is a gate line of the next row and also forms an auxiliary capacitance of the pixel Zn _{, m} . Y _m is the data line. _CLC indicates a pixel capacitance (pixel electrode), and C is an auxiliary capacitance formed by overlapping _Xn and _CLC .

FIG. 3 shows a manufacturing process of this embodiment. Figures (A-1), (B-1), (C-1), and (D-1) are cross-sectional views, and (A-2), (B-2), (C-2),
(D-2) is a top view. Since the details of each process are described in Japanese Patent Application Nos. 4-30220, 4-38637, and 3-273377, no particular description is given here.

First, an underlying silicon oxide film 2 is formed on a substrate 1. This may be a multilayer film of silicon oxide and silicon nitride. Then, an island-shaped semiconductor region 3 is formed. further,
A gate insulating film (silicon oxide) 4 was formed, and a gate line X _n (5) and a gate line X _{n + 1} (6) of the next row were formed with aluminum. (FIGS. 3A-1 and 3A-2) Although not shown in the figure, a semiconductor region similar to the island-shaped semiconductor region 3 is also formed on the left or right side of the gate line 6. Is done.

Thereafter, anodization was performed to form aluminum oxide films 7 and 8 around the gate wirings 5 and 6, respectively. Then, an impurity region (source / drain) 9 was formed by implanting impurities. (FIG. 3 (B-1)
And (B-2))

Next, a silicon oxide interlayer insulator having a thickness of 50
Only 0 nm was formed. Here, the silicon oxide 10 was left only in the lower part of the data line, and the rest was removed. (FIG. 3
(C-1) and (C-2))

A capacitance is generated at a portion where the data line and the gate lines 5 and 6 intersect, and this capacitance causes a delay of a gate signal and data. In order to reduce the capacitance, it is good to form the interlayer insulator thick as described above, but such interlayer insulator is not particularly required for other portions. In particular, when the silicon oxide layer is removed up to the one formed as the gate insulating film as in the present embodiment, the conventional contact hole is unnecessary, and therefore, the contact failure is significantly reduced. Could be reduced.

In such a process, a mask is required for the silicon oxide region 10, but no mask is required for the other portions. This is because aluminum oxide formed as an anodic oxide film has extremely high corrosion resistance and, for example, etching with buffered hydrofluoric acid has a sufficiently slower etching rate than etching rate of silicon oxide.

Therefore, the silicon oxide film can be etched in a self-aligned manner with respect to the gate electrode. conventionally,
Although fine mask alignment was necessary for forming the contact hole of the TFT, this is not necessary in the present embodiment. Naturally, the silicon oxide formed on the auxiliary wiring is also removed, exposing the anodic oxide film.

Finally, the data lines 11 were formed of aluminum or chromium, and the pixel electrodes 12 were formed of ITO. At this time, the storage capacitor 13 was formed by arranging the pixel electrode and the gate line 6 so as to overlap.
(FIG. 4 (D-1) and (D-2)) Of course, the TFT
An aluminum (or chromium) electrode / wiring may also be formed on the pixel electrode side, and the pixel electrode may be formed thereon using ITO.

In this embodiment, the structure of the cross section of the storage capacitor has a structure of metal wiring (aluminum) / anodic oxide (aluminum oxide) / pixel electrode (ITO). In this case, the relative permittivity of aluminum oxide is three times that of silicon oxide, which contributes to increasing the auxiliary capacitance. If a larger storage capacitor is required, the gate line may be made of tantalum or titanium, anodized, and their oxides may be used as the dielectric of the storage capacitor.

Alternatively, a method of using metal wiring / oxide (which can be formed by a CVD method or a sputtering method using silicon oxide, silicon nitride, etc.) / Pixel electrode as conventionally used without taking such a manufacturing method / structure. May be used.

[0022]

As described above, according to the present invention, pixels can be efficiently arranged. This arrangement of pixels not only reduced defects, but was also effective in displaying colors. The above description relates to a planar type TFT often used for polysilicon TF, but an inverted stagger type TFT often used for amorphous silicon TFT.
Obviously, the same effect can be obtained even with the above.

[Brief description of the drawings]

FIG. 1 shows a circuit diagram of an active matrix.

FIG. 2A shows a circuit arrangement of an active matrix according to a conventional method. (B) shows a circuit arrangement of an active matrix according to the present invention.

FIG. 3 shows an example of a manufacturing process of a circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Underlying silicon oxide layer 3 Island-shaped semiconductor region 4 Gate insulating film 5, 6 Gate electrode / wiring 7, 8 Anodized film 9 Impurity region 10 Interlayer insulator 11 Data line 12 Pixel electrode 13 Auxiliary capacitance

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[Procedure amendment]

[Submission date] May 22, 2000 (2000.5.2)
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

6. A any one of claims 1 to 7,
The display device, wherein a channel formation region of the thin film transistor is made of amorphous silicon.

7. In any one of claims 1 to 7,
The display device, wherein the thin film transistor is a planar thin film transistor.

8. In any one of claims 1 to 7,
The display device, wherein the thin film transistor is an inverted staggered thin film transistor.

Claims (4)

[Claims] A plurality of pixels, each of the plurality of pixels including a pixel electrode and the pixel electrode;
The thin film transistor connected to the
Active matrix type display device, wherein a pixel Z_{n, m}, The gate line X in the n-th row_n And m-th column
Data line Y_m The thin film transistor is connected to
Pixel electrode X for transistor_nY_m Is connected, and the pixel Z_{n + 1, m}, The gate line X in the (n + 1) th row_n as well as
M-th column data line Y_mIs connected to a thin film transistor,
The thin film transistor has a pixel electrode X_{n + 1}Y_m Is connected, and the pixel Z_{n + 2, m}, The gate line X in the (n + 2) th row_{n + 2} Passing
And the m-th column data line Y_mThin film transistor connected to
And the pixel electrode X_{n + 2}Y_m Is connected
The gate line X_{n + 1} Is the pixel electrode X_nY_m And insulation
Through the pixel Z_{n, m}The capacitance of the gate line
X_{n + 1} And the pixel electrode X_nY_m To a pair of electrodes.
The edge is made of a dielectric material, and the gate line X_{n + 2} Is the pixel electrode X_{n + 1}Y_m And insulation
And the pixel Z_{n + 1, m}The capacity of the game
Line X_{n + 2} And the pixel electrode X_{n + 1}Y_m To a pair of electrodes,
Using the insulator as a dielectric, the gate line X in the (n + 3) th row_{n + 3} Is the pixel electrode X_{n + 2}Y_m 
And the pixel Z_{n + 2, m}The capacity of
The gate line X_{n + 3} And the pixel electrode X_{n + 2}Y_mA pair of
The electrode is made of the dielectric material as a dielectric, and the data line Y_m In the above, the pixel Z_{n, m} Thin film tiger
The connection portion of the transistor is connected to the pixel Z_{n + 1},_m Thin film transistor
The pixel Z _{n + 2, m} of
On the same side as the connection part of the thin film transistor;_{n, m}Is the pixel Z in the row direction._{n + 1, m} And close,
In the column direction, the pixel Z_{n + 2 , m} Is characterized by being adjacent to
Display device. 2. The display device according to claim 1, wherein a channel formation region of the thin film transistor is made of amorphous silicon. 3. The display device according to claim 1, wherein the thin film transistor is a planar thin film transistor. 4. The display device according to claim 1, wherein the thin film transistor is an inverted staggered thin film transistor.