JP2001004699A - Manufacture of semiconductor device and jig for inspection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspecting method of a semiconductor device, capable of ensuring high reliability at a low cost. SOLUTION: An integrated structure is formed of a base 3, contactors 5, trays 4, an elastic body, and a lid 9. After a multiplicity of LSI chips 1b are cut off and separated from a wafer, an appropriately fixed number of them can be rearranged and inspected collectively and systematically by utilizing the integrated structure. Thus, a fixed number of them can be collectively inspected without using conventional sockets, etc., the inspection process is simplified to sharply increase efficiency, and therefore the inspection cost can be decreased. Further, a secondary electrode 5c is formed on a surface of each contactor 5 while a probe part 5a is formed on a back face thereof. The probe part 5a confronts an electrode pad 1c of each chip 1b and is supported by a flexible beam 5d. When a contact probe 6a makes contact with and presses against the secondary electrode 5c, the probe part 5a is simultaneously pressed against the electrode pad 1c, and thus they can be surely brought into conduction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including a step of inspecting circuit elements of a manufactured semiconductor device, and more particularly to a method of manufacturing a semiconductor device suitable for simplifying and improving the inspection step. About the method.

[0002]

2. Description of the Related Art First, a conventional method for manufacturing a semiconductor device will be described.
This will be described with reference to FIGS. 9 and 10 attached. FIG. 9 is a flowchart outlining a manufacturing process portion including a test process according to the present invention, among the conventional semiconductor device manufacturing methods. FIG. 10 shows various forms of a manufactured semiconductor device in various steps of the above-mentioned semiconductor device manufacturing process. Conventionally, a semiconductor device is generally manufactured by the following steps roughly in its manufacturing method. Manufactured. Note that the order of these steps is consistent with the order described below.

(1) Pre-process This pre-process 100 is an LSI in which a large number of circuit elements are integrated and formed on a semiconductor wafer 1a (FIG. 10 (a)).
This is a step of forming a large number of (large-scale integrated circuit) chips 1b.

(2) Probing Inspection Step The probing inspection step 100 A
LS formed on the semiconductor wafer 1a formed by the process
This is a step of performing a so-called initial discrimination of whether the I is good or bad for each LSI chip 1b using a probe.

(3) Cutting Step This cutting step 101 is performed by using the L
This is a process of cutting the semiconductor wafer by using, for example, a laser beam, a dicer, or the like to cut the SI into individual chips 1b.

(4) Integration Step (Mounting or Packaging Step) In this integration step 102, each chip 1 b obtained in the cutting step 101 is adapted to be compatible with a subsequent step (inspection step). After mounting on a so-called socket 2 ((c) in FIG. 10), or electrically connecting each electrode pad on the chip to a lead frame, these are packaged with a resin or the like, and then an object to be inspected in a subsequent inspection process is obtained. It is a process of forming as.

(5) Burn-in step In the burn-in step 103, a plurality of electrical or thermal stresses are simultaneously applied to the subject obtained in the integration step 102 for a long time, and the LSI chip 1b manufactured by this is applied. This is a process of accelerating and sorting out potential defects.

(6) Sorting and Inspection Step This sorting step 104 is performed after the above steps 100 to 103, and is a final inspection step for reliability and performance of the semiconductor device.

[0009] Then, the semiconductor devices that have been sorted and inspected in the sorting and inspecting step 104 are shipped in the shipping step 105.

[0010] Of the above steps, a probing inspection step 100A, a burn-in step 103, a screening inspection step 1
In each step of step 04, probes arranged corresponding to their positions and dimensions are brought into contact with a predetermined group of electrode pads 1c formed on the semiconductor wafer 1a or the chip 1b. A predetermined inspection is performed independently by conducting with an inspection system (not shown).

[0011] However, as is clear from the above description, of the above-described steps, especially in the initial probing inspection, as shown in FIG.
This is performed while a large number of LSI chips 1b are formed on a. On the other hand, in the subsequent burn-in process 10
As shown in FIG. 10B, in each inspection process including the step 3, each LSI is usually performed in the state of the LSI chip 1b cut from the semiconductor wafer 1a on the chip.

More specifically, in each inspection process after cutting each LSI chip 1b from the semiconductor wafer 1a, each chip 1b is mounted on an individual socket 2 as shown in FIG. I do. Socket 2 is usually a substrate (not shown) that meets the specifications of the various inspection processes
Is installed in advance. Therefore, each chip 1b
Each time these inspection steps are performed, attachment / detachment with the socket 2 is repeated. By mounting these various substrates on an inspection system, a predetermined electrical connection is established, whereby a predetermined inspection is performed.

In contrast to the above-described steps, a method of directly mounting a plurality of chips 1b after cutting and separation on a substrate for inspection without using the socket 2 as described above, for example, This is disclosed in JP-A-3-131048. A method of performing burn-in without cutting a wafer is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-204621.
No. in the official gazette.

[0014]

However, the above-mentioned prior art has the following problems. First,
In the conventional semiconductor device manufacturing method described with reference to FIGS. 9 and 10, each chip 1b cut from the semiconductor wafer 1a is attached to and detached from the socket 2 each time the chip 1b is transferred to each socket 2. Had to be repeated. That is, it is necessary to mount one test chip 1b to one socket 2.

Therefore, it takes a lot of trouble to attach and detach the cut and separated test chip 1b to and from the socket 2. In addition, in order to conduct the test chip 1b and the socket 2 in a conductive manner,
Predetermined operations and costs are incurred.

Therefore, in order to reduce the inspection cost of the semiconductor device without causing the work and cost for conducting the initial defective chip, as shown in the flowchart of FIG. Socket 2 of test chip 1b
It is necessary to perform a probing inspection in advance before mounting on a chip, and thereby eliminate an initial defective chip before the cutting step. However, as a result, there is a problem that the number of steps for inspection increases and the cost for inspection increases.

In addition, as shown in the above-mentioned Japanese Patent Application Laid-Open No. Hei 3-131048, when a chip to be inspected 1b is directly mounted on an inspection substrate in chip units and the inspection is performed, a small It is necessary to prepare a fine probe group provided with a plurality of probes corresponding to the arrangement of the fine electrode pads on the surface of the test chip 1b.

However, such a group of microprobes is expensive in terms of its production, and when the type (shape, size, layout) of the chip 1b to be tested is diverse, it is necessary to deal with these various types of chips 1b. As a result, a large number of expensive fine probe groups are prepared, and this requires a great deal of equipment cost, which in turn increases the inspection cost.

Further, as is known from the above-mentioned Japanese Patent Application Laid-Open No. 63-204621, a method of performing a burn-in process on a manufactured LSI chip while keeping it in a wafer state,
Particularly, in recent large-diameter wafers, the formed LS
As the number of I increases, the number of electrodes to be electrically connected to the inspection system at once becomes enormous.

Therefore, it is difficult to realize a group of fine probes necessary for connecting to a substrate for inspection in order to perform a burn-in process in a wafer state. Further, even if it is realized, it becomes very expensive, and requires a large cost in terms of equipment, which also increases the inspection cost.

Further, even if an enormous number of electrodes are connected, the processing capability of the inspection system may be exceeded. further,
In particular, at the outer peripheral portion of the wafer 1a, the relative displacement between the contact (probe) and the electrode pad on the wafer due to the thermal expansion becomes large, and there may be cases where these two cannot physically contact each other. There was also a problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the prior art, that is, to solve the problems in the above-described prior art, to realize a low-cost and high reliability as a result. It is an object of the present invention to realize a possible semiconductor device manufacturing method.

Still another object of the present invention is to realize an inspection jig in a method of manufacturing a semiconductor device which can guarantee high reliability at a low cost.

[0024]

In order to achieve the above object, the present invention is configured as follows. (1) A step of forming a plurality of LSIs composed of a plurality of circuit elements on one semiconductor wafer, a step of cutting the wafer into a plurality of LSI chips, a step of inspecting the cut LSI chips, and the inspection Selecting an LSI chip that satisfies a desired standard based on the result of the inspection in the step. And a predetermined number N of cut LSI chips integrated by the integration step are integrated into at least a predetermined inspection process in the inspection step.

(2) Preferably, in the above (1),
The inspection step is performed using an integrated structure for rearranging and integrating the cut LSI chips by a predetermined number N, and the integrated structure has a secondary electrode formed on a surface thereof, On the back side, there is a contactor member in which a probe portion which is opposed to the electrode pad of the chip and supported by a flexible beam is formed, and a contact probe for inspection is brought into contact with the secondary electrode of the contactor member. By pressing the secondary electrode, the probe portion is pressed against the electrode pad of the chip, and the contact probe is electrically connected to the electrode pad of the chip.

(3) A step of forming a plurality of LSIs composed of a plurality of circuit elements on one semiconductor wafer, a step of cutting the wafer into a plurality of LSI chips, and a step of inspecting the cut LSI chips And selecting a LSI chip satisfying a desired standard based on the result of the inspection in this inspection step, and rearranging a predetermined number N of the cut LSI chips. A jig for inspecting a semiconductor device for integration, comprising: a plate-shaped base; a material disposed on the base; and having a linear expansion coefficient substantially equal to that of the LSI chip. A plate-shaped tray accommodating the cut LSI chip, a plate-shaped contactor for electrically connecting the chip accommodated in the tray and an external inspection means, and A lid for accommodating the tray and the contactor between the contactor and a plate-like base; and one surface of the contactor has electrodes of a predetermined number N of LSI chips rearranged in the inspection jig. A probe portion that is locally bendable in accordance with a load for electrically connecting with the portion is provided, and a secondary electrode that is electrically connected to the probe portion is provided on the other surface of the contactor. The tray and the contactor constitute an integrated structure in which the contactor is sandwiched between the base and the lid, and a predetermined portion of the probe portion is provided between the chip mounted inside and the substantially lower surface of the contactor. There is a gap substantially equal to the local deflection.

(4) Preferably, in the above (3),
The contactor and the tray are formed from silicon.

(5) Preferably, in the above (3), the plurality of secondary electrodes provided on the other surface of the contactor are formed at a pitch of 0.5 to 1.5 mm with respect to each other.

By utilizing the integrated structure, a large number of LSI chips cut and separated from the wafer can be rearranged by a predetermined number as appropriate and processed collectively and systematically, and the subsequent inspection process can be performed. Handling in
In particular, it is possible to collectively secure a predetermined number of electrical connections to the inspection system or the like.

This simplifies the steps in the method of manufacturing a semiconductor device, particularly, the inspection step, thereby greatly improving the efficiency, reducing the cost of the inspection step, and reducing the manufacturing cost of the semiconductor device. Becomes possible.

Further, if a secondary electrode is formed on the front surface of the contactor and a probe portion is formed on the back surface facing the electrode pad of the chip and supported by a flexible beam, the contact probe can be formed. By contacting and pressing the secondary electrode, the probe portion is simultaneously pressed against the electrode pad, and the electrical conduction can be ensured.

[0032]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. First,
FIG. 1 is a flowchart showing schematic steps in a method of manufacturing a semiconductor device (partly including a method of inspecting a semiconductor device) according to an embodiment of the present invention. FIG.
(A) and (b) are views showing the form of the semiconductor device in the steps in the above manufacturing method. In the method of manufacturing a semiconductor device according to one embodiment of the present invention, the following steps are performed in the following order.

(1) Pre-process (2) Cutting process (3) Integration process (4) Burn-in process (5) Sorting inspection process Details of each process in the above-mentioned manufacturing method are described below for each process. I do.

(1) Pre-process The pre-process 100 here is an LSI (Large Scale Integration) in which a large number of circuit elements are integrated and formed on a semiconductor wafer 1a (see FIG. Circuit) chip 1b
Is formed by a wafer processing apparatus including a known diffusion device, photolithography device, epitaxial growth device, and the like.

The LSI in the preceding step 100
The formation of 1b is carried out on the wafer 1a, which is obtained by slicing a thin slice from an ingot of single crystal silicon (Si) and mirror-polished the surface, through many unit processes according to the specification of the LSI to be manufactured.

The details are not described here because they are not directly related to the present invention.
-MOS (Complementary Metal)
In the case of Oxide Semiconductor, p-type and n-type formation processes (devices) of the wafer 1a substrate, element isolation processes (devices), gate formation processes (devices), source / drain formation processes (devices), and wiring processes are roughly divided. (Apparatus), a protective film forming step (apparatus) and the like.

More specifically, the wafer 1
In the p-type and n-type formation steps of a, boron (B) or phosphorus (P) ion implantation is performed on the surface of the wafer 1a.
It is then spread on the surface by diffusion.

In the element isolation step, the wafer 1
A silicon oxide film is formed on the surface of a, a nitride film is patterned for region selection, and an oxide film in an unpatterned portion is selectively grown, thereby separating into individual fine elements.

Further, in the gate forming step, a gate oxide film having a thickness of about several nm is formed between the above-mentioned elements, and a polysilicon (poly Si) layer is formed thereon by CVD (Chemi).
The deposition is performed by a cal vapor deposition (cal vapor deposition) method. After that, this deposited layer is processed to a predetermined size,
Thereby, a so-called gate electrode is formed.

In the source / drain formation step, after the formation of the gate electrode, ion implantation of impurities such as P and B is performed, and a source / drain diffusion layer is formed by activation annealing.

Further, in the wiring step, aluminum (A
l) Each element separated above is electrically connected by stacking wirings, interlayer insulating films, and the like.

In the protective film forming step, the intrusion of impurities or moisture from the outside into the fine elements formed on the wafer 1a as described above is prevented, and furthermore, when the chip circuit is packaged later. LSI from mechanical stress
Is formed on the circuit surface to protect the circuit.

One wafer 1a used in the above process has a thickness of several hundred μm and a size of about 6 to 12 inches in diameter. For example, DRAM (Dynamic Rand)
om Access Memory)
About 800 LSI chips are formed.

In this state, the wafer 1
a shows the form shown in FIG. L formed
One size of SI1b is, for example, several mm on one side.
To several tens of mm, each of which is provided with tens to hundreds of electrode pads 1c. In addition, each electrode pad 1c
Is formed as a quadrilateral with one side of several tens of μm.

Here, following the previous step 100 described in detail above, the conventional initial probing inspection step 1
Without performing 00A (see FIG. 9), a cutting process of the wafer 1a on which the LSI is formed is performed. This aims at reducing the cost required by omitting the probing inspection process 100A.

(2) Cutting Step In this cutting step 101, the L formed in the previous step 100 is used.
This is a step of cutting the SI into chip-shaped LSI chips 1b. As a result, the LS cut into chips
The I chip 1b has the form shown in FIG. Then, according to the present invention, following the cutting step 101,
The integration step 102 described below is performed.

(3) Integrating Step In the integrating step 102, the cutting in the cutting step 101 is performed.
In the subsequent burn-in step 103 or the screening inspection step 104, a plurality of separated LSI chips 1b are used as if they were silicon wafers 1a by a predetermined number N.
This is a process for enabling the unit to be integrally handled, similarly to the case where the unit is handled as it is.

That is, a predetermined number N of LSI chips 1b
Are positioned with high precision and their relative positions are restricted. Note that the predetermined number N is a natural number of 2 or more and is smaller than the number of LSI chips 1b cut out from one silicon wafer 1a.

Further, a specific form of the integration step 102 will be described with reference to FIGS. FIG. 3 shows a partial perspective view of an example of an integrated structure which is an integrating means (a jig for integration), and FIG. 4 shows a contactor of the integrated structure, which will be described later. Is shown.

First, in FIG. 3, the integrated structure comprises the base 3, the contactor 5, the tray 4, the elastic body 8, and the lid 9 as respective components. Each of these components is as follows.

(3-1) Base 3 and Lid 9 (3-1a) Materials Generally, the material of the base 3 and the lid 9 is a metal such as a thermosetting resin, aluminum, various stainless steels, etc., which are molded. Ceramic such as aluminum nitride.

(3-1b) Purpose of use LS to be inspected to be mounted between the base 3 and the lid 9
When a predetermined load is applied to the I chip 1b,
Reduction (reinforcement) of warpage (deflection) of contactor 5 and tray 4
Is one of the purposes of use.

Each of the above components and the LSI chip 1
Forming mechanisms for mechanical integration of b (eg, screw holes, locating pins, locating holes, latches) is another use.

Another object of the present invention is to provide a high-precision plane suitable for vacuum suction when positioning and fixing the integrated structure to an inspection system by, for example, vacuum suction.

Still another object of the present invention is to prevent the internal components from falling off when the integrated structure is moved and transported.

(3-2) Tray 4 The number of openings 4a equal to the number N (16 in this example) of the predetermined LSI chips 1b to be integrated is formed in the tray 4 at a predetermined interval from each other. Is done. This tray 4 also
It is also made of Si, which is the same material as the above-mentioned LSI chip 1b, or a metal or ceramic (for example, aluminum nitride or the like) whose linear expansion coefficient is similar.

The opening 4a is formed at a position where the predetermined number (16) of the LSI chips 1b are to be arranged and in a size suitable for the size of the LSI chip 1b.

That is, the cut and separated LSI chip 1b
By being inserted into the opening 4a of the tray 4, the predetermined number (16) of the LSI chips 1b can be rearranged with high precision after cutting and separating.

(3-3) Contactor 5 FIG. 4 shows a state in which the contactor 5 is turned upside down from the state shown in FIG. 3 (or a state where the lower surface is viewed from the back side of the state of the contactor 5 shown in FIG. 3). I have. Assuming that the state shown in FIG. 4 is the front surface of the contactor 5, as is clear from FIG. 4, the contactor 5 is mounted on the back surface by being inserted into the opening 4a of the tray 4 and mounted thereon. Chip 1
A plurality of protruding probe portions 5a are provided at positions corresponding to (matching with) the electrode pads 1c of FIG. FIG. 5 is a view seen from the back surface of the contactor 5, and is an enlarged view of a portion where the probe unit 5a is arranged. As shown in FIG. 5, the probe 5a is supported by a flexible beam 5d. In addition,
The contactor 5 is mounted so that the surface having the probe portion 5a faces the LSI circuit forming surface side of the chip to be mounted.

On the other hand, on the surface of the contactor 5 opposite to the surface on which the probe portion 5a is formed (that is, on the upper surface (see the contactor 5 shown in FIG. 4)), there are formed fine particles penetrating through the inside of the contactor 5. A secondary electrode 5c electrically connected to each of the probe portions 5a is arranged by the wiring 5b (see FIG. 5).

In the structure of the contactor 5, the probe 5a (back surface) and the secondary electrode 5c (front surface) located on opposite surfaces are electrically connected to each other. Although it is necessary to penetrate through the inside of the contactor 5, one embodiment of the present invention is achieved by forming a through hole in the contactor 5 main body, metallizing the inside, and connecting wirings on both sides (through holes).

However, the present invention is not limited to such a structure. In addition, wiring may be provided over both surfaces of the contactor 5 so that the probe 5a (back surface) and the secondary electrode 5c
(Surface) can also be electrically connected.

The contactor 5 is also provided with the tray 4
Similarly to the above, the same material as that of the above-mentioned LSI chip 1b is used.
It is desirable to be formed of i or a metal, ceramic, or the like (for example, aluminum nitride or the like) having a similar linear expansion coefficient.

However, the probe section 5a, the secondary electrode 5c,
Further, when a remarkable accuracy is not required for the fine wiring 5b, it is also possible to form the contactor 5 using an organic thin film such as glass epoxy, ceramic, or polyimide in addition to the above. Would.

(3-4) Elastic Body 8 The elastic body 8 is the LSI chip 1 to be inspected to be mounted.
b. Absolute thickness and multiple LSIs mounted together
When the relative value of the thickness of the chip 1b varies,
It is provided for the purpose of absorbing it.

FIG. 3 shows an example in which the elastic body 8 is formed of a rubber elastic sheet such as Si rubber, and the entire area where a plurality of chips 1b are arranged is covered by a single elastic body 8. However, this may be divided, for example, into units of each chip 1b.
It may be arranged for each.

As described above, a predetermined number (16 in this example) of cut and separated LSI chips 1b to be inspected are again arranged with high precision on the integrated structure formed as described above. The integrated structure including the chip 1b is mechanically integrated. FIGS. 6A and 6B show perspective views of the integrated state from the upper direction and the lower direction, respectively.

As shown in FIGS. 6 (a) and 6 (b), in a state where the integrated structure is integrated after the chip 1b is mounted, it should be particularly noted that each electrode pad 1c on the chip 1b is to be described. With each electrode pad 1 of the chip 1b.
This is that the secondary electrode 5c whose size and arrangement pitch have been greatly enlarged as compared with c is exposed on the surface of the integrated structure.

That is, the integrated structure in one embodiment of the present invention shows that the function as an object in a burn-in process and a screening test performed thereafter is not different from that of the semiconductor wafer 1a. is there. And by using such an integrated structure,
The following effects can be obtained in each of the subsequent burn-in step and screening inspection step.

In particular, L which is relocated within the integrated structure
The opening 4a for accommodating the SI chip 1b therein (that is, the predetermined number N of openings),
b, a contactor 5 for taking out the electrode pad 1c to the outside,
The number can be set appropriately corresponding to an appropriate number (for example, a range of about 10 to 100).

As a result, the number of openings 4a and the like can be adjusted to the number suitable for the processing capacity of the inspection system used in the inspection process performed thereafter, and the optimum inspection processing can be performed. become. For example, as an example,
In consideration of the processing capacity of the inspection system and the substrate for inspection in the current inspection process, the predetermined number N is
For example, it can be set to 32 or 64.

In particular, the secondary electrodes 5c appearing outside the integrated structure (the surface of the contactor 5) (that is, much larger than the dimensions and pitch of the electrode pads 1c)
By using the method, it is possible to easily and reliably perform operations such as electrical continuity between each of the LSI chips 1b to be inspected and the inspection system. The secondary electrode 5c appearing on the surface of the contactor 5 is particularly 0.5 mm
It is desirable to form at a pitch of up to 1.5 mm.

This is because, as a contact probe of an inspection board generally used for inspection, it is excellent in reliability as well as workability by humans, and a contact probe (pitch) having a proven track record. For example,
(Narrow pitch: about 0.5 mm, wide pitch: about 1.5 mm) are used in many cases, so that it is possible to easily and surely cope with such a contact probe.

In addition, by setting the pitch of the secondary electrode 5c to a pitch of about 0.5 mm to 1.5 mm, the following effects can be obtained. here,
First, L in the integrated structure in one embodiment of the present invention.
Consider that the SI chip 1b is most densely incorporated. This is nothing less than incorporating each LSI chip 1b with the gap as small as possible.

That is, it means that the area of the secondary electrode 5c for one chip is not smaller than the area (area) of one chip. For example, the realistic area of a current DRAM is about 1
A 300 mm ² approximately, and because the electrode pad number to be probed for inspection is several tens to about 100, the pitch allowed for the secondary electrode relative to the above-described object (100 mm ^{2/100) 1 / 2} = 1 mm.

That is, setting the formation pitch of the secondary electrode 5c to a pitch of 0.5 to 1.5 mm leads to the effect that the integrated structure in one embodiment of the present invention can be most efficiently used. It is.

Further, by increasing the pitch and the size of the secondary electrode 5c as described above, for example, the inspection system side (particularly, a portion electrically connected to the secondary electrode 5c)
Even when a glass epoxy substrate having a significantly different linear expansion coefficient from the material (ie, Si) of the chip 1b (and the above-mentioned integrated structure) to be inspected is used, a temperature difference between the two may be used. Therefore, even if the two are misaligned, the semiconductor device can be inspected reliably without inconvenience such as disconnection of the conduction state.

In addition, according to the integrated structure, the number of the secondary electrodes 5c provided on the surface of the contactor 5 and the layout of the secondary electrodes 5c have a predetermined margin. Just change the dimensions of the body,
The same inspection system-side substrate can be used for the inspection of different types of LSI chips 1b, and as a result, the inspection cost can be reduced.

(4) Burn-in Step In the burn-in step 103, the LSI chip 1b is heated (applied with a thermal stress) to about 100 to 150 ° C. while simultaneously applying electric power to the LSI formed via the electrode pads 1c. This is a reliability inspection process in which a target stress is given and the chip 1b is left for a predetermined period of time to thereby accelerate and sort out and extract potential defects of the chip 1b.

Here, a burn-in process as a reliability test process will be described as a specific example, but it is apparent that other processes for testing a manufactured semiconductor device may be used. There will be.

In FIG. 8, a plurality (predetermined number N) of LSI chips 1b integrated by the integrated structure of the present invention are printed on their printed circuit boards 6 (burn-in step) in this burn-in step. (A substrate used for this purpose) is shown in a sectional view.

In FIG. 8, the printed circuit board 6 is provided with, for example, a contact probe 6a having a wide pitch (for example, 1.5 mm pitch), while being provided on the surface of the contactor 5 of the integrated structure. Secondary electrode 5
c is also formed at the same pitch.

Thus, the contact probes 6a of the printed circuit board 6 are positioned so that the integrated structures are located at positions corresponding to the corresponding secondary electrodes 5c, thereby providing electrical contact between them. Can be done.

The contact probe 6a is connected to a circuit in the printed circuit board 6, and is finally connected to an inspection system (not shown). As described above, in the burn-in process, the integrated structure and the inspection printed board 6 are fixed to each other in such a state,
The above-described thermal and electrical stresses are applied to the integrated structure.

Note that a predetermined number N
According to the integration of the chip 1b, it is possible to reduce the volume per chip compared to the conventional method in which one chip is mounted on one socket. During the burn-in process, the number of chips that can be inserted into the heating furnace as the heating means increases,
As a result, the inspection efficiency can be further improved.

(5) Screening Inspection Step This screening inspection step 104 is performed, for example, at 25 ° C. to 75 ° C.
This is the final performance inspection process performed at a temperature of about
The inspection is usually performed using an inspection system called a handler based on the result of the burn-in step 103 which is the inspection step.

In the screening inspection step 104, although not shown, although the specifications of the printed circuit board and the inspection system used are different, the inspection form is the same as that of the burn-in step 103 of the above (4). LSI that is the inspection object
This is performed by securing electrical continuity between the electrode pad 1c of the chip 1b and the inspection system.

Therefore, in the screening inspection step 104, a predetermined number N of LSIs are rearranged and integrated by the integrated structure in the same manner as shown in FIG.
The sorting inspection is performed on the chip 1b.

As described above, according to the semiconductor device manufacturing method described in detail above, the integration step 102 for integrating a predetermined number N of a large number of LSI chips 1b cut and separated from the semiconductor wafer 1a. After that, the LSI chip 1b maintains the integrated state until the end of the screening inspection step 104. Therefore, it is possible to manage the inspection results for each chip 1b by the arrangement position (address) in the integrated structure, and also to transfer the chip 1b from the plate-like form of the integrated structure (further, (Especially when this is formed into a disk shape) (by a transport system which is mechanically similar to a conventional wafer transport system), it becomes possible to carry a line between inspection processes.

In the screening test, only the LSI chip 1b finally determined to be non-defective is extracted from the integrated structure at the stage when the integration is released, and for example, reliability is guaranteed. Chip (KGD: Known G)
ood Die) without being packaged.

As described above, in the above-described method for manufacturing a semiconductor device, the mounting or packaging process of the LSI chip 1b to the individual sockets 2 in the prior art is not required, and the accompanying cost is not generated. The pre-process 100 in the conventional manufacturing process (see FIG. 9 described above), that is, an LSI on the semiconductor wafer 1a
It is not necessary to go through a preliminary probing inspection step that was performed after the step of forming the circuit element of
The number of steps in manufacturing a semiconductor can be reduced.

However, this probing inspection step prevents the probing inspection step from being performed if, for example, the production yield is low and it is determined that the probing inspection step is more efficient. is not.

As described above, according to the integrated structure of the present invention, the semiconductor wafer 1a on which a large number of LSIs have been formed in the previous step 100 is cut into units of the respective LSI chips 1b, and is then re-cut by a predetermined number N. Since the arrangement and integration are performed and the processing in the subsequent steps is performed, the processing of the inspection system is compared with the conventional inspection method, in particular, a method in which an LSI chip is mounted on a socket one by one in each step. It is possible to perform inspection processing in an appropriate number of LSI chips in conformity with the capacity, as if the preprocessed semiconductor wafers are intact (although the shape and number of LSI chips are different), that is, systematically collectively. It becomes possible.

As a result, a large number of LSI chips 1b can be efficiently inspected, and when an existing facility or the like is used, the semiconductor device can be inspected efficiently according to its capability as needed. An excellent inspection system that can be performed can be realized.

In addition, a conventional inspection method, in particular, L
According to the integrated structure of the present invention, even when comparing the method of mounting the SI chip alone on the inspection substrate as it is or the method of performing the inspection while keeping the wafer state, the semiconductor device has a plurality of inspections. It becomes possible to handle the LSI chip 1b integrally, and by using the secondary electrode 5c (which is larger than the electrode state of the LSI chip 1b as it is in a wafer state or as a single LSI chip), it is possible to handle the inspection system. Since electrical continuity can be achieved simply and reliably, it is possible to implement semiconductor device inspection at relatively low cost without using expensive fine probe groups and the like.

As described above, according to the integrated structure of the present invention, a large amount of LSI chips 1b can be inspected efficiently and relatively inexpensively, as shown in FIG. In particular, it is possible to omit an initial probing process, which is an initial discrimination process after the pre-processing, which is necessary in the conventional inspection method in which the LSI chip 1b is mounted on the socket 2 one by one in each process.

As is clear from the above description, according to the semiconductor device inspection method of the present invention, a large amount of L
Since the SI chip 1b can be inspected efficiently and relatively inexpensively, the inspection cost is not so large even if the initial discrimination after the pre-processing does not remove the defective product beforehand but also performs the subsequent sorting inspection. By not rising.

Further, according to the semiconductor device inspection method of the present invention, the probing process, which is the initial discrimination process after the pre-processing required in the conventional method, is omitted, thereby further reducing the cost of the semiconductor device. Can be realized as described above.

The above-mentioned integrated structure is not limited to the embodiment described in detail above, but aims to enjoy the effects and advantages described above in various ways.
Therefore, the number and the interval of the chips 1b arranged on the base 3 are arranged so as to satisfy the above-mentioned effects and advantages in consideration of the size and pitch of the secondary electrodes 5c on the surface of the contactor 5 and the number thereof. It is determined on the condition that it can be done.

The number of the LSI chips 1b arranged on the base 3 of the integrated structure depends on the external dimensions and constraints of the integrated structure including the base 3, and / or
Alternatively, it is desirable to be determined on condition that the processing capacity of the inspection system can be utilized to the maximum.

Therefore, the integrated structure according to the embodiment of the present invention obtains a configuration of a pseudo wafer whose specifications are changed so as to make the subsequent inspection easier and more efficient. Although the outer structure of the structured structure is shown as a quadrilateral, according to the present invention, it is not necessary to limit the shape to a quadrangle, and as described above, it is also possible to make the outer shape a circle similar to the wafer 1a, for example. .

In the above description, the probe unit 5 formed on the back surface of the contactor 5 in the integrated structure is described.
c shows only an example in which it contacts the electrode pad 1c on the LSI chip 1b disposed therein.
The purpose is to achieve electrical continuity between the LSI chip 1b, which is a subject, and the inspection system, and is not necessarily limited to the above-described configuration.
It may be one that comes into contact with a solder ball or the like provided on b.

By the way, the electrode pad 1c of the chip 1b
In order to establish electrical continuity with the probe section 5a, that is, the contactor 5, the probe section 5a must be
It is necessary to press on c. According to our measurements,
In the case of the contactor 5 made of Si, a pressing load of at least about 3 to 10 gf was required.

Therefore, for example, the integrated chip 1
Assuming that the predetermined number N of b is 16 and the number of electrode pads 1c to be pressed in each chip 1b is 80, the pressing load of the entire integrated structure reaches about 7 kgf. If the internal force acts in a state where the integrated structure is integrated, there is a possibility that the integrated structure, particularly the contactor 5, may be bent or broken. Therefore, when designing and manufacturing the integrated structure according to one embodiment of the present invention, it is desirable to perform the design under the following dimensional conditions.

The dimensional conditions will be described with reference to FIGS. 7 and 8. FIG. 7 is a partial sectional view of the integrated structure after integration. Here, the tip of the probe section 5a is in contact with the electrode pad 1c of the chip 1b, and each component of the integrated structure and the chip 1b are in a positionally stable state.

In this state, the pressing load of the probe portion 5a on the electrode pad 1c has not reached the load value (3 to 10 gf) necessary for the conduction, and therefore, an excessive internal force is generated in the integrated structure. I haven't. For this reason,
There is no inconvenience that excessive bending or the like occurs in each component including the contactor 5. Therefore, stable conduction between the electrode pad 1c and the probe section 5c has not been obtained.

On the other hand, FIG. 8 shows that, as shown in FIG. 7, the integrated integrated structure is mounted in an inspection system, and the secondary electrode of the integrated structure is mounted by a contact probe 6a of the inspection system. It is a figure which shows the state at the time of probing 5c and performing an inspection.

In this state, the contact probe 6
a presses the secondary electrode 5c, the probe 5a of the contactor 5
The electrode pad 1c is elastically deformed by being pressed by the electrode pad 1b. Then, the gap h between the tip 1b and the contactor 5, which has existed in FIG. 7, is eliminated, and the beam 5d of the probe portion 5a is flexed accordingly. As a result, the beam 5 of the probe 5a
A pressing force is applied to the electrode pad 1c of the probe portion 5a in proportion to the deflection of d, and a load required for conduction between the two is generated.

Here, in the state shown in FIG. 7, that is, before the contact probe 6a comes into contact with the secondary electrode 5c, the probe section 5a does not necessarily come into contact with the electrode pad 1c of the chip 1b. Good.

As described above, the contact probe 6a
When the probe contacts the secondary electrode 5c and presses the secondary electrode 5c, the beam 5d of the probe section 5a bends.
This corresponds to the protruding distance of the probe portion 5a from the beam 5d.

The above-described probe section 5a and electrode pad 1c
For example, when the contactor 5 is formed of Si, the pressing force value 3 to 10 gf necessary for conduction with the electrode pad 1 c
Probe array 5a when the arrangement pitch of
The length of the flexural deformation area is 1 to 1.4 mm and the thickness is 40
By setting the size of about μm and the gap h to a size of about 10 μm, it is possible to provide a good condition.

The integrated structure according to one embodiment of the present invention includes an elastic body 8, and when the contact probe 6a comes into contact with the secondary electrode 5c and presses the secondary electrode 5c, The elastic body 8 also bends, but the amount of the bend is an amount that does not interfere with ensuring good electrical conduction between the probe portion 5a and the electrode pad 1c.

As described above, according to the integrated structure of one embodiment of the present invention, the secondary electrode 5c is formed on the surface of the contactor 5, and the electrode pad 1c of the chip 1b is formed on the back.
Probe section 5a which is opposed to and supported by flexible beam 5d
Is formed, the contact probe 6a contacts and presses the secondary electrode 5c, thereby simultaneously pressing the probe portion 5a against the electrode pad 1c, thereby securely connecting the contact probe 6a and the electrode pad 1c of the chip 1b. Can be made electrically conductive.

[0114]

As described above, according to the present invention, by using an integrated structure, a large number of LSI chips after cutting and separating from a wafer are appropriately rearranged by a predetermined number and collectively integrated into a system. It is possible to process it matically, and the handling in the subsequent inspection process, especially the securing of electrical connection to the inspection system etc., is performed collectively by a predetermined number without using a conventional socket etc. It is possible to do.

As a result, the steps in the method of manufacturing a semiconductor device, in particular, the inspection step thereof are simplified, the efficiency is greatly improved, the cost of the inspection step is reduced, and the manufacturing cost of the semiconductor device is reduced. Becomes possible.

That is, according to the present invention, it is possible to realize a method of manufacturing a semiconductor device which can guarantee high reliability at low cost.

Further, according to the present invention, it is possible to realize an inspection jig in a method of manufacturing a semiconductor device which can guarantee high reliability at low cost.

Further, according to the present invention, the secondary electrode is formed on the front surface of the contactor, and the probe portion which is opposed to the electrode pad of the chip and is supported by the flexible beam is formed on the rear surface. Then, when the contact probe comes into contact with and presses the secondary electrode, the probe portion is simultaneously pressed against the electrode pad, and the electrical conduction can be reliably performed.

[Brief description of the drawings]

FIG. 1 is a flowchart showing schematic steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of a semiconductor device in a step of the manufacturing method of FIG. 1;

FIG. 3 is a partial perspective view of an example of an integrated structure which is an integrated means according to the present invention.

FIG. 4 is a diagram showing the back surface of the contactor of the integrated structure according to the present invention.

FIG. 5 is an enlarged view of a portion where a probe unit is arranged, as viewed from the back surface of the contactor according to the present invention.

FIG. 6 is a perspective view showing a state in which the integrated structure according to the present invention is integrated.

FIG. 7 is a partial cross-sectional view after the integration of the integrated structure according to the present invention.

FIG. 8 is a diagram showing a state when an integrated structure according to the present invention is mounted in an inspection system and an inspection is performed by a contact probe.

FIG. 9 is a flowchart schematically showing a manufacturing process of a conventional semiconductor device.

FIG. 10 is a view showing various modes of a semiconductor device manufactured by a conventional semiconductor device manufacturing process.

[Explanation of symbols]

 1a Wafer 1b LSI chip 1c Electrode pad 2 Socket 3 Base 4 Tray 4a Opening 5, 5e Contactor 5a, 5f Probe 5b Wiring 5c Secondary electrode 5d Beam 6, 10 Printed circuit board 6a, 11 Contact probe 7 Reinforcement 8 Elastic body 9 Lid

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroyuki Ota 502 Kutachi-cho, Tsuchiura-city, Ibaraki Pref. Machinery Research Laboratory, Inc. (72) Inventor Masatoshi Kanamaru 502-Kindachi-cho, Tsuchiura-City, Ibaraki Pref. Inside the Machinery Research Laboratory (72) Inventor Atsushi Hosogane 502, Kandachicho, Tsuchiura-shi, Ibaraki Pref. Inside the Machine Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshie Endo 502, Kunitachi-cho, Tsuchiura-shi, Ibaraki Pref. (72) Inventor Akihiko Ariga 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Naoto Ban 5--20-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. F-term in the semiconductor group of the factory (reference) 2G003 AA07 AA08 AA10 AC01 AD02 AF05 AF06 AG03 AG11 AG12 AG14 AG16 AH02 AH04 2G011 AA02 AA03 AA16 AB01 AB06 AB08 AB10 AC06 AC14 AC21 AE03 AF06 4M106 AA02 AD08 AD09 BA14 CA56 CA60 DJ33

Claims (5)

[Claims] A step of forming a plurality of LSIs each including a plurality of circuit elements on a single semiconductor wafer; a step of cutting the wafer into a plurality of LSI chips;
A method of manufacturing a semiconductor device, comprising: a step of inspecting an I chip; and a step of selecting an LSI chip satisfying a desired criterion based on a result of the inspection in the inspection step. And a predetermined number N of cut-off LSI chips integrated in the integration step are integrated and subjected to at least a predetermined inspection process in the inspection step. Manufacturing method of a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the inspection step is performed by using an integrated structure for rearranging and integrating the cut LSI chips by a predetermined number N. The integrated structure has a contactor member having a secondary electrode formed on a front surface thereof, and a contactor member formed on a rear surface thereof and opposed to an electrode pad of a chip and having a probe portion supported by a flexible beam. By contacting a contact probe for inspection with the secondary electrode of the member and pressing the secondary electrode, the probe portion is pressed against the electrode pad of the chip, and the contact probe and the electrode pad of the chip are pressed. And a method for manufacturing a semiconductor device, wherein 3. A step of forming a plurality of LSIs comprising a plurality of circuit elements on a single semiconductor wafer; a step of cutting the wafer into a plurality of LSI chips;
A predetermined number N of cuts used in a method of manufacturing a semiconductor device, comprising a step of inspecting an I chip and a step of selecting an LSI chip satisfying a desired standard based on a result of the inspection in the inspection step. A jig for inspecting a semiconductor device for relocating and integrating an LSI chip, comprising: a plate-shaped base; and a material arranged on the base and having a linear expansion coefficient substantially equal to that of the LSI chip. A plate-shaped tray accommodating the predetermined number N of cut LSI chips, a plate-shaped contactor for electrically connecting the chips accommodated in the tray and external inspection means, at least the tray And a lid for accommodating the contactor between the contactor and the plate-shaped base. A predetermined number N of LSs rearranged in the inspection jig are provided on one surface of the contactor. A probe portion which is locally bendable according to a load for electrically connecting to the electrode portion of the chip is provided, and the other surface of the contactor is electrically connected to the probe portion. A secondary electrode is provided, and the tray and the contactor constitute an integrated structure in which the probe and the contactor are sandwiched between the base and the lid. A jig for inspecting a semiconductor device, wherein a gap substantially equal to the predetermined local deflection amount exists. 4. The jig for inspecting a semiconductor device according to claim 3, wherein said contactor and said tray are formed of silicon. 5. The jig for testing a semiconductor device according to claim 3, wherein the plurality of secondary electrodes provided on the other surface of the contactor are formed at a pitch of 0.5 to 1.5 mm from each other. A jig for testing a semiconductor device.