JP2000513887A - High-speed CCD imaging, image processing, and camera system - Google Patents

Abstract

(57) [Summary] A solid state imaging array has a plurality of analog memory cells that operate linearly and continuously, and is constituted by an array of imaging photosensitive units (202). The captured image charge signal is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION Cross Reference of High Speed CCD Imaging, Image Processing, and Camera System Related Applications This application describes the benefits and benefits of US Provisional Application No. 60 / 017,035, pending May 3, 1996. Claim priority. GOVERNMENT RIGHTS This invention was made with government support under Contract F08630-96-C-0066 commissioned by the Department of Defense. The government has rights in the invention. BACKGROUND OF THE INVENTION The present invention relates generally to ultrafast imagers, optical processors, and electronic camera systems. More particularly, the invention relates to an electronic imaging system capable of capturing electronic images at an image frame rate of, for example, up to one million image frames per second or more, and a more compact analog storage capability and / or processing of captured images. The present invention relates to a camera system having capability. There is a need for economical, ultra-fast electronic imaging in a variety of scientific, commercial, and military applications. Ultrafast electronic imaging and sensors with recording speeds of one million frames per second or more can be used in the fields of molecular physics, high-speed physical chemistry, industrial process control, medical biology, high-resolution long-distance imaging telescopes, and combustion flows. It is basically desired to enable applications. Unfortunately, current electronic detectors are not sensitive enough and are relatively slow or expensive. For example, currently available high resolution electronic imagers, such as commercially available CCD image sensors made of silicon, have a medium to large number of output channels (eg, at least 512 × 512 pixels) with a medium number of output channels (eg, 32). ), The practical speed limit is on the order of thousands of frames per second. High speed semiconductor devices, such as high speed semiconductor devices such as bump GaAs output circuits, are expected to have some improvement in electronic imager frame rate speeds, but higher frame rates require newer imager designs and geometries. There will be. In the past, providing a high effective frame rate has typically employed multiple imagers in a multiplexed assembly or using a high speed film system. In this regard, various ultrafast cameras are based on rotating prism / mirror assemblies and have inherent mechanical delays in starting and synchronizing. These systems are large, inflexible, expensive, and have various disadvantages. For example, achieving high rotational speeds of the mirror / prism assembly requires purging the camera housing with helium to reduce drag, and manufacturing the prism from relatively fragile beryllium, which is a health aspect. May be harmful. Due to the mechanical inertia involved, such a camera system would be limited (rather than triggered by an event) to trigger the event being imaged, providing only a fixed inter-frame period It is typical to do it. The mechanical "spin-up" time required for the camera to reach steady state makes it difficult to trigger the camera asynchronously based on the event being imaged. This also makes it difficult to trigger multiple cameras simultaneously for stereo image capture. Combining the user selectable period between frames with asynchronous triggering and fast gating allows acquisition of image data with high temporal resolution, and provides stereo photography using a common precision trigger of multiple cameras. Providing control of electronic image exposure independent of the imaging frame rate provides more flexibility in tailoring camera performance to imaging needs in specific imaging applications. However, at an ultra-high imaging speed, it is difficult to achieve independent control of shutter and frame rate with high image quality. Management and storage of image output data from ultra-high speed imagers is also a problem at this time. For example, when a camera of 1K × 1K pixels is operated at one million frames per second, image data shooting and memory requirements become enormous. The image data digital output rate of a 1K × 1K pixel imager operating at one million frames per second is one terabyte per second, exceeding the capacity of currently available digital storage systems. SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a high speed electronic imager capable of high frame rates, for example, imaging frame rates up to one million frames per second or more. A further object is to provide an imager and camera system having a new and effective geometry and capable of efficient imaging. It is a further object of the present invention to provide an independent choice of frame rate and exposure time at such very high frame rates. It is yet another object of the present invention to provide compact image storage for ultra-high speed image capture. In general, the present invention is capable of very fast image capture, and includes an electronic image sensor including a high speed analog memory partially linearly tied to the imaging pixels of the high speed imager for storing images of a plurality of captured continuous images, and It relates to an electronic camera system. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects of the present invention will become apparent from the following detailed description and the accompanying drawings. In the drawings, FIG. 1 is a schematic block diagram of an embodiment of a CCD imaging system using an ultra-high frame rate low fill factor CCD imager having a plurality of analog memory sections directly linearly associated with each photodetector. . FIG. 2 is a schematic plan view of one embodiment of an ultra-high frame rate CCD imager that can be used in an imaging system such as the system of FIG. FIG. 3A is a schematic top view of a portion of the imager of FIG. 2, showing the spacing of active photoreceptors for partially linearly associated memory storage cells. FIG. 3B is a schematic plan view of another photoreceptor and partial memory geometry of the imager of FIG. FIG. 4 is an enlarged plan view of one of the photosensitive units of the imaging / array of FIG. FIG. 5 is a cross-sectional view of the active photosensitive section of FIG. 4 along the horizontal column direction of FIG. FIG. 6 is a cross-sectional view of the active photosensitive section of FIG. 4 along the vertical transfer direction. FIG. 7 is a schematic top view of a 3D stacked CCD sensor for an ultra-high speed imager with greatly expanded analog memory directly related to each imaging photoreceptor. FIG. 8 is a 3D stacked array of the edge and imaging CCD sensors of FIG. 7 with 1K buffered CCD channels forming a compact 2D imager and 3D analog memory system. FIG. 9 is a bump-mounted high-speed CCD imaging system with expanded 3D memory and / or processing capability. FIG. 10 is a cross-sectional side view of a multiple SOS imager bump mounted on a CCD wafer stack of the type shown in FIG. FIG. 11 is a schematic cross-sectional side view of a "pillar-recess" z-axis and y-axis positioning system for a 3D image sensor and memory assembly, such as the assembly of FIG. 8 or FIG. FIG. 12 is an ultra-high-speed stereo photography system using a plurality of simultaneously-triggered ultra-high-speed cameras of the present invention. FIG. 13 is a schematic top view of a large format 4096 × 4096 storage cell / pixel CCD imager with full frame architecture suitable for ultra-high speed imaging. FIG. 14 is a top view of an ultra-high speed CCD imager with a 4-phase high conductivity parallel transfer electrode bus system. FIG. 15 is a schematic plan view of a portion of an ultrafast imager similar to the imager of FIG. 3A suitable for color imaging. DETAILED DESCRIPTION OF THE INVENTION In general, the present invention includes an array of imaging sensitizers, in part related thereto, a plurality of linearly-contiguous serially-stored image charge signals for storing successively captured image charge signals from each sensitizer. The present invention relates to an electronic imaging system including a plurality of analog memory cells that operate in a dynamic manner. In general, the photoreceptor array is preferably a two-dimensional array of 1000 active photoreceptors regularly arranged in a two-dimensional array, and is configured as a regular two-dimensional array of at least 200,000 active photoreceptors. Is more desirable. As mentioned above, the photoreceptor has a plurality of continuously operating analog memory cells, each partially connected. "Partially tied" is the photosensitive portion of each of the regularly arranged imaging arrays, e.g., at least four, preferably at least ten, and preferably at least ten using CCD charge transfer channels. It means 64 analog memory cells for each photosensitive section which are connected linearly adjacently and can be transferred continuously. Furthermore, analog memory cells that are linearly associated with adjacent photoreceptors are preferably located adjacent along the charge transfer channel, and analog memory cells that are partially associated with linearly adjacent photoreceptors. A group of memory cells can also be transferred and read continuously. High speed operation is preferably generated by the photoreceptor at a rate of at least about 100,000 image samples per second, preferably at a rate of at least 200,000 image samples per second, and most preferably at a rate of at least 1,000,000 image samples per second. Each photosensitive section is directly connected to at least 16 consecutively operated analog memory cells capable of receiving and storing successive charge signal samples. In a preferred embodiment, groups of analog image signal storage cells partially associated with each photoreceptor are linearly and continuously arranged along a continuous CCD charge transfer channel. Each group of linearly adjacent photosensitive area analog image signal storage cells is regularly and continuously arranged along the transfer channel such that a group of image signals partially linearly associated with adjacent photosensitive sections. The data can be read from the transfer channel in the same relative order. Preferably, all of the analog image storage cells are shifted in parallel on a common transfer electrode array, and the array is a three or four phase electrode transfer clock system. Solid state CCD imagers conventionally use a regularly arranged array of photodetectors to generate and collect charge upon exposure. The amount of charge collected as a charge packet by the light detection unit corresponds to the intensity of the image and the integration time at each photosensitive unit position. These charge packets are periodically transferred from the imager for digitization and further processing. The electronic imager sensitizer may be an analog, such as a surface channel or buried channel charge coupled device (CCD) or other charge transfer device (CTD), a charge injection device (CID), or other optical sensor array, as described in detail below. Used in various optical sensor systems that can partially relate memory. While imaging sensitizers designed for the visible light spectrum (e.g., wavelengths of 400-700 nanometers), such as silicon photodiode imagers, are particularly desirable, the method and apparatus of the present invention is directed to silicon and other semiconductors, e.g. Using Group V and II-VI materials, infrared (e.g., 0. It is also useful for imaging in the far-infrared (eg, 15-25 μm, or 15-100 μm wavelength), ultraviolet (eg, 100-400 nanometer wavelength) spectral range. Although various imager types are known and used in various wavelength ranges, such imagers can be used to provide an active photoreceptor detector at that wavelength according to the present invention. Charge coupled devices with buried charge transfer channels are particularly preferred when used in the sensor geometry of the present disclosure because of their high speed operation and compact, continuous memory storage capability. Provided are CCD and associated camera devices and output electronics capable of very high frame rates, good pixel uniformity, and low noise when used with the imager geometry and method of operation of the present disclosure. A fast charge injection device (CID) and a CMOS photoreceptor can also be used as an edge sensitive photoreceptor for an electronic imager, particularly a 3D stack of imaging memory chips described below. Such devices include a linear array of photosensitive capacitor elements at the edge of the chip. Image readout involves storing the pixel image charge on one electrode and measuring the potential generated on the other electrode when transferring a charge packet to the other electrode for transfer to a continuously linked extended CCD memory. (For a description of the CID imager, see Zarnowski et al. , SPIE vol. 1447 (1991) Charge Coupled Devices and Solid State Optical Sensors II, pp. 191-201; Carbone et al. , Same SPIE vol. 1447, pp. 229-237). CTD and CID also perform sampled image input by performing partial pixel level image subtraction and other partial neighborhood operations according to the charge mode of each pixel. The photosensitive section array desirably has at least an effective fill factor of 75% when a convex lens array or lenslet array (for example, a diffractive optical system or a diffraction grating) is provided. It is desirable to optimize the design of optical lens systems and electronic imager systems to provide a suitable balance between resolution and aliasing (C. S. Bell, Lens Evaluation for Electronic photography, SPIE vol. 1448 (1991) pp. 59-67). In this regard, the limiting resolution and the inherent alias characteristics of the image sensor should be best designed to correspond to the characteristics of the lens system. As a result of aliasing and / or blurring, large amounts of image information are lost in conventional imaging systems even under optimal conditions. A minimum of two pixels are required for detecting the modulation contrast of the image (note that each individual grid pixel can generate an image edge extension value of the image at the image grid location according to the present invention) and the Nyquist of the sensor array The frequency limit will be approximately inversely proportional to twice the pixel repeat distance. Aliasing, an interference effect, can occur in imagers with image information at frequencies (spatial resolution) higher than the Nyquist limit. Optical blur has traditionally been used in single frame imagers to reduce (or match) the spatial frequency resolution of the lens to that of the imaging system. In systems that perform color sampling, optical pre-filters that provide different amounts of blur or smear with different colors optimize the lens system for images at each wavelength sensitivity in a conventional manner. To provide resolution enhancement, imagers are conventionally used in an image scanning mode in which a continuous image is created after shifting the imager by a pixel width within the image field ("step and repeat" or "fine"). "Scan" operation). Imagers used to increase image resolution in this manner are also intentionally designed to have a low fill factor (J. Milch, “High Resolution Digitization of Photographic Images With An Area Charge-Coupled Device (CCD) Imager”, Applications of Digital Image Processing, Proc. SPIE 697, pp. 96-104 (1986); Kontron Commercial Camera). Therefore, the method and apparatus of the present disclosure use a system that shifts the output frame of the photosensor portion of the ultrafast imager at high speed to form a high resolution composite image. Illustrated in FIG. 1 is an ultra-high speed electronic camera system 100 that incorporates a relatively large conventional frame transfer or full frame CCD imager with specialized photomask and modifications to the photoreceptor architecture. And high-speed imaging operation can be performed. Large pixel count CCD sensors such as those used in the system of FIG. 1 are typically designed for relatively slow frame rate applications, such as from about 1 to about 60 image frames per second. While all columns of image data were conventionally shifted in parallel at high speed (eg, a million shifts per second along a vertical transfer register), the conversion of a parallel data stream to a serial output via a small number of output circuits (eg, In specialized systems, 32 or more channels can be used, but typically 1 to 4 output channels) limit the framer / imaging speed of the imager. 5K × 5K or larger CCD imagers (eg, 2500 to 60 million pixels) are conventionally possible with full frame architectures. As schematically shown in FIG. 1, the ultra-high-speed imaging system 100 includes a lens 102, a photoelectric shutter and lenslet system 104, a high-speed CCD image sensor 106, a CCD image sensor 106, and an electronic device for the photoelectric system 104. And a drive control system 108. Lens 102 is any suitable camera lens for effectively focusing a coherent or incoherent image or optical transform on the focal plane of imager 106. Optional photoelectric system 104 includes a high speed photoelectric shutter, such as a Kerr cell, and / or a lenslet / array to increase the effective fill factor of high speed CCD image sensor 106, as shown in FIG. It will be described later in detail with reference to FIG. The electronic drive control system 108 also provides a substantially conventional design to provide drive and output signal processing to the imager 106, and when used in combination with imager modifications as described below with reference to FIGS. Provides image frame rates in the order of one million frames per second in a continuous frame sequence. The CCD drive control system 108 generally includes a vertical (parallel) shift register drive circuit, a horizontal shift register drive circuit, a data output A / D conversion and memory circuit, a CCD bias circuit, a specific CCD imager (for example, a CCD imager and its connected individual). (See Thomson-CSF Semiconducteurs Specifiques 1996 Product Sales Catalog "CCD Product 1996" for identification information, register drive and readout voltage and timing diagrams, CCD camera / drive kits, which are incorporated herein by reference.) And other circuits suitable for controlling the Shown in FIG. 2 is a large format frame transfer 1024 × 1024 CCD imager 106, which features a parallel architecture that is easy to drive and collect output data. The imager 106 is packed closely with 1024 × 1024 photosensitive pixels having a cell size of 14 μm × 14 μm. The 1024 × 1024 pixel imaging area is located along a conventional vertical shift register adjacent to the light-shielded frame transfer memory area. In this conventional design, the entire 1024 × 1024 pixel image frame is placed about 1. 1. To transfer 1024 lines of image from a parallel frame transfer rate of 3 MHz or an image area along the vertical transfer column of the device, a 0. It is transferred at a high speed within 001 seconds. The shielded frame transfer memory area has 4 parallel outputs, each operating at a maximum data rate of 20 MHz, and a full chip output rate up to 60 Hz (made of 1024 x 1024 memory cells) at 10-12 bit gray scale resolution. I will provide a. Other unique on-chip capabilities include anti-blooming and exposure time control. The illustrated device 106 is a THX7887A type CCD imager, commercially available from Thomson CSF Semiconductors, which conventionally operates at up to 60 frames per second, but is modified with dedicated light shielding and operating methods to exceed one million frames per second. It provides a structure for performing ultra-high-speed imaging at a frame rate. As shown in FIG. 2, the CCD imager 106 has a 256 × 255 pixel image frame size of approximately 1.times. A square frame transfer area array CCD imager specially designed to capture up to 16 images at frame rates up to 3 megaframes. Special modifications include metal masks on opaque imaging areas other than the precise array pattern of pixel apertures, allowing ultra-high speed operation of the imager. The imager 106 itself has the same storage capacity as an imaging area 202 of approximately one million pixels formed of 1024 × 1024 square pixels (14 μm × 14 μm) formed along a vertical CCD shift register (in the direction of the arrow). , And can perform simultaneous control reading of analog data in the memory area. Image area 202 consists of 1044 horizontal lines (columns) and includes 1024 pixel lines, five dark reference lines at the top of array 202 and five dark reference lines at the bottom. An auxiliary line is used as a separation line for dark reference integrity. The optically inactive memory area 204 has the same number of lines as the imaging area. To increase the output rate of memory area 204, the imager has four outputs 206, 208, 210, 212, each receiving an analog charge packet from one quarter (256 columns) of the 1024 CCD transfer columns. . Therefore, the imaging and high-speed frame storage area 202 and the memory area 204 can be considered to be functionally divided into 256 CCD transfer channels, respectively. The imaging and high-speed frame storage area 202 itself, together with the high-speed transfer clock of the CCD transfer channel of the imager, performs high-speed imaging of 16 frames of an image size of 256 × 255 pixels by special masking of another actual imaging area of the imager. Specially designed to allow. A plan view of a portion 300 of the imaging and high speed frame / partial / analog memory storage area 202 of the CCD imager 106 is schematically illustrated in an enlarged form in FIG. 3A. As shown in FIG. 3A, the active pixel cells 302, 304 are configured in a conventional vertical CCD transfer channel toward the memory area 204 (not shown) of the frame transfer imager 106 in the direction of the arrow. Each of the cells 302, 304, according to conventional methods (see FIGS. 4-6), is typically an active photoreceptor for imaging via each of the four phase vertical transfer and register electrodes of the imager 106. . However, other conventional CCD imagers 106 are modified by a special opaque metal mask 306, shown with a dark grid pattern covering most of the photosensitive area 304. In the illustrated embodiment 300, only 1/16 of the cells are not masked with the opaque aluminum layer. The pixel openings in the mask layer 306 form the active photosensitive areas 302 and are evenly spaced on the surface of the imager (approximately 4 cells apart in the vertical and horizontal directions). Displaced at an angle to the direction, the charge collected on photoreceptor 302 travels vertically along transfer channel 310 via “opaque” storage cell 304 before reaching another active photoreceptor 302. To be serially shifted in the direction of 15 lines. As shown in FIGS. 3A and 3B, the active photosensitive units 302 are arranged at equal intervals along the two axes at predetermined intervals, and at least one of the axes is provided in the vertical (parallel) transfer register 310 of the CCD 106. It is arranged to rotate with respect to the longitudinal direction. This results in a linear shift of the image data from each photo-sensitive section, generally at a predetermined spacing between the active photo-sensitive sections 302 along the transfer / channel direction before reaching another active photo-sensitive section 302. Move forward by multiples. The predetermined spacing generally corresponds to the total number of pixels / memory cells 302, 304 in the direction of each axis, and may be different for each axis of the photosensitive array. As shown in FIGS. 3A and 3B, the multiple of the spacing along the transfer channel direction is a function of the integer cell spacing along the other axis of the photoreceptor array. Therefore, the photosensitive unit and the storage cell structure shown in FIG. 3A can capture and store 16 images. If the photosensitive units are separated by 8 cell units along each array axis, the imager will be able to capture and store 64 images, but the number of active pixels in the imager will be 4 pixels apart. It becomes 1/4. Because the charge packets are transmitted at very high speed along the transfer channel (eg, at a four-phase clock rate of 1 MHz or more due to the conventional frame transfer operation of a THX7887A CCD imager and camera device circuit), the imager design 300 requires the Extremely high-speed imaging can be realized while transferring images. As shown in FIG. 3, the continuous 16 images are interleaved, and the more recent the cell 16 becomes the first image, the more the cell 15 becomes the second image and the more the cell 1 becomes, the more recent the image becomes. The 16 images captured and stored in the high-speed frame storage area 202 are clocked into the memory area 204 for subsequent reading using a conventional electronic camera CCD drive output circuit of a Thomson 7887A CCD imager chip. Is done. In operation, under control of the electronic drive control system 108, the ultra-high speed camera system 100 is initially in the closed position with the shutter 104 closed, and the four-phase transfer electrode is in a non-transfer mode, in a stopped state, ready to accept imaging. . At least two, and preferably three, of the four electrodes are at an electron deficient potential to maximize the image signal charge storage capacity of the photoreceptor. Preferably, prior to imaging, the anti-blooming gate and drain are activated to remove unwanted image signals. To capture images at high speed in a relatively simple mode of operation, the system 108 opens the shutter 104 and / or activates the illumination of the event to be captured to at least 50,000 frames per second (or vertical shift). Up to 16 cycles of parallel vertical transfer along the vertical register 310 of the imaging area 202 at a vertical shift rate corresponding to the desired imaging rate from 1 to one million or more frames per second. Drive. The start of the transfer cycle is within one-fourth of the cycle time and is accurately triggered by conventional imager driving methods. Anti-blooming and drain gate stop during imaging. The THX 7887A imager 106 is designed to operate at vertical shift rates up to 1.3 million cycles per second (vertical shift). The maximum number of images that can be picked up at high speed is limited to the number of memory cells that are partially associated with each active photoreceptor, here sixteen. The vertical clock shift cycle stops, during which the image data is held in each storage cell. With the shutter or field illumination turned off, the composite image is recorded in the frame storage area 204, from which it is read with high accuracy by conventional methods. The individual images are precisely located in the composite image and can be easily "sorted" or separated into digital memory in any suitable way. Imaging is performed so as to generate a uniform frame rate such that the exposure time is the reciprocal of the frame rate as described above, but other imaging modes can be used. For example, if desired, the exposure time for each image can be separately programmed and cycled. In this regard, referring to FIG. 3A, the first transfer cycle time is 1 μs, the second through fifth cycle times are 5 μs, and the remaining sixth through sixteenth cycle times are 10 μs. The corresponding exposure time has been reached. Similarly, the camera can be operated to provide independent control of the frame rate and the exposure time, so that the image exposure time can be less than the reciprocal of the frame rate. For example, a first image may be shifted at a first rate (eg, 1 μsec) and a second image may be held for a predetermined exposure time (eg, 9 μsec) before shifting the image again at 1 μsec, followed by The third image is shifted at the first (1 μs) rate, and the fourth image is clocked by the CCD vertical transfer with an exposure time of 9 μs, and so on. By alternating the image of the first exposure time and the image of the second exposure time, it is possible to alternately discard the images and provide desired exposure control. In the disclosed embodiment, the effects of imaging 100,000 frames per second with either 1 μs or 9 μs exposures are provided in a fully programmable and user-selectable manner. The penalty is that half of the image is discarded and the corresponding storage area of the imager is not used directly. However, this is a very powerful feature of the present disclosure and requires an imager custom chip that can be programmed via the imager's clock control, such as a very large interline transfer CCD with independent gate sensitization. do not do. The active photoreceptor array of FIG. 3A has a row of photoreceptors arranged such that the linear shift of charge packets to linear memory cells partially tied to the active photoreceptor is extended. It is not a square pixel array. FIG. 3B is an active photoreceptor distribution showing a square active pixel array, but both axes of the array are rotated with respect to the vertical charge transfer channel 310. In this arrangement, the continuous active photoreceptor 302 is separated by approximately 4 cells, but is rotated horizontally and vertically relative to a square grid aligned with the CCD transfer channel (the structure of FIG. 3A). It should be noted that the active photoreceptor is rotationally shifted in one direction only) and that the imager can store 17 high-speed continuous images instead of 16 images. A similar pattern can be provided to further increase the number of consecutive images that can be continuously captured and stored in an analog memory cell partially adjacent to the active photoreceptor. For example, an array of regularly arranged photoreceptors similar to FIG. 3A but with active portions separated by 8 cells provides an array in which the analog charge is shifted 64 times before hitting another active photoreceptor. Yes, so the system can capture 64 consecutive images at a very fast image frame rate. The active photoreceptors are located in both the horizontal and vertical directions and are separated by approximately eight cells, thereby increasing a square array similar to the array of FIG. 3B to 65 consecutive image frames. As described above, the resolution of each image frame becomes approximately 1/4 if the same number of cells are used. This uses a larger imager, such as, for example, a 2024 × 2024 or 4048 × 4048 cell imager, to provide an expanded number of image frames while maintaining the desired image resolution. The imager 106 outputs 16 (FIG. 3A) or 17 (FIG. 3B) image frames stored in the frame memory output area 204 at a rate (fps) of up to 60 frames per second in the conventional manner of this chip. Used to This frame rate is obtained through four parallel area arrays of 256 (vertical) by 1204 (horizontal) pixels each ending at its own serial CCD readout register 206, 208, 210, 212. The four parallel output amplifiers provide data signals to the control unit 208 at a maximum data rate of 20 MHz (20 MHz × 4 for the entire array). The output data is digitized and stored in the digital memory of the control unit 108, where the individual images are separated. At one million frames per second operation, an electronic image of the photon flux incident on the unmasked photosensitive area is sampled by the pixel array during a very short time interval. An electronic shutter on the chip is available but not required during this period. However, if it is desired to operate the chip at a slower frame rate, the anti-blooming gate is clocked at the shutter level voltage, damping unwanted optically generated charge towards the anti-blooming drain. . After capturing 16 frames at a continuous uniform rate or at a programmed variable rate, the composite electronic image shifts very rapidly from the imaging area to the memory area. During this period, the photoelectric shutter 104 is turned off, the illumination is turned off, or the electronic shutter on the chip is used if available. In this way, all the charge packets representing the pixels of one exposure image out of the 16 images shot at high speed consecutively are all transferred to the memory area 204 in the same order. The memory area 204 can be shifted, independently of the imager area, on a scan line basis to four serial CCD registers, each terminated by an output node (floating diode). These output nodes are simultaneously reset to the reference voltage level VDR before receiving a charge packet from the next CCD serial shift register stage. These potentials are permanently detected by a double-stage source-follower NMOS amplifier, and the charge packets sampled by the CCD registers are continuously clocked toward these nodes for each stage. Therefore, each output amplifier has 16 interleaved ultra-high-speed images stored in the frame. Supplied with a typical serial waveform of the switching diode signal. As shown in FIG. 4, the unit cell pitch of the photosensitive section and the storage cells 302 and 304 is 14 μm × 14 μm, and includes an anti-blooming structure and a sensitive area used as a photosensitive section at the mask opening. In this frame transfer architecture, the sensitive region 302 is a partially associated analog memory at the active photoreceptor, and a storage cell unit 304 that is not active at the masked cell. The meter is a pixel "fill factor" (FF) and its light response, saturation charge, the efficiency of the anti-blooming drain that also functions as a dump drain for integration time control (electronic shutter), and the transfer efficiency at high speed Should be optimized. The fill factor of each active photosensitive portion is still relatively small compared to the area of the imaging region 202 because of masking used for high-speed operation. The effective active light sensor area can be increased with convex microlenses and / or reflective lenslet arrays, such as those included in optical member 104 of FIG. For example, provide a reflective microlens array of individual lenses, each positioned vertically above and each focusing on each of the active photoreceptors, with an area approximately 10 to 15 times the area of the active photoreceptor 302. Thus, the effective fill factor can be increased by at least 80%. Increasing the effective fill factor and, correspondingly, the effective light efficiency for an image, tends to require large light intensities to allow enough collected light to record a useful image in some event This is especially important at ultra-high imaging speeds. FIG. 5 is a cross-sectional view of the pixel. In FIG. 5, the pixel has a side overflow drain structure used in the high-speed operation of the imager as described above. The anti-blooming structure is shared between two adjacent pixels and functions as a pixel separation on both horizontal pixel sides. This structure consists of one half of the drain and one gate on each side of the pixel (anti-blooming drain and anti-blooming gate), one drain and two gates per pixel pitch. The potential barrier controlled by the anti-blooming gate is set to the anti-blooming potential level and extra charge in the CCD channel first flows to the anti-blooming drain instead of reflecting off adjacent pixels. The photosensitive and transfer areas are located in the CCD part of the cell unit. It consists of a set of four overlapping gates as shown in FIG. Thus, the four-phase transfer operation can be performed during the image shift toward the memory area. This transfer mode is much larger than the three-phase or two-phase mode and is used for better charge handling and charge capacity. As an example, the saturation level of this four-phase pixel cell unit is 210,000 e- if only 140,000 e- in the three-phase mode. In addition, in a four-phase structure, when using a three-gate architecture, three Length—improves the optical modulation transfer function of the sensor. Each 14.times.14 .mu.m square imaging pixel uses a three-level polysilicon MOS gate structure on an epitaxial p / p + silicon-based buried channel phosphorus implant. The anti-blooming overflow drain is a phosphorus implant and self-aligns with the two control gates. With 1.5 μm design rule CCD technology, this anti-blooming structure layout is only about 5.5 μm wide. Si / SiO _Two The pixel aperture at the interface level is 10. It is estimated to be 3/14, providing a fill factor of 0.74 in the active cell. This value is the minimum fill factor for this pixel at the blue wavelength because blue photons are absorbed in the first 100 nanometers below the interface. For red light, the fill factor is much larger and the internal pixel separation inside silicon is Si / Si 2 O 3 _Two Thinner than at the interface, the internal electric field expands under the anti-blooming gate, thereby increasing the fill factor at these wavelengths. In the memory area, instead of an anti-blooming device, vertical isolation between pixels is provided by thick oxide on a p + boron implant. This part of the circuit uses a polysilicon CCD gate structure with only two levels. The area not used in the anti-blooming structure has a CCD stage length of 13.mu.m for the image area of 14.mu.m. It can be reduced to 2 μm. This also achieves a greater charge handling capability than the imaging pixels to eliminate the saturation limit in this region. This region terminates at a specific gate that controls charge transfer to the read register. To provide high-speed charge transfer, interconnects are used to contact the pixel gates with the aluminum rails, and the aluminum bus runs from the top of the array, thus providing the anti-blooming structure in the image area and the thickness of the memory area. Drives both the image and memory regions. Because the entire array has a relatively large capacity, each clock of the photosensitive array (Pi) of the entire imager 106 is in a range that is difficult to drive through a classic clock drive circuit such as the 0026 series. is there. Therefore, the array is divided into four sub-arrays of 256 columns, each of which can be easily driven at high speed by a conventional clock driving circuit. This gives a typical frame transfer frequency up to 2 MHz, which is comparable to ultra-high speed imaging operations. In the memory area, one CCD readout register is provided for each of four subarrays of 256 × 1024 pixels. Each readout register has 256 stages for receiving the signal charge arriving from the associated pixel sub-array in parallel, and 15 readout registers that are needed to drive the charge toward the output amplifier and can also be used as electrical reference pixels. Consists of an extra stage. This structure is repeated four times along the last 1024 pixel lines of the memory area. The four CCD readout registers use a two polysilicon two-phase structure with buried channels and have the same 14 μm pitch as the imaging and high-speed frame storage area 202. All four are driven in parallel with two clocks (L), each terminating at a 9X gate VGS and stopping at an output floating diode. Using the channel turns, the tap structure can be operated without interruption at a 14 μm pitch. The readout design structure is the classic "floating diode readout" (FDRO), which uses an output n + / p diode as a charge detector after resetting to a reference plus voltage (VDR) via a clock (R). Charge packets arriving from the output register are dropped one by one into the floating diode well region at the last clock (2L), lowering the floating potential of that diode on the output gate BGS. This voltage is detected by each output amplifier. Four output amplifiers are used in the circuit to supply video signals arriving from the four output registers. It is designed for low noise operation with a bandwidth of 95 MHz. Each of the output amplifiers is a double stage source follower NMOS amplifier. The output CCD register is 20. Driven at 8 MHz, the device has a very high dynamic range (dark noise level 80 dBw. r. t. ) In the progressive scanning mode. Integration time from 0 to 15. 15. Can be set up to 9 milliseconds. The memory output rate of one memory block composed of 16 continuous partial images per 6 milliseconds is obtained. Imager area frame transfer is 1. Operating up to 3 MHz, the applied voltage is set to a nominal value. Additional features of the imager other than high-speed dedicated masking and imaging processing include “THX7887A: New high frame rate 1024 × 1024 pixel CCD sensor” by Buchala et al. (“THX7887A: A New High-Frame-Rate 1024 x 1024 Pixel CCD” Sensor, "G. Boucharlat et al. , SPIE vol. 2273 pp. 255-2763); A. "THX7897M: 2048x2048 CCD sensor for astronomy" by Kochiura (J. A. See also Cortiul a, "THX 7897M: Capteur CCD 2048 x 2048 Pour Applications Astronomiques," OPTO 93, Paris, May II-13, 1993). The system of FIGS. 2-6 is based on the conversion of an existing frame transfer imager to minimize design costs and other capital investments to create new masks, but without additional metal or Existing designs can be used by adding other opaque masks to produce the desired limited active pixel pattern. Similarly, applying a mask can modify other existing imagers to provide the most cost-effective initial fabrication of ultra-high speed imagers. For example, an interline transfer imager, a full frame imager, a frame transfer imager can be used. The commercially available 2024 × 2024 pixel Thomson CSF 7899 full frame imager is useful due to the large number of pixel cells and allows for mask pixel design of scattered and distributed active pixels. Such an array is what has previously been described as an array in which the active pixels are nominally separated or staggered by 8 pixels in both the column and column directions, resulting in a 64 or 65 ultra-fast continuous image. Create an imager that can store. Gated photodiodes are used in many imagers, such as interline transfer imagers, and are not on the charge transfer channel, provide the most efficient electronic shutter, and can initiate imaging during the ultra-high-speed sequence of imaging However, imaging is stopped during reading of the imager. Ultra-high speed CCD imagers take advantage of all the benefits of the architecture so that the active photosensitive area (preferably not in the charge transfer / memory cell channel and subject to electronic shuttering) takes up a very small percentage of the area of the imaging array. It can also be designed to provide an associated analog memory cell that is a major part of the imaging array. One example is the high speed system described in U.S. patent application Ser. No. 08 / 423,654, filed Apr. 17, 1995, for a high speed CCD imager, which is incorporated herein by reference. As shown in FIG. 12, by using a common high precision trigger 1201, two or more ultra-high speed cameras 1201, 1202, 1203 can be incorporated into a stereo photography system. The camera is suitable for receiving a common trigger signal in combination with a common frame gate and exposure program, and provides synchronized stereo imaging from multiple cameras. The cameras 1201, 1202, and 1203 are high-speed framing solid-state cameras capable of capturing substantially film-quality images, and are suitable for providing a variable interframe period of 100 μs to 100 nanoseconds, and have a time gating capability. Down to 1-10 nanoseconds. With pulsed laser illumination, the camera can provide at least 4, and preferably at least 16 frames of 10- to 12-bit grayscale images in on-chip image storage. FIG. 13 is a top view schematically illustrating a large format 2048 × 2048, preferably 4096 × 4096 storage cell / pixel CCD imager 1206 of a full frame architecture suitable for ultra high speed imaging of the camera system of FIG. . The full frame CCD imager 1206 has a large format of at least 2048 × 2048 storage cells / pixel size, more preferably at least 4096 × 4096 storage cells / pixel size, and a 4-port parallel output architecture for high data throughput. It is characterized by. It is designed and manufactured substantially in accordance with the THX7899M full field image sensor manufactured commercially by Thomson CSF Semiconductors (Orsay, France) (Thomson CSF Semiconducteurs Specifiques, Orsay, France). The electrical application of the CCD imager is shown in FIG. 13 and is as follows: Φ1,2,3,4 P (n) Used with vertical image shift (clock rate = 1-10 MHz) Low-speed four-phase clock Φab anti-blooming gate clock Vab anti-blooming sync bias voltage Φ1,2L high-speed two-phase horizontal image shift clock (clock rate = 20 MHz) Vdd on-chip amplifier bias Vssa on-chip amplifier ground return Vos ( n) Video output The preferred imager itself is a 4096 x 4096 square pixel (e.g., each pixel or storage cell is approximately 10 [mu] m x 14 [mu] m x 14 [mu] m in size, arranged along a vertical CCD shift register (in the direction of the arrow). 1.6 million images formed with an active photoreceptor area of 10 μm) It includes an imaging region, simultaneous and control of the image area analog data has been so read. To increase the output rate of the device, the imager has four outputs, each of which receives an analog charge packet from a quarter of a 4096 CCD vertical transfer column as shown in FIG. During normal operation, the imager integrates the optical image for each of the pixel cells in the image area under control of the camera control system over a predetermined time interval. The imager releases the shutter externally. The image is then shifted down vertically one column at a time until the entire image is directed to each output amplifier. Modifications of the spatial light shield include a metal mask of the type shown in FIG. 3A or 3B above the opaque imaging portion except for a correctly aligned pixel aperture 1024 × 1024 pattern. When combined with a customized CCD clock sequence, this special light shield mask allows ultra-high speed imaging of 1024 x 1024 partial images inside a large 4096 x 4096 array. Applying a custom mask to the other active pixels in the imaging area creates a partial image storage area and requires that the entire image (4096 columns) of the array be clocked before taking the next image. Sex is eliminated. Indeed, with proper design of the metal mask, a 1024 × 1024 partial image shifts the data into the memory area, ready for the next image capture after only one vertical shift cycle. Because the vertical shift can be performed at short time intervals of 100 nanoseconds, the 1024 × 1024 sub-imager can capture new images at a rate of 10 MFPS until the partially created memory area is exhausted. For a 1024 × 1024 sub-image of the 4096 × 4096 image array, approximately 16 ultra-high-speed continuous sub-images can be captured and stored for high precision low speed readout. Therefore, the structure of the photosensitive unit and the storage cell illustrated in FIG. 3A can capture and store 16 images of approximately 1K × 1K image size. Because the charge packets are transferred at very high speed along the transport channel (eg, at a four-phase clock rate up to 10 MHz), the sub-imager actually captures new images up to a rate of 10 million frames per second. The 16 continuous images are interleaved as shown in FIG. 3, and the more recent the cell 16 becomes the first image, the more the cell 15 becomes the second image, and the more the cell 1 becomes, the more recent the image becomes. In conventional operation, a 4096x4096 imager requires 4096 consecutive vertical shifts to read an image frame. In the high speed (10 million frames per second) mode of operation, this clock pattern is stationary until triggered by a trigger signal. Starting a conventional four-phase clock pattern, a predetermined number of vertical parallel shifts that do not exceed the number of storage cells (here, 16 including the photosensitive section) partially linearly associated with each photosensitive section are performed. provide. The clock pattern is abruptly stopped within one cycle, and the partial image is kept stored without any overlap from the image signal from the adjacent photosensitive section. The camera is effectively shuttered and idle until readout begins. In some environments, as described above, it may be desirable to capture image bursts at 10 million frames per second, stop for a long time to capture a million FPS bursts, stop, capture 500 KFPS, and so on. For example, the user captures 6 frames at 10 million FPS, pauses for 1 millisecond, captures another 6 bursts at 1 million frames per second, pauses for 10 milliseconds, and fills the remaining memory buffer with 500 KFPS. You may want to do that. This mode of operation can be provided as a programmable function of the high speed solid state camera system of the present invention. The transport electrode of such a large-sized image sensor is relatively elongated, and has a relatively large resistance in addition to a large-capacity load caused by a large area of the imager. It is difficult to drive such a large image sensor at high frame rates, well over one million parallel (vertical shift cell) transfers per second, without charge transfer inefficiencies and other problems. To provide an imager structure for ultra-high speed imaging at frame rates in excess of 5-10 million frames per second, a custom light shield is applied, a special clock scheme is used, and a large The addition of straps or bus-type electrodes changes the imager architecture, which allows for high speed operation. Strap-type electrodes are enabled for light shielding and imager operation, because if a high percentage of the imager is used as a photosensitive part, the strap-type electrodes will interfere with imaging at the photosensitive part. . As shown in FIG. 14, a large strap electrode is provided above a metal mask applied to an imager, and is insulated from the mask. A wide bus is periodically connected to each of the respective common mode transport drive electrodes by vias according to conventional integrated circuit manufacturing techniques. Due to the significantly smaller resistance and the significantly smaller aspect ratio, the width is about 2. Ultra-high-speed operation is possible at a higher transfer rate than when using only a four-phase polysilicon transfer electrode that is only 5 μm and penetrates and is thin enough to allow imaging in a pixel cell. As shown in FIG. 14, the area between the active pixel portions can be advantageously used for an additional relatively wide high-conductivity transport electrode bus, which is regularly (vias) transferred to the lower transfer electrode. Can be used to apply a clock signal. These electrodes are made of metal and are 10 times or more than the polysilicon or silicide pixel transfer electrodes (four at each pixel site in a four phase transfer electrode structure as used in the systems of FIGS. 1 and 13). Beyond that, and at least 10 times more conductive, the resistive drive load is greatly reduced, the transfer / clock frequency can be increased to 500-100,000 frames per second, while at the same time substantial pixel uniformity And the charge transfer efficiency can be maintained. To increase the light sensitivity to the final camera (since most of the active pixel area is shielded from light), mount the lenslet array on a masked CCD array and fill factor up to at least 60% and preferably up to 85%. Pull up. For example, in the pixel pattern of FIG. 3A, the optically active aperture exists only once every four pixels. Assuming a basic pixel pitch of 14 μm, the fill factor is about 1/16 or 6%. Applying and focusing a lenslet on each of the sensitive apertures results in a diameter of about 55.5 mm. It becomes 5 μm (the lenslet interval is set to 1 μm for manufacturing purposes), and the effective fill factor is raised to 90% or more. A significant advantage of this solid-state architecture is that after capturing 16 images at up to 10 million frames per second, the "memory" of the captured frames is read out at a relatively slow data rate, resulting in a very large dynamic The point is that you get a range. Standard (commercial) high performance including analog-to-digital converters and frame grabbers, rather than expensive ultra-fast data acquisition systems, because the read data rate can be maintained at a relatively low rate, eg, 20 megapixels per second. Readout circuitry can be used for data capture. Fast time gating independent of the frame rate is achieved by pulsed laser illumination and / or fast gate intensifiers (photomultiplier tubes). There are copper vapor lasers with gate pulse durations on the order of 1 nanosecond. While this "gate" duration is sufficient for most high speed imaging, the repetition rate of pulsed laser sources is typically limited to tens of kilohertz. Gated intensifiers provide another path that provides not only time gating but also image amplification (a significant advantage in high speed imaging applications). High resolution intensifiers up to 641 p / mm can be realized with 18 mm intensifier cells providing repetition rates in excess of 10 MHz and gate resolutions on the order of 1-15 nanoseconds. 1 and 12 are designed to operate in wideband panchromatic mode or in monochrome mode with an external color filter or light source. What is shown in FIG. 15 is masking with a color plate super-high-speed imager. In the imager 1500 of FIG. 15, a mosaic of the minute red color filter dots 1501, the minute green color filter dots 1502, and the minute blue color filter dots 1503 is formed before applying the light shield mask as shown. Manufactured on top of an imager array. As shown in FIG. 15, three columns are used to store image data of each of the RGB pixel arrays. The pixels make the entire RGB pixel area closer to a square (eg, with an aspect ratio up to 3: 1). A large microlens on each pixel is used to focus light from the circular area onto the RGB pixel pattern. For example, as shown in FIG. 2, the rate of image data captured by an ultra-high-speed imaging system such as a two-dimensional array limits the number of frames and image resolution that can be realized with a two-dimensional array. To provide additional image memory partially associated with each active photoreceptor, the present invention provides a CCD imager that uses a three-dimensional stack of parallel edge-input CCD imaging arrays, such as the edge-sensitive CCD 702 illustrated in FIG. With respect to the system, it forms an integrated imager, memory, output or processing system, such as the system 802 shown in FIG. Such a stacked array can store a larger number of image frames and process high-speed captured continuous images to compress or selectively simplify the data output requirements of the system. Stacked imagers and camera systems based on unusually compact imager / memory stacks formed with such chips can provide significant performance enhancements. In the imager / memory stack, individual CCD memory chips are stacked and assembled to form an imaging surface and an output surface (see FIG. 8). The individual memory chips are each driven at 1 to 10 MHz and are relatively slow for CCD memory operation, but provide ultra-high speed imaging operation due to the fully parallel processing design. The chip has a linear array of edge-sensitive input pixels, each of which is clocked into its own CCD memory channel, which can be 1,000 or 2,000 memory cells or longer. The memory channels are multiplexed and clocked to one or more conventional high speed output amplifiers to clock the image data off chip, as shown in FIG. When the edge sensitive CCD memory chips of FIG. 7 are stacked vertically, the linear photoreceptor at the edge of each chip forms a two-dimensional pixel array on the imager surface. In addition, the associated CCD memory channels form a compact, ultra-dense 3-D memory, operating in full parallel, receiving data clocked at 1-10 MHz from each corresponding edge sensitizer. . As shown, the imaging surface is formed by an edge-sensitive linear pixel array on each chip, which can include optical directors and lenslets to improve light response. The pixel x spacing (see FIG. 8) is fabricated directly on each chip. The pixel y-spacing depends on the thickness of the chip wafer and ranges from 10 μm for ultra-thin wafers to 300 μm or more for “standard” wafers. Using a lenslet array with off-axis lenslets can effectively reduce the y-axis pixel spacing (while increasing the x-axis spacing). Alternatively, a Pareto imager, such as a backside thin or silicon-on-sapphire type imager, can indium bump directly into the edge sensitive CCD input area of a stacked 3-DCCD memory cube. CID image sensors can be easily bumped to each charge mode detector on a stacked memory chip, and are therefore desirable as sensors for such 3-D bump imager arrays. Since the photoreceptor is directly clocked in parallel with its corresponding CCD memory channel, the bump mounted imager can operate at an ultra-high frame rate corresponding to the memory CCD channel's 1-10 MHz rate. Bump mounting of the silicon-on-sapphire imager to the 3-DCCD memory stack provides close y pixel spacing when stacking "thick" wafers. For example, by multiplexing the eight pixels of a bump mounted imager to each CCD memory channel of a "stack" of 200 μm thick CCD memory chips, a 25 μm pixel spacing is created. A 1K length CCD memory channel provides 125 full frame image memory storage, while a 2K length CCD memory channel allows 250 full frame images to be stored in a 3D array and is 512 × 512 multiplexed into 64 stacked chips. The imaging array has a memory capacity of 65 megabytes or more. As shown in FIG. 9, the bump mount can also be used for interconnection at the output side of the imager / memory cube. This allows independent control of the high-speed imager drive circuit, high-speed CCD memory channel drive circuit, and low-speed output drive circuit. The compact stacked geometry is suitable for operation in triggered burst mode, where the trigger event allows for fast imaging and storage of 1,000 or more image frames in analog CCD memory along the "z" axis. Start. 1,000 or more frames of image data can be clocked or "read out" for processing at a second, lower data rate. The stacked z-axis CCD memory chip geometry of the present disclosure provides complete design efficiency with parallel operation of the cores, independent imager, memory, output driver connectivity, powerful functional compactness and 3-D density of arithmetic circuits, Small size, light weight, compatibility with image intensifiers, fill factors to extend lenslet array selectivity of "good" chips for assembly of defect-free large arrays, simplicity with one linear imager array It has the advantage of high production yield of CCD memory chips. The x-axis pixel separation is manufactured on-chip. However, the y-axis tolerance depends on wafer thickness and stack uniformity, while the z-axis tolerance depends on wafer die cutting and alignment tolerances. The use of precise deep etching techniques, such as "black silicon" vertical etching techniques, as opposed to wafer-saw technology, isolates the CCD dice for stacking and damages the silicon grid resulting in excessive dark current. Can be avoided (H. Jansen et al., "The Black Silicon Method", H.S. Jansen et al. , J. et al. Micromech. Microeng. 5, pp. 115-120 (1995)). Various alignment methods can be used for z-axis alignment, including "pillar-concave" stacking and optical flat assembly as illustrated in FIG. Bonding of silicon wafers with evenly deep grooves can be achieved by anodic bonding of silicon wafers with a thin layer of photoresist or photoresistor, or by R.O. F. It can be easily realized using sputtered glass. A processing potential of about 1 volt is sufficient for an anode bonded silicon wafer with a glass layer of 100 nanometers or less (V. Spearing et al., "Electrocorrosion-proof wafer bonding for planarization after deep etching" Spiering, et al. , "Sacrificial Wafer Bonding for Planarization After Very Deep Etching," Journal of Microelectromechanical Systems, vol. 4, pp. 151-157 (1995)). A properly aligned mirror polished silicon surface can also be welded by a wafer bonding technique where surface silanol group dehydrate and residual oxygen atoms disappear at high temperatures. The low-temperature bonding method is a preferred method recently developed for performing Si / Si bonding at a temperature of 400 ° C. or less (Tong, “Low-temperature wafer direct bonding” Tong, "Low Temperature Wafer Direct Bonding," Journal of Microelectromechanic al Systems, vol. 3, pp. 29-35 (1994)) and an attempt can be made to bond the front mounting post to the backside of the wafer as shown in FIG. Since a single CCD memory chip operating at a clock rate of 1 MHz using a low-resistance aluminum clock electrode typically dissipates about 2 watts, the 3-D "stack" of 512 such chips is 2 A centimeter cube will generate about 1000 watts of heat. This heat output is (a) designed by the drive circuit to operate only when the imager is functioning (e.g., the total heat in 1,000 frames at 1 megaframe / sec is 0,0). 001 × 1K watts = 10 watts or less) and (b) removing heat using a 3D internal refrigerant network. The large bulk density of the circuit generates considerable heat and can be removed by passive integrated heat pipes or forced refrigerant circulation. As shown in FIG. 10, the pillar arrangement chip stack can be cooled by a refrigerant circulation system passing through the yz plane. Similarly, since the CCD memory channel is smaller than the imager pixels, it can accommodate through-chip coolant holes etched on the chip by deep-etched parallel wall technology used in micromechanical device fabrication and chip separation. Micro heat pipe arrays can be used as efficient backside heat dissipation or heat removal devices by reducing the heat path between the frontal heat source and the heat sink (Malik, “Integration of Semiconductor Devices”). Manufacture of micro heat pipe array deposited as `` A. Mallik, "Fabrication of Vapor-Deposited Micro Heat Pipe Arrays as an Integral Part of Semiconductor Devices," Journal of Microelectromechanical Systems, vol. 4, pp. 119-131 (1995)). The sealed microheatpipe array can be fabricated on the backside of a thick chip wafer as a coreless non-annular channel with a hydraulic cross section of 10-50 μm and a length of up to 2 cm. Surface coating as low as 2% produces a 40% increase in heat removal. Greater heat removal can be achieved by forced liquid circulation through the chip stack. The compact 3-D stack design can be used with conventional image intensifiers and can provide a fill factor of 80% or more by using lenslets. The design is also fully compatible with image intensifiers that generate direct electronic output by using an electro-absorbing edge-sensitive input “pixel”. This application of the electronic direct hit detection mode can provide about 5000: 1 effective optical gain for a conventional CCD imager. Although various aspects of the invention have been described with respect to particular embodiments, alternatives and modifications are apparent from the disclosure and are intended to be within the spirit and scope of the invention as set forth in the following claims. It is understood that there is.

────────────────────────────────────────────────── ─── Continuation of front page    (81) Designated countries EP (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, L U, MC, NL, PT, SE), OA (BF, BJ, CF) , CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG), AP (GH, KE, LS, MW, S D, SZ, UG), EA (AM, AZ, BY, KG, KZ , MD, RU, TJ, TM), AL, AM, AT, AU , AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, G B, GE, GH, HU, IL, IS, JP, KE, KG , KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, N O, NZ, PL, PT, RO, RU, SD, SE, SG , SI, SK, TJ, TM, TR, TT, UA, UG, US, UZ, VN, YU (72) Inventor Marrick, James, Jay.             United States 60022 Illinois             Lencoe Greenwood Avenue             748

Claims (1)

[Claims] 1. A plurality of analog memory cells that perform a continuous operation that is partially connected, A solid state camera comprising an array of photodetectors capable of high-speed continuous imaging. Remote imaging array. 2. The partially tied memory cells are aligned along a CCD charge transfer channel. 2. The solid stay according to claim 1, wherein the solid stay is linearly connected to each photosensitive portion. Remote imaging array. 3. The photodetectors are arranged in a two-dimensional imaging area, and the analog -Some of the memory cells are provided by a directional member orthogonal to the two-dimensional imaging region. 2. A three-dimensional imaging unit and a storage unit are oriented to form a three-dimensional imaging unit. Solid state imaging array. 4. An array of photodetectors having partially associated memories, the array comprising Under the exposure control, scanning is performed at the first rate and the second rate, and the effective first frame is scanned. -State imaging that provides a frame rate and an effective second frame rate Image array.