JP2000501543A - Method and system for soft programming algorithm - Google Patents

Abstract

(57) Abstract: A floating circuit including a control circuit (2, 3, 4) for generating a repair pulse so as to repair a super-erased cell so that the cell can be repaired block by block (1). Gate memory device. The invention involves repairing the cell by applying a repair pulse to the cell's bit line (10, 11) while maintaining the word line voltage above ground. In different embodiments, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION       Method and system for soft programming algorithm Background of the invention Technical field   The present invention relates to floating gate memory devices such as flash memories. And, in particular, a method for repairing a floating erased memory cell that has been over-erased. Circuit.Description of related technology   Non-volatile memory design based on integrated circuit technology is an expanding field. Indecision Various general classes of volatile memory are electrically erasable and programmable Based on an array of floating gate memory transistors.   Floating gate memory transistor memory in one general approach The act of programming the array causes the negative charge to accumulate on the floating gate, Floating of addressed cells with electrons increasing cell turn-on threshold Including injecting a gate. Therefore, when programmed, the cell is turned on. That is, the cell is not opened with the read potential applied to the control gate. When dressed, it is held non-conductive. Cell with negatively charged floating gate The act of erasing electrons involves removing electrons from the floating gate to a lower threshold. No. At lower thresholds, the cell has a read potential relative to the control gate. When turned on, turns on to the conductive state. For the opposite polarity array , Programming selectively removes electrons from the floating gate of the addressed cell Including doing.   Floating gate memory cells suffer from over-erasure problems, especially Erasure can reduce the threshold by removing electrons from the floating gate. It is a problem when including. During the erasing step, over-erasing means that too many electrons are Or It occurs if it is removed from the floating gate leaving a significant positive charge. Positive charge is Even when not addressed, small currents leak through the memory, Bias the memory cells slightly on. Many along a given data line Over-erased cells can cause the accumulation of leakage current to be a source of misreads. Can be made.   When floating gate cells are over-erased in addition to causing misreads It uses hot electron programming to successfully re- Programming, especially with algorithms embedded in integrated circuits. Make it difficult. This difficulty moves over-erased cells to the programmed state. This occurs because a large amount of electrons are needed to drive the cell compared to a normal cell.   In addition, erase and program operations affect different cells of a single array each Floating gate memory design can be erased and programmed Often includes circuitry to check the success of the logging step. For example, by Jungroth Was invented as "VOLTAGE MARGINING CIRCUIT FOR FLASH MEM0RY" See U.S. Patent No. 4,875,118. If the array does not pass the erase test, The entire array is usually erased again. The re-erase process involves over-erasing the array. Cell may be deteriorated.   One solution to the over-erase problem of the erase inspection process is the erase inspection operation. 1995 shows a method and apparatus in which only those blocks that fail U.S. Pat. No. 5,414,664 issued to Lin et al. On May 9, 2014, entitled "FLASH MEM0RYWI TH BL0CK ERASE FLAGS FOR 0VER-ERASURE PR0TECTI0N ". Follow Thus, re-erasing of the entire array after each check operation is not required. This means that Alleviates the phenomenon, but does not completely eliminate it.   Accordingly, a repair process has been developed to correct over-erased cells. Ong, etc. Published by "METHODS OF REPAIRING FIELD-EFFE CTCELLS INANELECTRIC ALLY ERASABLE AND ELECTRICALLY PR0GRAMMABLE MEM0RY DEVICE " U.S. Pat. No. 5,233,562 describes so-called drain, source or gate interference. Use harmful techniques to describe the process for such repairs. Ong patent repairs Later, time is provided to spend the entire array repair inspection operation. even more See also Shrivastava U.S. Patent No. 5,416,738 for background information. .   In either case, the repair and repair inspection process is time consuming. therefore, Faster and more efficient flash memory and other floating gate memory over-erased cells There is a need for a method and apparatus for mechanical repair.                                 Summary of the Invention   The present invention provides a floating gate memory that quickly and effectively repairs over-erased cells. Include soft program cycle in erase sequence for re-device It is. The process is integrated with integrated circuit flash memory devices It is suitable for use in a type erase algorithm and has a floating gate memory Suitable for architecture.   According to the present invention, a segmentable gate memory array is provided by a soft processor. Apply a gram repair pulse in parallel across an entire sector of a floating gate memory cell Provide a circuit for: The technology to cooperate with the sector by the sector erase structure is Rapid and effective techniques for data erasure have been implemented in floating gate memory devices. Provided to the software recovery pulse.   Thus, according to one aspect, the present invention provides an array of floating gate memory cells. Including floating gate memory integrated circuits. The array is Connected to the drain terminal in each row of cells in the Number of drain lines and source lines in each row of cells in a sector Multiple source lines connected to the terminal and each of the cells in the sector And a plurality of word lines each connected to a control gate terminal of that column. Having a Of course, depending on the architecture of the array, a single conductor Both source and drain lines between adjacent memory cells Can work. The control circuit adjusts the threshold voltage of the cell in the selected sector, Low threshold state where the cell has a specific range of threshold voltages (erased state) To set the drain line, source line and Connected to the word line. The control circuit provides a specific range of threshold voltages (over-erased). The selected section yields some cells with thresholds lowered below pressure. Provide a circuit for continuously supplying a voltage so as to lower the threshold value of the cell in the Includes voltage to supply. Continuing the first voltage to lower the threshold Thus, a repair pulse is provided to the selected sector. Healing pulse Applied for the duration of the tarball, in which case it is the source disturbance or drain disturbance software ・ Includes program effects.   According to one aspect of the invention, the word line voltage is the maximum of a particular range of threshold voltages. It is set at a level below the small and above the ground. Increased word line voltage Is the current injected into the cells that are dependent on the soft program Speed up the process. In another system, the word line is Substantially pulled to ground. To control cell failure in the array, Word line voltage in preferred system is above ground during repair pulse Is pulled to a level less than 0.5 volt.   According to another aspect of the invention, the control circuit includes a repair circuit in two successive stages. During the pulse, a circuit for driving the word line is included. In the first phase of the sequence, the word line is Driven to a first level for one interval time and a second During the sea, the word line is driven to a second higher level during a second interval Is done. These two level pulses on the word line This is a technique for controlling the amount of current consumed in a vehicle. Therefore, the first stage During continuous low voltage, cells subordinate to the repair pulse are controlled due to low word line voltage. The current is programmed to go to the columnar erase state. After the first stage , A second higher voltage level is applied to the word line. This high voltage is Inducing more thermionic injection currents to balance the gram pulse Repair cells more efficiently in the amount of time. In a preferred system, the repair time The interval is held at a first low level of about 0.1 volt for 100 ms. , And then about 0.2 ms for a 200 ms repair pulse interval balance. A word line voltage rising to a second high level of 4 volts lasts about 200 ms. Like Alternatively, during the first phase of the repair pulse, the word line voltage is set to about 0.2 volts with ground. of It is held at a value between. During the second stage, the value is less than about 0.5 volts, approximately It is held at 0.4 volts.   According to the present invention, the repair pulse is applied to a plurality of dots of a selected sector in the array. By driving the rain line, for example, a positive voltage of about 5.5 volts can be used. To drive the plurality of source lines to substantially ground. This is Increase any drain disturbance repair pulse. Another system grounds the drain While applying a positive voltage to the source, a so-called source disturbance repair pulse can be used. You. In addition, the current limiting circuit may include multiple drain lines and sectors in the array sector. And at least one of a plurality of source lines. For example, current control Limiting transistor may be connected to the source line. This is what the array The amount of current in a particular sector depends on the available drive of the voltage source that provides the repair pulse. Avoid consuming dynamic power.   Accordingly, the present invention provides a built-in erase algorithm with soft program pulses. A rhythm is provided for quick and effective repair of erased cells. pulse Is applied sector by sector or parallel to the entire array, in this case commercial integration Achieved in the relatively short time available for use in the circuit. More preferred In an embodiment, soft programming with a low voltage on the bit line; Fast soft programming without disturbing properly erased cells and soft Can manage the current consumed during the soft programming operation. Provide a step pulse.   Other aspects and advantages of the invention are set forth in the drawings, the detailed description, and the appended claims. checking ...                             BRIEF DESCRIPTION OF THE FIGURES   FIG. 1 is a schematic block diagram providing an overview of an integrated circuit according to the present invention.   FIG. 2 is divided into segments for floating gate memory cell devices. FIG. 2 is a circuit diagram illustrating an array architecture according to the present invention.   FIG. 3 is an overall flowchart of the present invention.   FIG. 4 is a more specific flow illustrating the sector erase and repair process of the present invention. It is a chart.   FIG. 5 illustrates a word line driver having two levels of pull down according to the present invention. FIG.   FIG. 6 illustrates the two-stage soft programming process of the present invention. It is a flow chart.   FIG. 7 shows a three level pull down circuit for a word line driver according to the present invention. FIG.   FIG. 8 is a circuit showing a word line driver circuit element for use in the circuit of FIG. FIG.   FIG. 9 shows a top block selection window for applying a repair pulse according to the present invention. It is a schematic diagram of a driver.   FIG. 10 is a graph showing the effect of the soft program pulse according to the present invention. is there.                             Detailed description of the invention   A detailed description of a preferred embodiment of the invention is provided with reference to the figures. Of the present invention The soft program is preferably a data containing an array of cells arranged in blocks. Embedded erase sequence for floating gate memory cell devices, such as devices Part. Soft programs measure the amount of current generated during the process. Pulse limiting and fast repairing cell blocks over-erased by blocks Generate   FIG. 1 shows the basics of a 4 MB floating gate memory cell integrated circuit incorporating the present invention. Shows a simple structure. This circuit has a plurality of blocks (32 blocks in FIG. (Lock) memory array. Memory array segmentable Repair pulse according to the present invention for each cell block And therefore repair the block by repairing the block of the over-erased cell. You can do it. The array architecture is described in detail below with reference to FIG. Bell.   Still referring to FIG. 1, a read and program control circuit, generally indicated at 6, A block / erase / erase inspection / repair circuit indicated by 2 is connected to array 1 It is. The block / erase / erase check / repair circuit 2 contacts the block erase flag 3 Continued. Address counter 4 is a memory cell, block, or erase Increment / delete through entire array for inspection / repair sequence To be included.   The chip contains other information such as address, data, and output enable and chip enable signals. It includes command logic 5 connected to the control line. Command logic 5 Means read / program control logic 6 and block / erase / erase inspection / repair The input for setting the operation mode with respect to the circuit 2 is translated.   Command logic 5 is an add-on to the present invention for erasing cells, blocks or arrays. Advanced Micro Device, I of Sunnyvale, California with additional commands nc. Standard floating, such as the Am28F020 flash memory chip manufactured by It can be implemented as done in a loose gate memory integrated circuit. Command Logi In response to the command issued by the block 5, the built-in erase operation performs the erase / erase operation. This is executed by the state machine of the inspection / repair circuit 2. The user can Via the host CPU or another to indicate the preferred mode of operation. The address and data signals are provided to command logic 5. Erase / Erase Inspection / The mode performed by the repair circuit 2 is that all blocks of the array are erased. Chip erase mode should be and selected block of array should be erased And a block erase mode. Blocks to be erased in response to user input The lock is identified by the block or sector erase flag 3 stored in the chip. Is done.   FIG. 2 is issued on March 21, 1995, incorporated herein by reference. United States named "NON-VOLATILE MEMORY CELL AND ARRAY ARCHITECTURE" A floating gate device in which the present invention can be implemented, such as described in US Pat. No. 5,399,891. Segmentable array architecture with drain-source-drain configuration for memory circuits The details of the architecture are exemplified. Other array architectures can also be used .   The circuit is implemented by a buried diffused conductor, the first local bit line 10 and a second local bit line 11. Also, by buried diffusion A local virtual ground line 12 that is implemented is included. Multiple floating gut The transistors are connected to the local bit lines 10, 11 and the local virtual ground. A drain and a source connected to the drain line 12. In a single block A significant number of these floating gate transistors are the result of the erase step described above. As a result, overlapping erasure is performed at a changed degree.   The drain of the first column of the transistor, generally indicated at 13, is the first local A second capacitor of the transistor, generally indicated at 14, connected to the bit line 10; The drain of the ram is connected to the second local bit line 11. Each word line ( For example, WL1) is the transistor of the first local bit line 10 (eg, For example, the transistor 15) and the transistor of the second local bit line 11 (Eg, transistor 16) to be connected to the floating gate The gate of the transistor is connected to WL0 via word line WLN. Transistor 1 5 and 16 may consider two transistor cells with shared source diffusion You.   The act of changing the floating gate is a floating gate memory cell program. ・ It is called a step. This is as large as 12 volts between the gate and the source. A positive voltage between the drain and source, such as 6 volts Thus, it is achieved on a bite basis via hot electron injection.   The act of discharging the floating gate is the erase step for the floating gate memory cell. Called This is between floating gate and source (source erase) or floating FN (Fowler-Nordheim) tunneling between the gate and the substrate (channel erase) Achieved through a logging mechanism. Source erase, such as 12 volts or 7 volts, Implemented by applying a positive bias to the source, while the gate Grounded or negatively biased, such as -7 volts. Bro The channel erasure on the grounds can be done by applying a negative bias to the gate and / or This is performed by applying a positive bias thereto.   The individual blocks of the cell have a selection signal, ie, a top block selection signal TBS. EL_AAnd TBSEL_BAnd bottom block selection signal BBSEL_AAnd BBSEL_B And is controlled by The individual control of the block is controlled by applying a repair pulse to the selected row. Provides the ability to apply to cull bit lines 10 and 11.   Still referring to FIG. 2, the first global bit line 17 and the second A global bit line 18 is associated with each drain-source-drain block. Be involved. The first global bit line 17 is connected via a metal diffusion contact 55 Connected to the source of top block select transistor 19. Similarly, the second Global bit line 18 is connected to top block via metal diffusion contact 56. Connected to the source of the select transistor 21. Top block selection transition The drains of the stars 19 and 21 are connected to the first and second local bit lines 10 and And 11 respectively. Therefore, the top block select transistor The gates 19 and 21 are connected to the top block select signal TBSEL on line 23._ATo Therefore, it is controlled.   In a similar manner, the gate of the bottom block select transistor 65A is connected to the line Bottom block selection signal BBSEL exceeding 26_AIs controlled by Low The virtual virtual ground line 12 is connected to the bottom block selection transistor 65A. Via the conductor 54A to the virtual ground terminal. Bottom b The drain of the lock selection transistor 65A is connected to the local virtual ground line 1 2 is connected. The source of the bottom block selection transistor 65A is the conductor 5 4A. In this architecture, conductor 54A is a straight metal virtual In a location that is placed horizontally through the array and provides contact to the It is a buried diffusion conductor extending to the metal diffusion contact 60A.   For the sense amplifier and program data of the structure, the data line 29 is , Vertically via an array for each column select transistor 70, 71 It is connected to extending global bit lines 17 and 18. Thus, empty The source of the memory select transistor 70 is connected to the blow bit line 17. The gate of the column selection transistor 70 has a column decode signal Y_noConnected to And the drain of the column select transistor 70 is connected to the data line conductor 29. Is done.   Blocks of floating gate memory cells as shown in FIG. In a plurality of sub-arrays as shown in FIG. Is done. The sub-array is totally divided along dotted line 50 and above line 50 Subarray 51A shown generally and subarray 51 shown generally below line 50 B. The first group 52 of cells is a given bit line pair (eg, 1 Along the second group of cells along with the mirror image. one Memory bit array as the virtual line pair progresses, Body 54A, 54B (buried diffusion) and metal-metal diffusion contacts 55, 56, 57, 58 Flip to share. The virtual ground conductors 54A and 54B To the vertical virtual ground metal line 25 via the metal diffusion contacts 60A, 60B. Spread flat. A subarray is a sub-array whose adjacent sub-arrays are Repeat on both sides of metal virtual ground line 25 to share line 25 . A metal virtual ground line connects to the array ground and the erase high voltage circuit. It is. Therefore, the layout of the sub-array is Two metal contact pitches per column of two transistor cells One metal contact pitch is required for the ground line 25.   Splitting the word line with a slight high voltage during the soft programming pulse is This creates the possibility that high currents can be generated in sectors that are soft programmed. This current is limited by the current control circuit on the source side of the cell. Refer to FIG. Then, the bottom block selection transistor 65B or 65A is connected to the current limiter. It works. This transistor on its source side is 0 depending on the mode of operation. For an array ground power supply, which is a generator to support volts or positive voltage Connected. Therefore, the bottom block selection transistors 65A and 65B are Sector decode transition also serves as current limiter during shift program It is a star. Besides, use other current limiting schemes like current mirror circuit Can be done.   Due to the sector decode capability provided by the circuit of FIG. While grounding about 5 to the local drain line. Apply 5 volts By doing so, only the drain disturbing soft program pulse is selected in the array. Can be applied to selected segments.   Also, another system has about 5. Apply a 5 volt soft program pulse Or soft ground while grounding the bit line or drain terminal. Circuit parameters via the source terminal of the device being programmed More dependent. The same segment-by-segment decoding and word line driver Can be used for a source jamming approach.   Referring to FIG. 3, a chip or chip including the soft program steps of the present invention 4 shows an overall flowchart of a block erase process. Erasure calculation (step 80 ), And then via the host CPU or via the command logic 5 Otherwise, for the chip or block selected for erasure, The programming is initialized (step 81). In step 82, the program The recovery period causes the voltage to stabilize after pre-programming. In step 83, a program check process is caused. Then the system If the last address of the chip or block is programmed, (Step 84). If not, pre-programming The process, which begins with a single step, is a process where all cells of a chip or block are pre- Repeat until programmed.   After pre-programming, an erase recovery period 86 for stabilizing the erase voltage Then, an erasing operation is performed in step 85 following the operation of FIG. Next, an erase check operation 87 is executed. You. The system then sees if the erase process is completed at step 88 To check for. If not, it returns to step 85 and completes Execute the erase operation until When complete, the soft program pulse is turned off. So that the last operation is applied in parallel to all cells of the chip or block. In step 89, the software program is initialized. Soft program recovery This occurs at step 90. The process ends at step 91.   FIG. 4 shows a block diagram using the block erase flag 3 and the address counter 4 shown in FIG. Embedded erase and repair process of the present invention, typically performed by control circuit 2 1 illustrates one embodiment of the present invention, including an algorithm for: This embodiment Is above ground, or beyond word line and source terminal. 5 bolt repair pad Maintain the word line during lus, preferably slightly above ground.   According to the built-in erase algorithm, the erase operation is performed on the array This is done at step 99 with the setting of one or more flags that indicate the Chip eraser Set all flags and reset the address counter to address zero. Period. If a block erase operation is to be performed, Flag is set. According to this embodiment of the invention, one is The repair flag, which is related to the erase flag, generates a soft program repair pulse. It is also set to identify the sector to receive (step 99A). Next, a pre-program operation is performed on the selected sector (step 100). .   In the next step, all sectors having the setting flag are erased (step 1). 01). During the erase operation, the high voltage on the virtual ground line 25 is, for example, BBSEL It is isolated from unselected sectors by transistors. Same section BBSELs have the same voltage level for the blocks of data. BBSEL, When the sector flag is set, a high voltage is applied to pass the array high voltage. It is driven at 0 volts when the rectifier flag is reset. By this Then, the selected erase operation is performed. Then, the overall settings of the selected block are Erase by applying the voltage as described above. Bottom block selection tiger Divide into segments under transmitter control.   Next, the timer waits for an erase time-out state (step 102). Thailand After the sleep state, an erase recovery stage is entered (step 103). Again, this recovery stage On the floor, timing is taken as shown in step 104.   After erasure recovery, an erasure test voltage is set up (block 105). This operation Is named ERASE AND PROGRAM VERIFICATION CIRCUIT FOR NON-VOLATILE MEMORY No. 5,463,586.   The next step is to evaluate the flags and have the flag in the block inside each position Testing the data (block 106). This routine uses the flag Including determining if it has been set (block 107). Is set If so, the routine passes the erase check pass and overs of the least significant bit counter. A check is first made for the flow (block 108).   If a path is detected and the counter is not at the end of the block, then the bottom The bit address is incremented (block 109). At this point, the algorithm The loop returns to block 106.   If the flags are not set, then the algorithm To block 110 which performs a test to determine if it has been reset Loop. If everything is reset, or reset at the beginning of the routine If so, the algorithm then indicates that erasure has occurred. (Block 112). If all flags have not been reset, then Algorithm into block 101 for re-erased block with set flag return.   At block 108, if the cell does not pass the erase test, or passes, If it is the last LSB of the lock, then the algorithm proceeds to block 113 Execute a branch instruction. In block 113, the algorithm returns to the erasure detection. Test for the pass and end of block. At the end of the block If yes, then the erase flag for the block is reset (block Lock 114). Cell is not at end of block, erase flag for block If has not been reset now, then the MSB address is stored in the next block. Increment to go, LSB address is reset (block 115). this At that point, loop through other blocks that have configuration flags for erase verification The algorithm then returns to block 106.   After the erase check, a soft program repair pulse is applied to the block with the set repair flag. Apply to the lock. Thus, the word line voltage may be at ground or, preferably, at about 0. It is initially set at 3 volts (step 116). In this embodiment, Repair for approximately 200 ms on the bit line for the sector with the recovery flag The word line voltage is maintained while applying the pulse (step 117). Finally, The repair flag is reset without a repair check operation (step 118). Restoration During the reset, the top block select transistor of the selected sector And in this case, 5. A 5 volt repair voltage is applied to the selected cell. (In the case of sector erase) or the entire chip (in the case of chip erase). Apply to the buried drain line to repair these over-erased cells. repair The pulse depends on the channel length and other cell parameters, the repair pulse length, and other factors. And about 3. About 10 from 5 volts Up to 0 volts Good.   FIG. 5 illustrates the software over an implementation in which word lines are pulled to ground during soft programming. Slightly higher than ground to increase the speed of the software program process A word line driver adapted to drive a word line of a selected sector is shown. The circuit of FIG. 5 includes a first input 501 connected to a word line decoder. Input 501 Is connected to the node 502 via the pass transistor MN2. Tiger The transistor MN2 is biased by the voltage VDD connected to its gate. . Node 502 is connected to the drain of n-channel transistor MP1. The source and n-well of transistor MP1 are connected to supply AVX. p-cha The gate of the flannel transistor MP1 is connected to the word line 503 (WL). No Is also connected to the gate of p-channel transistor MP2 and the n-channel transistor. It is connected to the gate of transistor MN1. Source and transistor of transistor MP2 The n-well of transistor MP2 is connected to supply voltage AVX. Transistor MP The drain of 2 is connected to word line 503. The drain of transistor MN1 is Connected to line 503. The source of transistor MN1 is pulled Connected to down driver circuit.   The pull-down driver circuit 76 is a software program ENSPG that can be used. An input 92 is included. Input 92 is an n-channel transistor approximately 3 μm wide and approximately 100 μm long. Connected to the gate of transistor 93. The drain of the transistor 93 is supplied VD D and the source of transistor 93 is connected to node 504. node 504 is a gate of an n-channel transistor 95 having a width of about 4 μm and a length of about 1 μm. And the drain. The source of the transistor 95 is the transistor MN1 Connected to the node 99 which is also connected to the source of Node 99 is an intrinsic n channel Beyond the flannel transistors 94 and 96, they are connected to the ground terminal. true N-channel transistor 96 has its gate and drain connected to node 99. It has a rain and its source connected to ground. The transistor 96 is The width is about 20 μm and the length is about 1 μm. Transistor 94 is connected to node 99. And its source connected to ground. Transis The gate of the inverter 94 is connected to the output of the inverter 505. Transistor 94 , About 200 μm in width and about 1 μm in length. Inberg 505 input is available Software program ENSPG input 92.   During the soft programming process, all word lines drive input 501 Has been selected high. This uses a pull-down transistor MN1. While enabled, pull-up transistor MP2 is disabled. Word line 503 When pulled down, transistor MP1 is pulled up at node 502 .   During the available soft program sequence, pull-down driver 76 , Receive a high usable soft program signal. This is transistor 9 3, 95 and 96 are turned on and transistor 94 is turned off. This This is in this embodiment about 0. Word line voltage at node 503, 3 volts higher Create a voltage driver that holds Available soft program pulses When finished, the signal goes low at node 92, turning off transistors 93 and 95. And the transistor 94 is turned on. Transistor 94 is a transistor Slightly larger than transistor 96, causing node 99 to fall substantially to ground potential.   Turning to FIG. 6, another embodiment of the present invention is shown. Here, the repair pulse has two Applied to sequential steps. In the first step, the word line voltage is At a first level above ground, and in a second step, the word line voltage is Maintained at a second, higher level. In advance, these similar steps in FIG. I do. However, FIG. 6 showing between steps 607 to 610 is different, The line voltage is maintained at two different levels, and the repair pulse is applied to the bit line. It is.   First, step 607 determines if the word line voltage is, for example, .0. 1 volt and 0. 2 bolts Between, for example, approximately 100 ms above ground provide. The first phase of the repair pulse is maintained during step 608. 1st Seo During lower program steps 607 and 608, lower word line bias is applied. By applying it first, the current in the "over-erased" cell will be higher and the wordline power will be higher. Cells that are smaller than those that can occur with pressure, and the majority of over-erased cells Cells (ie they restore the threshold voltage to a better value) ). Thus, after the first soft program steps 607 and 608, some Are calibrated and a second step is applied. The second step Steps 609 and 610 reduce the word line voltage to approximately 0.5. 4 volts and 0. Between 5 volts During the repair pulse is applied, for example, approximately 10 Apply an additional time of 0 ms.   Therefore, during the repair pulse, the word line voltage is driven in two stages, the first stage being the word stage. When the line voltage is approximately 1 volt and 0. 100 volts while maintained between 2 volts ms, the second phase being approximately 0,0 ms. 4 volts and 0. Stay between 5 volts While held, it occurs for 100 ms. This two-step process is smaller Approximately 200 m for the small computational current and the whole repair process on the chip Soft programming of over-erased cells with better computational efficiency requiring only s Improve   Turning to FIG. 7, three levels of pull-down driver circuits, including circuit dimensions and shapes. The route diagram provides a word line driver for the two-step embodiment of FIG. , Used in combination with the circuit of FIG.   The three level pull down driver of FIG. 7 is provided at node ZD2 701 Operates to control voltage. The circuit has a first input at node 702 and a node 703 has a second input. The first input of node 702 is an available soft G program ENSPG pulse. The second input of node 703 is A control signal SPG1 for indicating the first stage of the program algorithm . The input of the node 702 is the gate of a transistor M41 having a width of 3 μm and a length of 1 μm. Connected to. The drain of the transistor M41 is connected to the supply VDD. The source of transistor M41 is connected to the source of p-channel transistor M42 and Connected to n-well. This transistor is protected by an asterisk. Formed in the protective ring. The gate and the drain of the transistor M42 are connected to a node 701. Node 701 also has a width of 250 μm and a length of about 8 μm Connected to the drain of n-channel transistor M43. Transistor M43 Are connected to ground.   Node 701 also has a width of about 100 μm and a length of about 0.5 μm. 8 μm n-channel transformer The drain of the transistor M47, the drain of the intrinsic n-channel transistor M44, Connected to the gate. The transistor M44 has a width of about 350 μm and a length of about 1. 6 μm. The sources of M47 and M44 are connected to the drain of transistor M45. Continued. The transistor M45 has a width of about 15 μm and a length of about 1. 6 μm. G The gate of the transistor M45 is connected to the source of the transistors M41 and M42 at the node. Connected to. The source of the transistor M45 is connected to the ground 25.   Transistor M43 receives the available soft program pulse. To the output of inverter 704, which has its input connected to node Continued.   As described above, using the driver of FIG. 7, node ZD2 has three different It can be driven against a level. Soft programs available on node 702 When the pulse is low, transistor M41 is off and transistor M4 3 is on. The transistor M43 sets the node ZD2 to substantially ground. Pull. During an available soft program pulse, node 702 is high. This turns on transistor M41 and turns off transistor M43. Off. When the transistor M41 is on, the gate of the transistor M45 is Then, lift M45 to turn on. When the transistor M41 is on , Transistor M42 is also on, and pulls transistor M44 high. The gate of the transistor M44 to be turned on is pulled. Therefore, the transistor M44 And M45 connect node ZD2 to about .0. Above ground less than 5 volts Pull down to the level. When the input is high at node 703, this also D2 to about 0. Transistor M further pulling down to less than 2 volts Turn 47 on.   As described above, the node 701 supplies the potential ZD2 to the word line driver of the array. I do. A typical word line driver is shown in FIG. It is, as shown, the node 701 Receives the ZD2 signal. Other inputs are the IN of node 801 and the input of node 802. Includes the output of the decoder for word lines that are VXP and XR at node 805. Change The positive voltage supply AVX is supplied to the node 803. The negative voltage supply NVPP is Provided at node 804. The supply level of the three signals depends on the operation mode of the circuit. Is controlled by the supply circuit. The control signals PG1 and PG2 are Used to select the voltage level for 806 (WL).   The signal IN and the signal XR are high, the control signal PG1 is low, and the control signal When PG2 is high, then supply the value of ZD2 at node 701 to the word line. .   The signal IN at the node 801 is connected to the decode signal XR at the node 805. To the source of an n-channel transistor M10 having a gate of Transi The drain of star M10 is connected to node 825. Also, the p-channel transistor The drain of star M20 is connected to node 825. Transistor M20 saw And its n-well are connected at node 803 to the supply AVX. Node 802 And when control signal VXP is low, node 825 goes high between AVX signals. Drawn. When VXP is high, transistor M20 is not included in the circuit. Node 825 is connected between the gate of n-channel transistor M22 and the p-channel transistor. It is connected to the gate of the transistor M21. The source and n-way of the transistor M21 Is connected to the supply AVX. The source of the transistor M22 outputs the signal ZD2. It is connected to a node 701 for receiving.   The node between the drains of the transistors M21 and M22 is referred to as 832. node 832 is a word line at node 806 via p-channel pass transistor M30. Connected to. The n-well of the transistor M30 is connected to the bias voltage AVW. It is. The gate is connected to the control signal PG1. Node 806 at the word line also Negative supply NVPP at node 804 via channel pass transistor M31 Connected. The n-well of the transistor M31 is connected to the bias voltage AVW. You. The gate of the transistor M31 is connected to the control signal PG2.   Using the circuit of FIG. 8, WL 806 controls the voltage (by transistor M30). From the left path or from the right path (by transistor M31). You. The left pass is a very high positive voltage for programming (12. 6 volts VPP level), normal read voltage level (such as 5 volts), soft Regarding programming (0. 1 volt and 0. 2 bolts (like 4 volts) Te It is simply used to supply the top voltage or ground. Right pass is (-7 button Used to supply a negative voltage (like default).   During a predetermined mode of operation, AVX is (4. VDD as low as 4 volts) From the read voltage at the level (12. High program power (as high as 6 volts) Can be switched to the order VPP. AVX resets the state from the high program potential. To the ground potential. In this case, the ZD2 line 701 is negative via M22. Pushed towards voltage.   By adding a guard ring to the circuit of FIG. 7, this negative push in ZD2 Therefore, it is possible to prevent the latch-up problem that occurs. Good strap P-substrate and n-well (so-called "protection ring") with Used to avoid In such a case, the double assemblage next to M42 in FIG. Protective ring (shown as tallis **) is M42 to prevent latch-up. Placed in AVX switch returning from VPP level to VDD level Medium, ZD2 negative spike damages M43, M44, M45 and M47 obtain. Thus, the single assemblage next to M43, M44, M45 and M47 in FIG. Protective rings (identified by a alisk *) can also be attached to these transistors. Is preferred.   FIG. 9 illustrates, for example, lines 10 and 11 of FIG. 4. To get within the buried drain line of the sector 5 volt soft program In order to be able to use the system pulse, the transistor 19 of FIG. For driving a top block select transistor corresponding to and 21 Is illustrated. The driver of FIG. 9 serves as a reference, as described fully herein. No. 5,414,664, incorporated by reference above. Used in conjunction with algorithms. The sector erasure algorithm described in such patents For each scheme, each sector is associated with its block erase flag. According to the present invention , Repair flag erases the chip in addition to the block erase flag, Set to the sector to be cleared after the ram cycle. Therefore, in one embodiment According to each local bit line is a deep 32 word line, the local bit line Four top blocks used to decode the four sets of lines Selection The select signal (TBSEL in FIG. 2) shares a single driver as shown in FIG. These four 32-word segments of the array correspond to a single sector. this In the design, there is one flag per sector.   During the soft program pulse for the selected sector, the driver At line 901 (called TBSEL in FIG. 2) to pull it high -Connected to block select signal TBSEL. This signal is the SR flip-flop. 904, the sector repair flag of the line 903 and the available soft program of the line 903. It is controlled by the RAM signal ENSPG. The signal on line 902 is Supplied at an output corresponding to a reset flag register (not shown). Connected to latch 904. This latch is connected to line 9 connected to the reset input. 05 has a reset signal RESALL. Flag 902 goes high and latches When 904 is set high, the available soft program on line 903 Enable a NAND gate 906 to switch in response to a signal. The flag corresponding to the sector is set during the usable soft program pulse If so, then the signal on line 907 is driven low. In addition, signal line 9 07 is high for unselected sectors. NAND gate 908 , Block 901. Available software for line 903 During the program pulse, the NAND gate goes low for the selected sector. Is controlled by a signal line 907. Therefore, the selected sector is N It will have a high value at the output of AND gate 908. This is pass gate 9 10 is supplied to a node 901 which drives a block selection transistor. The pass gate 901 is an intrinsic device having a width of about 20 μm and a length of about 2 μm.   Node 901 is connected to a pull-up circuit indicated generally by 911. 9 for the whole The pull-up circuit shown at 11 has its gate connected to a high programming potential. And an n-channel transistor M48 having a drain (15 μm wide × 2 μm long) )including. The source of transistor M48 is connected to its gate connected to node 901. Transistor M42 (width) having a gate and its source connected to node 912. 25 μm × length 1. 8 μm). Node 912 is a node The drain of transistor M43 having its source connected to Connected to gate. The transistor M43 has a true width of about 25 μm and a length of about 3 μm. Device. Node 912 also includes a transistor connected as a capacitor. Star M45 (width 3 μm × length 289. 33 μm). Tran The source and drain of transistor M45 are connected to the clock signal on line 913. You. When node 901 is high under the control of NAND gate 908, the clock If signal 913 is available, transistor M42 turns on and blocks Approximately 5. through select transistor to buried drain line To pass 5 volts Occurs when raising node 901 to a sufficient level.   As shown, a similar set of circuits on the right is included, as indicated by box 914. Is expressed. The RESALL signal on line 905 is a soft program Asserted at the end of the cycle to reset all repair flags.   Using the circuits of FIGS. 7-9, all cells in the selected sector are Simultaneous soft program pulse via select transistor decoding Connected to. Word lines in sectors that are not selected will apply to cells from which they have been erased. It is a low enough value that does not disturb. Therefore, only the selected sector Program pulse is received through the selected TBSEL transistor. This fruit In an embodiment, all word lines (whether selected or not) are simultaneously set to .0. 1 bol Or 0. Note that it is driven to a 4 volt ground. It repair TBSEL transistor used to select the sector to be performed. Change At the same time, the selected transistor receives the pulse simultaneously. This means that the whole Simultaneously guarantees a fast soft programming process on the whole module or the entire array I do. A large number of erased cells are not disturbed during soft programming and leaks Since the number of cells is limited to a small number within a given sector, the activation circuit is controlled. Follow Soft programming is efficient and fast for the selected sector. Very good repair of formed and over-erased cells.   FIG. 10 shows the overlap along trace 1000 starting at a threshold of about -1 volt. Over-erasure starting at a threshold of about 0 volts along trace 1001 with the cell left Along the cell and trace 1. A large number of cells with a threshold of 6 volts, Approximately 1. along trace 1003 Source for large number of cells with 6 volt threshold 5 is a graph showing the performance of the lift program pulse. The figure shows the logarithm of seconds on the horizontal axis. The vertical axis shows the cell programming threshold and the length of the soft programming pulse. You.   As can be seen by traces 1002 and 1003, the threshold Since the pressure remains substantially constant throughout the graph, a large number of cells Until the second, it is unaffected by soft program pulses. This is The gate voltage of race 1003 may cause a slight disturbance of a large number of cells even if the soft Indicates that it does not occur during the programming algorithm and has a voltage up to about 05 volts. Even if raised, it is true. See traces 1000 and 1001 to determine Thus, during the entire pulse, the drain voltage is about 5 volts and the gate voltage is About 0. 2 volts and the trace has a threshold voltage of about 1 volt after 200 ms. Gather in an area that is   Accordingly, the present invention provides a method for rewriting erased cells on a block Offer to repair. In addition, the present invention provides a method for producing the composition of the present invention having a capacity of about 0.1. 1 volt and 0. 5 volts A repair pulse that maintains the word line at a voltage at or above ground, such as between And applying. In addition, the present invention provides a repair pallet in two successive steps. Supplying the erased cells to the erased cells. In the first stage, the word line voltage is Approximately 0.1 ms for about 100 ms 1 volt and 0. Maintained between 2 volts . In the second stage, the word line voltage is approximately 0.5 ms for approximately 100 ms. 4 volts And 0. It is maintained between 5 volts.   The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. You. The invention should not be exhausted and limited to the precise form disclosed. clearly, Many modifications and variations will be apparent to practitioners skilled in the art. The scope of the present invention is the following patents It is to be defined by the appended claims and their equivalents.

────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Iu Tom Dan-Shin             United States California             95035 Milpitas Los Potosdos             Live 793 (72) Inventor Sean Fuchsia             Taiwan Shin Chu Science Based               Industrial Park Water             Front Road First 2-3E             H (72) Inventor Lee Ai Rong             Taiwan Iran Shantou Chen               Kim May Road 471 (72) Inventor Chen Chia Shin             Taiwan Iran Shan Lo Tun             I Quo Road 33 (72) Inventor Chen Hyun Sung             Taiwan Key Run City I You               Road 29 (72) Inventor Liu Yuan Chang             Taiwan Miao Li City Chunk             N Riao Ping Street 14 (72) Inventor Shaw Tseng Huey             Taiwan Shin Chu Shan Shin Pho             Ping Street Lane 15-120 (72) Inventor Chang Cuen Long             Taiwan Taipei Pao Ye Road             109109 Ally 23-21-F4 (72) Inventor One Ray Lin             United States California             95035 Milpitas Oroville Road               520

Claims (1)

[Claims] 1. A set of floating gate memory cells comprised of a plurality of rows and columns;   A plurality of cells connected to a drain terminal of each row of the set of cells; A drain line,   A plurality of sources connected to the source terminals of each row of the set of cells. Source line,   A plurality of cells connected to a control gate terminal of each column of the set of cells And the word line   Circuits for continuous supply of voltage below the selected limit of threshold voltage Supply some cells below the threshold of the cell to give rise to some cells with a threshold Then, while setting the voltage of the multiple word lines to a level below the selected limit, Repair during repair time while crossing a number of source lines and multiple drain lines A voltage for supplying a pulse, wherein the threshold voltage of the cells of the set To set the state, multiple drain lines, source lines, and word lines A control circuit connected to the A floating gate memory integrated circuit having: 2. The control circuit pulls a plurality of lines to substantially ground during a repair pulse. The integrated circuit according to claim 1, including a circuit for: 3. The control circuit causes the plurality of word lines to be above ground but about The circuit of claim 1 including a circuit for pulling to a level less than 1 volt. Integrated circuit. 4. The control circuit causes the plurality of word lines to be above ground but about Claim 1 including a circuit for pulling to a level less than 0.5 volts. Integrated circuit. 5. The control circuit controls a plurality of word lines to a first level during a first interval time. For the second interval higher than the first level during the second interval time within the repair pulse. 2. The collection of claim 1, including circuitry for driving to two levels. Product circuit. 6. 2. The repair interval of claim 1, wherein the repair interval lasts about 200 ms. Integrated circuit. 7. 6. The repair interval according to claim 5, wherein the repair interval time lasts about 200 ms. Integrated circuit. 8. The circuit drives a plurality of drain lines with a positive voltage and a plurality of source lines. Applying a repair pulse by driving the transistor substantially at ground potential. 3. The integrated circuit according to claim 1, wherein 9. A circuit drives multiple source lines with a positive voltage and multiple drain lines Applying a repair pulse by driving the device substantially at ground potential. 2. The integrated circuit according to item 1. 10. At least one of the plurality of drain lines and the plurality of source lines The integrated circuit according to claim 1, including a current limiting circuit. 11. Each sector is         Multiple cells connected to the drain terminal of each row of cells in the sector A number of drain lines,         Multiple connected to the source terminal of each row of cells in the sector Source line and         Connected to the control gate terminal of each column of cells in the sector Multiple word lines, Floating gate memory arranged in a plurality of rows and columns having a plurality of sectors, comprising: An array of cells;   Circuits for continuous supply of voltage below the selected limit of threshold voltage A cell in the selected sector that results in some cells having a falling threshold Voltage below the selected threshold, and then the voltage of multiple word lines below the selected limit While setting the level, cross multiple source lines and multiple drain lines Provide a circuit to supply a repair pulse to the selected sector during the repair time between cuts. The threshold voltage of the cell in the selected sector, including the supply voltage. Multiple drain lines in multiple sectors and a soft A control circuit connected to the source line and the word line; A floating gate memory integrated circuit having: 12. The control circuit pulls a plurality of word lines substantially to ground during the repair pulse The integrated circuit according to claim 11, comprising a circuit for: 13. The control circuit sets a plurality of word lines above ground, but about 12. The method of claim 11, including circuitry for pulling to a level less than 1 volt. Integrated circuit. 14． The control circuit sets a plurality of word lines above ground, but about 12. The method of claim 11, including circuitry for pulling to a level less than 0.5 volts. An integrated circuit as described. 15. The control circuit sets a plurality of word lines to a first level during a first interval time. Higher than the first level during the second interval time within the repair pulse 12. The circuit of claim 11 including circuitry for driving to and from a second level. Integrated circuit. 16. 12. The method according to claim 11, wherein the repair interval time lasts about 200 ms. An integrated circuit as described. 17． 16. The repair interval according to claim 15, wherein the repair interval lasts about 200 ms. An integrated circuit as described. 18. The circuit drives a plurality of drain lines with a positive voltage and a plurality of source lines. Applying a repair pulse by driving the line substantially at ground potential 12. The integrated circuit according to claim 11, wherein: 19. A circuit drives multiple source lines with a positive voltage and multiple drain lines. Applying a repair pulse by driving the pump at substantially the ground potential. 12. The integrated circuit according to claim 11, wherein: 20. At least one of the plurality of drain lines and the plurality of source lines 12. The integrated circuit according to claim 11, including a current limiting circuit. 21. The array comprises a plurality of global bit lines and a plurality of bit lines. A plurality of drains of a set of sectors in the array. Sector drain selection corresponding to the drain line in the drain line And a transistor, wherein the circuit supplies a repair pulse to the sector / drain selection transistor. Feeds multiple drain lines in selected sectors through transistors The integrated circuit according to claim 11, wherein: 22. The array includes a source supply line and the source supply line connected to the array. Sector / Source Selection Transformer Combined with Multiple Source Lines in a Set of Sectors And a circuit for generating a repair pulse by using a sector / source select transistor. Claim to supply multiple source lines in a selected sector via 22. The integrated circuit according to item 21. 23. Wherein each of the cells has a drain, a source, and a control gate; Control gates communicate with word lines so that they can be programmed and erased A memory array containing multiple blocks of configured floating gate memory cells A floating gate integrated circuit having A method for erasing said programmed floating gate memory cell, ,   Erase the cell,   Maintaining said word line at a predetermined word line voltage level;   Generating a repair pulse having a repair voltage level;   Maintaining the plurality of blocks of floating gate cells during the word line voltage maintaining step Selecting said plurality of blocks of floating gate memory cells in relation to the others Applying the repair pulse to the selected block. 24. The repair pulse is used to determine whether the over-erased cell is a previously applied repair check operation. Repairing over-erased cells so that they can be re-programmed at a later time Item 24. The method according to Item 23. 25. Maintain word line voltage levels approximately above ground and 0.5 volts 24. The method of claim 23, comprising: 26. In two stages, including a first low voltage stage and a second high voltage stage, the word 24. The method of claim 23, comprising maintaining a line voltage level. 27. During the first stage, the method includes reducing the word line voltage below about 0.2 volts. 27. The method of claim 26, comprising maintaining. 28. During the second stage, the method comprises: reducing the word line voltage level to about 0.3 volts. 27. The method of claim 26, comprising maintaining between about 0.5 volts. . 29. Each cell has a drain, a source, and a control gate, and controls the cell. A gate that communicates with a word line whose gate is capable of maintaining a word line voltage; Memory cells, including floating gate memory cells configured to be erasable; ,   Floating gate memory in memory array to produce over-erased cells A control circuit for erasing the cell;   A first step in which the word line voltage is at a first low voltage level; While providing two stages, the second stage where the pressure is at a second high voltage level, The repair pulse crosses the source and drain of the floating gate memory cell. Said control circuit further configured to generate a return pulse; A floating gate integrated circuit. 30. The first phase of the repair pulse is approximately 100 ms in duration, Claim 2 wherein the second phase of the repair pulse is approximately 100 ms in duration. The circuit of claim 29. 31. While the repair pulse is applied to the erased cell, the control circuit Is configured to maintain the word line voltage between approximately ground and 0.5 volts. 30. The circuit of claim 29 formed. 32. During the first phase of the previous period, the word line voltage is approximately ground and about 0.2 volts. 30. The circuit of claim 29, wherein 33. During the second stage, the word line voltage is approximately 0.3 volts and 0.5 volts. 30. The circuit of claim 29, wherein 34. Each sector is           Connected to the drain terminal of each row and column of the sector Multiple drain lines;           Connected to the source terminal of each row of cells of said sector Multiple source lines,           Connected to the control gate terminal of each column of the cells of the sector Multiple word lines,         Floating gate memory organized in multiple rows and columns with multiple sectors An array of moly cells,   Multiple sector flags indicating which sectors of the array should be erased in response to the input signal When,   Circuits for continuous supply of voltage below the selected limit of threshold voltage A cell in the selected sector that results in some cells having a falling threshold Voltage below the selected threshold, and then the voltage of multiple word lines below the selected limit While setting the level, cross multiple source lines and multiple drain lines During repair time between cuts, select repair pulse as indicated by multiple sector flags A plurality of sector flags, including a voltage for supplying a circuit for supplying the selected sector. The threshold voltage of the cell in the selected sector indicated by the threshold Multiple sector flags and multiple sectors in multiple sectors to set And a control circuit connected to the drain line, the source line, and the word line. A floating gate memory integrated circuit. 35. The control circuit pulls multiple word lines substantially to ground during the repair pulse. 35. The integrated circuit according to claim 34, comprising a circuit for: 36. The control circuit sets the plurality of word lines above ground during the repair pulse but approximately 35. The method of claim 34, including circuitry for pulling to a level less than 1 volt. An integrated circuit according to claim 1. 37. The control circuit sets the plurality of word lines above ground during the repair pulse but approximately Claim 3 including circuitry for pulling to a level less than 0.5 volts. An integrated circuit according to claim 4. 38. The control circuit controls a first interval within a repair interval time. A second level higher than the first level during the second interval, 35. The level of claim 34, wherein the level includes circuitry for driving a plurality of word lines. Integrated circuit. 39. 35. The repair claim of claim 34, wherein the repair interval time lasts about 200 ms. Integrated circuit. 40. Claim 38. The repair interval time lasts about 200ms. Integrated circuit. 41. The circuit drives a plurality of drain lines with a positive voltage and a plurality of source lines. Applying a repair pulse by driving the line substantially at ground potential 35. The integrated circuit of claim 34. 42. The circuit drives a plurality of source lines with a positive voltage and a plurality of drain lines. Applying a repair pulse by driving the line substantially at ground potential 35. The integrated circuit of claim 34. 43. In multiple sectors, multiple drain lines and multiple source lines 35. The method according to claim 34, further comprising a current limiting circuit in at least one of the components. An integrated circuit as described. 44. Array with multiple global bit lines and multiple bit lines A bit line at a plurality of drain lines of a set of sectors in an array. And drain select transistor coupled to drain line in transistor And a circuit for controlling the sector drain selection according to the plurality of sector flags. Repair drain to multiple drain lines in selected sector via transistor 35. The integrated circuit according to claim 34, wherein said integrated circuit supplies a pulse. 45. The array comprises a source supply line and a plurality of sets of sectors in the array. A sector source selection track coupling the source supply line with a source line; A circuit for selecting a sector source according to the plurality of sector flags. To multiple drain lines in the selected sector via select transistors. 35. The integrated circuit according to claim 34, wherein the integrated circuit supplies a return pulse.