JP2000358056A - Physical layer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a consistent device information even in a device where ports of different characteristics are intermingled by providing one or more subcontrollers between at least one port and a main controller. SOLUTION: Two of three ports are DS ports 4 and the other one is a beta port 7. A subcontroller 8 which is not connected with a link layer circuit is connected between the beta port 7 which is only one having different characteristic and a main controller 2, to constitute a physical layer circuit 1-1. In this constitution, all the controllers including the subcontroller 8 are connected with respectively only ports having one kind of characteristic. Since each controller independently has a device information 6, a correct device information can be obtained by the whole bus by describing a part describing the characteristic of a port among device information, which each controller has, based on the capacity of the port directly connected with the controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a physical layer circuit used in a data transmission method conforming to a standard.

[0002]

2. Description of the Related Art High-speed serial bus IEEE1394-1
P13 considered as 995 or its additional specifications
94a is a standard developed for transmitting large amounts of data such as video at high speed between information devices such as computers and digital video cameras. This standard realizes data transmission using a transmission medium including four electric signal lines (two twisted pair lines).

[0003] The P1394b Standardization Committee is discussing a data transmission method using two optical fibers as a transmission medium.

[0004] IEEE 1394-1995 or P13
In 94a, characteristic values that may vary depending on the port, such as the maximum transmission speed, the presence or absence of power supply capability, and the maximum repeat delay time, are recorded in the physical layer circuit as part of device information. This information is determined not for each port but for each physical layer circuit. This information can be read from other devices on the bus, and based on this information, a packet called self-ID packet indicating its own capability is generated and transmitted to the bus. Has also become.

[0005] In P1394b, some information is recorded for each port. However, not all information unique to a port is used. Is not specified.

FIG. 9 is a diagram of a self-ID packet when the physical layer circuit has three ports. This figure omits portions describing other than port characteristics.
Numeral 11 is called a PHY_SPEED field, which describes the maximum transmission rate that the physical layer circuit can handle. Although this value is determined irrespective of the port capability, the transmission speed may actually be limited by the port capability, and thus should be originally determined for each port. 12
Is called a POWER_CLASS field, which describes whether or not there is a power supply capability and its capability value. This value is also a value that may be different for each port.

There is a maximum repeat delay time as device information which is not included in the self-ID packet but may be different for each port. The maximum repeat delay time is a maximum value of a delay time allowed in a repeat between ports that outputs an input from a bus connected to a certain port to a bus connected to another port.

[0008] The maximum repeat delay time is IEEE139
The upper limit is defined in the 4-1995 standard. The maximum value of the delay time allowed until data from the link layer is output to the bus is defined by the P1394a standard.

The conventional method is shown in FIGS. Hereinafter, each of them will be described.

FIG. 5 is a block diagram of a circuit that supports only electric signal lines as a transmission medium in accordance with IEEE 1394-1995 or P1394a.

FIG. 5 shows the configuration of a physical layer circuit having only one port. 1-5 is a physical layer circuit for performing communication,
It is connected to a link layer circuit 3 as an upper layer and one connector 5. The connector 5 is connected to the bus.
The physical layer circuit is roughly divided into one controller 2 for controlling the entire physical layer circuit, and the same number of ports 4 as connectors 5 for directly exchanging information with the bus. In this example, the port 4 is a port called a DS port, which is connected to a bus composed of electric signal lines. self-ID
The device information 6 to be referred to when generating a packet is recorded in the controller 2.

1-6 of FIG. 6 is a configuration diagram of a physical layer circuit provided with a plurality of (three in this example) DS ports 4.

1-7 in FIG. 7 shows that all three ports are DS ports as in FIG. 6, but 4-1 having a maximum transmission speed of 400 MHz and 4-2 having a maximum transmission speed of 200 MHz are mixed. This is the physical layer circuit in the case of

1-8 in FIG. 8 is P1394b or the like,
This is a physical layer circuit in which S ports and ports having different characteristics called beta ports are mixed. 1-5 is different only in that two types of ports, DS port 4 and beta port 7, are mixed.

Even in the physical layer circuit having a plurality of ports as in 1-6, 1-7, and 1-8, there is only one device information 6 because the device information 6 is recorded in the controller 2.

Consider a case where a device actually issues a self-ID packet. The self-ID packet is generated based on the device information 6 in the controller as described above. Therefore, the self-ID packet transmitted from any port is the same.

A problem arises when the physical layer circuit has one port as in the example of FIG. 5 or when the ports provided in the physical layer circuit have the same characteristics as in the example of FIG. Does not occur. However, even when ports having different characteristics coexist as shown in FIGS. 7 and 8, the same self-ID packet is transmitted from all the ports,
There is a problem that even if the information is correct on a bus connected to a certain port, the information is incorrect on a bus connected to another port. Specifically, for example, in FIG. 7, since the maximum possible transmission rate of the physical layer circuit is 400 MHz, the PHY_SPEE of the self-ID packet is
D field 13 is set to 400 MHz,
Actually, the port 4-2 can handle only the speed up to 200 MHz, and the information does not match the actual situation.

As described above, as a method for resolving the contradiction between the actual device state and the device information, Japanese Patent Application Laid-Open No.
There is a method disclosed in Japanese Patent Application Laid-Open No. 9-90. In this method, the transmission speed of all ports provided in the physical layer circuit is adjusted to the maximum possible transmission speed of the slowest port, and the transmission speed overwrites the corresponding part of the device information, so that the device information and the speed of the port are Are matched.

[0019]

As described above, even when ports having different characteristics coexist in one physical layer, the physical layer has only one type of device information. Could have. As a result, problems such as transmission of a self-ID packet including information that does not match the actual situation and return of incorrect information in response to access from another device occur.

In the method disclosed in Japanese Patent Application Laid-Open No. H11-98159, the transmission speed can be made to match the device information and the speed of the port. May still have information that does not match the actual situation. Also,
Since the overall transmission speed is adjusted to the slowest port, for example, when repeating from the top port 4-1 in FIG. 7 to the middle port 4-1, it is possible to repeat at a transmission speed of 400 MHz. Although this method should be used, there is a waste that this method can be repeated only at a transmission speed of 200 MHz.

Further, as described above, in the standard conforming to IEEE 1394, an upper limit is set for a maximum delay time required for repeat between ports and a delay time generated for outputting data from the link layer circuit to the bus. It is not possible to connect a bus made of a transmission medium that requires a time exceeding the upper limit time for the repeat between ports or the repeat from the link layer to the bus.

The present invention has been made in order to solve these problems, and it is intended to provide consistent device information even in a device in which ports having different characteristics coexist. It is an object of the present invention to support a transmission medium in which the delay time between the link layer and the bus exceeds the limit of the IEEE 1394-1995 standard.

[0023]

The physical layer circuit according to claim 1 of the present invention is a physical layer circuit for performing communication conforming to IEEE 1394 having one main controller and one or more ports, and One or more sub-controllers are provided between one port and the main controller.

A physical layer circuit according to a second aspect of the present invention comprises:
2. The physical layer circuit according to claim 1, wherein the main controller and the sub-controller include at least information unique to a port directly connected to the controller.

The physical layer circuit according to claim 3 of the present invention comprises:
3. The physical layer circuit according to claim 1, wherein port access information stored in a main controller or a sub-controller closest to each port is returned in response to access to each port from another device. And

One or more controllers (hereinafter, referred to as sub-controllers) are connected between at least one port and a normal controller (hereinafter, referred to as a main controller) to constitute a physical layer circuit. By describing the information of the directly connected port in the device information of the controller, and by accessing the bus, by returning the port specific information stored in the controller directly connected to the port connected to the bus, Provide device information that does not conflict with actual device capabilities across the bus.

By providing one or more sub-controllers between the port and the main controller, the maximum repeat delay time between the ports is equal to the sum of the maximum repeat delay times of the device information of all the controllers existing between the ports. The link layer-bus delay time is permitted by the sum of the maximum link layer-bus delay time of the main controller and the maximum repeat delay time of all sub-controllers provided between the port and the main controller. Therefore, it is possible to support a bus made of a transmission medium in which the repeat delay time between ports and the delay time between the link layer and the bus exceed the limit of the standard.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) (Case where Two Types of Ports are Mixed) FIG. 1 is a configuration diagram of a physical layer circuit according to the present invention where two types of ports are mixed.

Of the three ports, two are DS ports 4 and one is beta port 7. A sub-controller 8, which is not connected to a link layer circuit, is connected between a beta port 7 having only one characteristic and the main controller 2, thereby forming a physical layer circuit 1-1. Sub-controller 8
Has only limited functions as compared with the main controller 2 and can therefore be configured smaller than the main controller.

In this configuration, only one type of port is connected to all controllers including the sub-controller. Since each controller has its own device information 6, the part describing the characteristics of the port in the device information of each controller is described on the basis of the capability of the port directly connected to the controller. Can provide correct device information.

(Embodiment 2) (Case where Two Ports are Connected to One Subcontroller) FIG. 2 is a modification of the case where the configuration is basically the same as that of FIG. The circuit 1-2 also has two DS ports 4 and one beta port 7, as in the case of 1-1 in FIG. As shown in this figure, a configuration in which a sub controller 8 is connected between two DS ports and the main controller 2 is also conceivable.

(Embodiment 3) (Case where three or more types of ports coexist) FIG. 3 shows a case where three types of ports coexist. Here, DS port 4
And an X port 9 having characteristics that are neither of the above and the beta port 7 are considered. Also in this case, a sub-controller is inserted between a port having a different property and the main controller to configure the physical layer circuit 1-3. Port characteristics of the device information 6 of each controller are described based on the capabilities of the directly connected ports. By providing a plurality of sub-controllers as in this example, a physical layer circuit in which three or more types of ports coexist can be configured.

(Embodiment 4) (When connecting to a bus with a large delay time) FIG. 4 shows a transmission medium in which it takes a long time to repeat data between ports and transmit data received from a link layer to a bus. 2 is a configuration example of a physical layer circuit in a case where is supported.

As described above, in the standard conforming to IEEE 1394, since the maximum delay time required for the repeat between ports and the delay time generated for outputting the data from the link layer circuit to the bus are provided with the upper limit, In the method described above, it is impossible to connect a transmission medium that requires a time exceeding the upper limit time to repeat between ports or output from the link layer to the bus.

However, as shown in FIG. 4, a sub-controller 8 is connected in series between the port 10 connected to a bus using a transmission medium having a large delay and the main controller 2 to connect the physical layer circuits 1-4. The maximum repeat delay time of the sub-controller is set to a large value (for example, to the maximum value).

By doing so, each controller behaves as if it were one physical layer. Therefore, the repeat between ports includes only the sum of the maximum delay times of all the controllers connected in series. The repeat delay time is allowed, and the link layer-bus delay time is the maximum delay time between the link layer and the bus of the main controller and the maximum delay time of all the sub-controllers provided between the port and the main controller. Since only the sum of the repeat delay times is allowed, it is possible to connect to a bus made of a transmission medium having a large delay.

(Common to First to Fourth Embodiments) In the present embodiment, a physical layer circuit for performing communication conforming to the IEEE 1394 standard has been described as an example.
Communication that supports transmission media with different characteristics, including one device information and one or more ports in the physical layer circuit, repeat delay time per physical layer circuit, data coming from the upper layer The present invention can be applied to any physical layer circuit for performing communication in which the maximum value is set for the delay time before transmitting to the communication medium.

[0038]

According to the physical layer circuit of the present invention, since the sub-controller also has the device information, it is possible to provide correct device information for each port.

By providing a plurality of controllers between the ports, it is possible to support a transmission medium in which the repeat delay time between the ports or the delay time between the link layer and the bus exceeds the limit of the standard.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a physical layer circuit according to a first embodiment of the present invention;
This is a case where two types of ports are mixed.

FIG. 2 is a configuration diagram of a physical layer circuit according to a second embodiment of the present invention;
This is a case where two ports are connected to one sub-controller.

FIG. 3 is a configuration diagram of a physical layer circuit according to a third embodiment of the present invention;
This is a case where three types of ports are mixed.

FIG. 4 is a configuration diagram of a physical layer circuit according to a fourth embodiment of the present invention;
This is the case when connecting to a bus with a long delay time.

FIG. 5 is a configuration diagram of a physical layer circuit in the related art.

FIG. 6 is a configuration diagram of a physical layer circuit in the related art, in which a plurality of same-type ports are connected.

FIG. 7 is a configuration diagram of a physical layer circuit in the related art, in which a plurality of ports of the same type are connected to ports having different transmission speeds.

FIG. 8 is a configuration diagram of a physical layer circuit in the related art, in which a plurality of different types of ports are connected.

FIG. 9 is an explanatory diagram of a self-ID packet conforming to IEEE1394.

[Explanation of symbols]

1-1 Physical layer circuit of the first embodiment of the present invention (when two types of ports coexist) 1-2 Physical layer circuit of the second embodiment of the present invention (when two ports are connected to one sub-controller) 1-3 Physical layer circuit of the third embodiment of the present invention (when three types of ports coexist) 1-4 Physical layer circuit of the fourth embodiment of the present invention (when connected to a bus having a large delay time) 5 Physical layer circuit in the prior art (when one port is connected) 1-6 Physical layer circuit in the prior art (when a plurality of ports of the same type are connected) 1-7 Physical layer circuit in the prior art (a plurality of ports are connected) 1-8 Physical layer circuit in the prior art (when a plurality of different types of ports are connected) 2 Physical layer controller 3 Link layer circuit 4 DS port 4-1 DS port with a transmission speed of 400 MHz 4-2 DS port with a transmission speed of 200 MHz 5 Connector 6 Device information 7 Beta port 8 Subcontroller 9 X port 10 X port with a large repeat delay 11 PHY_SPEED field 12 POWER_CLASS field

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuki Sumimi 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside (72) Inventor Takashi Nishimura 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Incorporated (72) Inventor Yuji Ichikawa 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside (72) Inventor Masafumi Takahashi 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka F Terms (reference) 5K032 DB04 5K033 DB04

Claims (3)

[Claims] 1. A physical layer circuit for performing communication conforming to IEEE 1394 having one main controller and one or more ports, comprising one or more sub-controllers between at least one port and the main controller. A physical layer circuit. 2. The physical layer circuit according to claim 1, wherein the main controller and the sub-controller include at least information unique to a port directly connected to the main controller or the sub-controller. 3. The apparatus according to claim 1, wherein, in response to access to each port from another device, port-specific information stored in a main controller or a sub-controller directly connected to each port is returned. 2 physical layer circuit.