JP2000357818A - Light emitting element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a light-emitting wavelength changeable during manufacture by emitting light making defect or dislocation formed in an area near an interface between a first conductivity type silicon layer and a second conductivity type silicon layer laminated thereon a light emission center. SOLUTION: A defect layer 4 which becomes a light emission center is formed in an area near a p-n junction by performing on implantation of Si, B, P, etc., for a region of a p-n type Si layer 3 of a p-n diode and then annealed. Electron and hole are injected to the defect layer 4 by making a current flow to a p-n diode. Defect and dislocation in Si crystal become a light emission center and light emission line develops in a near infrared region. The defect and dislocation which become a light emission center of a light emission line are generated by annealing after ion implantation of Si, B, P, etc., to Si crystal. The sort of defect and dislocation to be generated and the sort of a light emission line to develop depend in ion implantation conditions and anneal conditions. Therefore, if proper conditions are set, just one light emission line can be made strong.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a near-infrared light emitting device using a semiconductor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Heretofore, light-emitting elements in the near-infrared region have been mainly used for optical communication applications, and the materials thereof are 1.2 to 1.6.
InGaAsP epitaxially grown on an InP substrate, which emits light in a wavelength band of μm, is generally known.

However, a light emitting device using a compound semiconductor such as InGaAsP has a problem that the composition ratio of each component must be accurately controlled at the time of manufacturing, and that the width of a light emitting line is wide.

As a material replacing such a compound semiconductor, an attempt has been made to use dislocation-generated silicon for a light emitting element.

The use of silicon as a light emitting element is a technology that enables a light emitting element to be incorporated in a current silicon LSI, and is expected to be very practically used in terms of high integration and multifunctional devices.

However, silicon having dislocations is 1.2%.
Although it emits sharp light in a wavelength band of about 1.6 μm, it is very difficult to put a silicon light emitting element into practical use because of its low light emission intensity.

In order to solve such a problem, the present inventors have already developed a light emitting device characterized by having at least a superlattice structure comprising a mixed crystal of germanium and silicon having dislocations on a silicon substrate. Proposed (Japanese Unexamined Patent Publication No.
-280479).

FIG. 6 shows the structure of the light emitting device. Mixed crystal layer 6 of silicon and germanium on n-type silicon substrate 61
The superlattice layer 64 is formed by sequentially epitaxially growing the thin films 2 and the silicon layer 63. At this time, dislocations are generated in the epitaxially grown silicon layer by performing a heat treatment after the formation of the superlattice structure or by reducing the thickness of the silicon layer by etching after growing the silicon layer thickly. A p-type silicon layer 65 is formed on the superlattice layer 62, and electrodes 66 and 67 are formed on the p-type silicon layer side and the n-type silicon substrate side, respectively.
To form When a voltage is applied to the electrodes 66 and 67, electrons and holes recombine at dislocations generated in the silicon layer near the interface in the superlattice structure, and emit light in a wavelength region of 1.2 to 1.6 μm. Strong light emission is obtained by the superlattice structure, and light of a specific wavelength can be extracted through the filter 68.

[0009]

However, the above-mentioned prior art requires a dedicated apparatus for forming a silicon-germanium mixed crystal layer in the manufacture thereof. Also,
In the method of forming dislocations by heat treatment, dislocations are unlikely to be generated sufficiently as desired, and there is a possibility that characteristics may vary from product to product. As another dislocation formation method, a silicon layer having a superlattice structure is grown thick to generate dislocations, and then the silicon layer is thinned, a silicon-germanium mixed crystal layer is formed thereon, and this method is repeated. In such a case, such an operation must be repeatedly performed every time a silicon layer is formed, which is very complicated and time-consuming. For these reasons, there is a need for a method that does not require the use of a dedicated device and that can form dislocations sufficiently using a simpler method.

In addition, the emission wavelength of the conventional light emitting device cannot change the type of defect formed during manufacturing,
Only 1.42 μm and 1.53 μm can be selected.

Further, since the intensities of these two wavelength lights are almost the same, an appropriate filter must be selected and provided depending on which wavelength light is used.

Accordingly, an object of the present invention is to provide one emission wavelength having a sufficiently high emission intensity, which emission wavelength can be easily changed at the time of manufacturing, and that the characteristics of each product have small variations and are simple. An object of the present invention is to provide a light emitting device that can be manufactured by the method and a manufacturing method thereof.

[0013]

According to a first aspect of the present invention, a {311} defect or dislocation formed near an interface between a silicon layer of a first conductivity type and a silicon layer of a second conductivity type laminated thereon is formed as a light emission center. And a light-emitting element that emits light.

According to a second aspect of the present invention, there is provided a defect layer having a {311} defect or dislocation formed near an interface between a first conductive type silicon layer and a second conductive type silicon layer laminated thereon. The present invention relates to a light-emitting element having a structure in which defect-free layers without dislocations are alternately stacked, and emits light with a {311} defect or dislocation in the defect layer as a light emission center.
In a third aspect, the light emission is in a wavelength band of 1.2 to 1.6 μm, and the light emission intensity of the light emission line having the largest light emission intensity in the wavelength band is higher than any of the other light emission lines in the wavelength band. The present invention also relates to the light emitting device of the first or second invention, wherein the relative intensity ratio is 10 or more.

A fourth invention relates to the light emitting device according to the first, second or third invention, wherein an element isolation region is formed so as to surround at least a periphery of the defect layer.

According to a fifth aspect of the present invention, an SOI substrate having an insulating layer formed on a silicon wafer and a silicon single crystal layer formed on the insulating layer is used, and the silicon single crystal layer reaches the insulating layer. The element isolation region is formed as follows,
The light emitting device according to the fourth aspect of the invention, wherein the first conductivity type silicon layer and the second conductivity type silicon layer laminated thereon are formed in a region isolated by the device isolation region. .

In a sixth aspect of the present invention, a first electrode is formed on the second conductivity type silicon layer, and the second conductivity type silicon layer is partially removed so that the first conductivity type silicon layer is exposed. The present invention relates to the light emitting device according to any one of the first to fifth inventions, wherein the second electrode is formed on the exposed first silicon layer.

According to a seventh aspect of the present invention, there is provided the method for manufacturing a light emitting device according to any one of the first to sixth aspects, wherein ions are implanted from a second silicon layer laminated on the first silicon layer.
Thereafter, the present invention relates to a method for manufacturing a light emitting device, wherein the defects or dislocations are generated by performing annealing.

According to an eighth aspect, in the seventh aspect,
The present invention relates to a method for manufacturing a light-emitting device, wherein a light-emitting wavelength is controlled by selecting and adjusting an ion species and a dose amount in the ion implantation, a type of an annealing method in the annealing, an annealing temperature and an annealing time.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail.

First Embodiment FIG. 1 is a schematic sectional view showing an example of the structure of a light emitting device according to the present invention.

The present embodiment has a pn diode structure in which an n-type Si layer 3 is formed near the surface of a p-type Si substrate 1. Then, the n-type Si layer 3 and the p-type Si substrate 1
The defect layer 4 formed near the interface with the element is surrounded by the element isolation region 2 made of SiO ₂ .

Such a structure can be formed as follows. First, a normal silicon LSI is placed on a p-type silicon substrate.
The element isolation region 2 is formed by an element isolation method such as LOCOS or STI used in the above. Next, an n-type Si layer 3 is formed by performing ion implantation on a region isolated by the element isolation region 2. The dose at this time is set so that the n-type Si layer 3 does not reach a position deeper than the element isolation region in consideration of the position of a defect or dislocation (defect layer 4) to be generated later.
That is, the n-type Si layer 3 and the n-type Si layer 3 and the p-type Si layer
Control is performed so that the vicinity of the interface with the substrate 1 is surrounded by the element isolation region 2.

In the pn diode structure described above, ions of Si, B, P, etc. are implanted in the region of the n-type Si layer 3,
Next, annealing is performed to form a defect layer 4 serving as a light emission center near the pn junction. Annealing can be performed by rapid thermal annealing (RTA) or furnace annealing (FA).

After the formation of the defect layer 4, the electrodes 5 and 6 for passing a current through the pn diode are respectively connected to the n-type Si layer 3.
It is formed on the upper surface and the back surface of the Si substrate 1. The electrode 6 formed on the back surface of the Si substrate 1 may be formed in advance.

In the above embodiment, the defect layer 4 is formed near the pn junction, but the defect layer 4 may be formed on a high resistance layer formed between the p-type layer and the n-type layer. This high resistance layer is formed, for example, as follows. Using a high-resistance silicon substrate (several hundreds to 1,000 Ωcm or more), a first conductivity type impurity is ion-implanted into the substrate to form a first conductivity type layer (for example, a p-type layer). By implantation, a second conductivity type layer (for example, an n-type layer) is formed. At this time, the position at which each conductivity type layer is formed is controlled by adjusting the energy at the time of ion implantation so that a high resistance layer having a low impurity concentration is formed between the first conductivity type layer and the second conductivity type layer.

By passing a current through the pn diode formed as described above, electrons and holes are injected into the defect layer 4. Emission lines are observed in the near infrared region with defects and dislocations in the Si crystal serving as emission centers.

The main emission line observed is {311}
A light emitting line of 1.37 μm caused by a defect and a light emitting line of 1.42 μm, 1.48 μm, and 1.53 μm caused by dislocation. The intensity of any one of these light emitting lines is increased depending on manufacturing conditions. The half width is also narrow.

The defects and dislocations serving as the light emission center of these light emitting lines are generated by performing an annealing after ion implantation of Si, B, P, etc. into the Si crystal. Whether such a light emitting line appears depends on the ion implantation conditions of the ion species to be implanted and the dose, and
It is determined by the type of annealing method and the annealing conditions such as annealing temperature and annealing time. Therefore, if the implanted ion species and dose, the annealing method type, the annealing temperature, and the annealing time are set to appropriate conditions, only one of the four light emitting lines can be made very strong.

The emission intensity of the emission line having the highest emission intensity in the wavelength band of 1.2 to 1.6 μm has a relative intensity ratio of 10 to any of the other emission lines in the wavelength band.
It is preferable that it is above. More preferably, it is 50 or more.

Table 1 shows an example of the relationship between the ion implantation conditions and annealing conditions and the strongest emission wavelength. FIGS. 2A to 2D show emission spectra when defects and dislocations are generated under the conditions shown in Table 1.

[0032]

[Table 1] Assuming that the light emission intensity of the 1.37 μm wavelength light of (a) is 100, the light emission intensity of the light emission line at the light emission wavelength under each of the conditions (a) to (d) in Table 1 is 1. 42μ
The emission intensity of light having a wavelength of m is about 50, and 1.48 μm of (c).
The light emission intensity of the light having a wavelength of about 70 was about 70, and the light emission intensity of the light having a wavelength of 1.53 μm in FIG. Further, the emission intensity of InGaAsP measured under the same conditions is about 500 to 100.
It was 0. The emission intensities of the above wavelengths (a) to (d) have a structure in which the element isolation region 2 shown in FIG. 1 and the defect layer and the defect-free layer shown in FIG. 3 are alternately stacked. This is the result of measurement of the case where no light-emitting element is provided. If the element isolation region or the laminated structure is provided, a stronger light emission intensity of several times to several tens times or more can be obtained.

In the configuration of the present embodiment shown in FIG. 1, light emitted at this time is extracted in a direction perpendicular to the plane of the drawing. In the configuration shown in FIG. 1, the element isolation region 2 is formed so as to surround a defect or a dislocation serving as a light emission center, so that diffusion of electrons and holes in the lateral direction (the plane direction of the substrate) is prevented. As a result, the luminous efficiency increases.

Second Embodiment FIG. 3 is a sectional view showing the structure of a second embodiment of the present invention. In the present embodiment, a structure like a superlattice in which defect layers and defect-free layers are alternately stacked is formed by repeatedly performing ion implantation while changing the acceleration voltage for ion implantation when forming the defect layer 4. . This makes it possible to increase the defect / dislocation density, which is the emission center, and at the same time, increase the effect of confining carriers to increase the emission intensity.

Third Embodiment FIG. 4 shows the configuration of this embodiment. FIG. 4A is a plan view,
FIGS. 4B and 4C respectively show AA of FIG. 4A.
It is sectional drawing along the line and the BB line.

In this embodiment, an SOI substrate having a single crystal silicon layer formed on an insulating layer 8 (silicon oxide film) on a silicon wafer is used as a substrate.
The effect of confining carriers not only in the lateral direction (substrate plane direction) but also in the substrate depth direction is increased.

In this embodiment, the p-type Si layer 7 is formed on the single crystal silicon layer of the SOI substrate isolated by the element isolation region 2.
Is formed, and an n-type Si layer 3 is formed thereon. The element isolation region 2 includes the p-type Si layer 7 and the n-type Si layer 3
Is formed to reach the insulating layer 8 of the SOI substrate. With such a configuration, it is possible to increase the effect of confining carriers not only in the lateral direction (the plane direction of the substrate) but also in the depth direction of the substrate.

In this embodiment, both electrodes 5 and 6 have a structure in which the electrodes are taken from the front side of the substrate. The electrode 5 is provided on the n-type Si layer on the substrate surface as usual, and the one electrode 6 exposes the p-type Si layer 7 by partially etching away the region of the n-type Si layer 5 on the substrate surface, The electrode 6 is formed on the surface. Note that such a structure in which both electrodes are formed from the front side of the substrate can be applied to the first and second embodiments shown in FIGS. 1 and 3.

Fourth Embodiment FIG. 5 is a schematic plan view of the present embodiment. By making the shape of the upper electrode 5 into a donut shape, light is extracted in a direction perpendicular to the substrate.

As another electrode structure, a structure in which the electrode is made of a material transparent to the emission wavelength and light is taken out in the direction perpendicular to the substrate can be used.

[0041]

As is apparent from the above description, according to the present invention, the types of defects and dislocations to be generated can be changed by changing the ion implantation conditions and annealing conditions in the same manufacturing steps of ion implantation and annealing. Thus, light emitting elements having different emission wavelengths can be easily manufactured.

Further, by setting the ion implantation conditions and the annealing conditions, the emission intensity of only one of the plurality of wavelength lights can be increased, so that a single wavelength light can be extracted without providing a filter. The process can be simplified, and the manufacturing cost can be reduced.

Further, since defects and dislocations can be formed more reliably and more reliably than in the prior art, it is possible to reduce variations in the characteristics of each product.

Further, since a light emitting element in the near infrared region using Si can be realized, it is possible to manufacture a Si-OEIC in which an optical device, a memory, a logic circuit, and the like are mounted on one Si chip.

Further, the ion implantation and annealing in the present invention can use the process used for the existing silicon LSI as it is, so that a new special device can be introduced or the LSI can be used for producing the Si-OEIC.
The Si-OEIC can be manufactured simply and at low cost without having to worry about consistency with the process.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a light emitting device of the present invention.

FIG. 2 is a diagram showing an emission spectrum of the light emitting device of the present invention.

FIG. 3 is a schematic sectional view of a light emitting device of the present invention.

FIG. 4 is a schematic cross-sectional view illustrating a configuration of a light emitting device of the present invention.

FIG. 5 is a schematic plan view illustrating a configuration of a light emitting device of the present invention.

FIG. 6 is a schematic sectional view of a conventional light emitting device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type Si substrate 2 element isolation region 3 n-type Si layer 4 defect layer 5 electrode 6 electrode 7 p-type Si layer 8 insulating layer 9 SOI substrate 61 n-type silicon substrate 62 silicon-germanium mixed crystal layer 63 silicon layer 64 super lattice Layer 65 p-type silicon layer 66 electrode 67 electrode 68 filter

Claims (9)

[Claims] 1. A method according to claim 1, wherein the first conductive type silicon layer and the second conductive type silicon layer laminated thereon are formed near the interface.
11. A light-emitting element which emits light with a defect or dislocation as a light-emission center. 2. A {311} near an interface between a first conductivity type silicon layer and a second conductivity type silicon layer laminated thereon.
It has a structure in which a defect layer in which defects or dislocations are formed and a defect-free layer without defects and dislocations are alternately stacked, and emits light with a {311} defect or dislocation in the defect layer as an emission center. Light emitting element. 3. The light emission is in a wavelength band of 1.2 to 1.6 μm, and the light emission intensity of the light emission line having the highest light emission intensity in the wavelength band is higher than any of the other light emission lines in the wavelength band. 3. The light emitting device according to claim 1, wherein the relative intensity ratio is 10 or more. 4. The light emitting device according to claim 1, wherein an element isolation region is formed so as to surround at least a periphery of the defect layer. 5. An element formed using an SOI substrate having an insulating layer formed on a silicon wafer and a silicon single crystal layer formed on the insulating layer, and the silicon single crystal layer reaching the insulating layer. An isolation region is formed, and the first conductivity type silicon layer and the second conductivity type silicon layer laminated thereon are formed in a region isolated by the element isolation region. The light-emitting element according to any one of the preceding claims. 6. A second electrode, wherein a first electrode is formed on the second conductive type silicon layer, and the second conductive type silicon layer is partially removed and exposed such that the first conductive type silicon layer is exposed. The light emitting device according to claim 1, wherein a second electrode is formed on one silicon layer. 7. The method for manufacturing a light emitting device according to claim 1, wherein ions are implanted from a second silicon layer laminated on the first silicon layer, and thereafter, annealing is performed. A method for producing the light emitting element, wherein the defect or the dislocation is generated by performing the following. 8. The emission wavelength is controlled by selecting and adjusting an ion species and a dose amount in the ion implantation, a type of an annealing method in the annealing, an annealing temperature and an annealing time. A method for manufacturing the light-emitting element according to the above. 9. The method according to claim 8, wherein the ionic species is any of Si, B, and P, and the annealing method is any of rapid thermal annealing and furnace annealing.