JP2000357180A - Manufacture of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a printed wiring board which can make the loss of signal transmission as small as possible by efficiently vary the line width of a signal line. SOLUTION: A printed wiring board is manufactured by stacking signal layers, ground layers, and a power supply layers and whether or not all the formed ground layers overlap with a signal line formed in the signal layer as a design layer is detected; when they overlap, the line width of the signal Line is varied from a reference value so that necessary characteristic impedance is obtained in the relation with the ground layer closest to the signal line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board in which a plurality of signal layers, ground layers, and power supply layers are laminated and a high-frequency signal is passed. It is.

[0002]

2. Description of the Related Art Hitherto, a printed wiring board formed by laminating a plurality of signal layers and power supply layers has been used for high-density wiring of electronic equipment. In this printed wiring board, the printed wiring board is formed on the signal layer. A high-frequency signal is passed through the signal line. When a high-frequency signal is passed through a signal line, it is necessary to change the wiring width of the signal line according to the distance between the power layer and the signal layer of the signal line of the printed wiring board in order to efficiently transmit the signal. is there.

A conventional method for designing the wiring width is described in Japanese Patent Application Laid-Open No. 9-199863. This conventional technique includes a means for setting a reference width of a wiring pattern to a reference width of an outermost (inner) layer, a means for changing a reference width of a wiring pattern of another layer, and a method for setting a pattern corresponding to an inner layer side pattern. It consists of a means for narrowing and a means for widening the pattern corresponding to the inner layer clearance.

More specifically, as shown in FIG. 5, the pattern of the signal line 1 of the signal layer located at the outermost layer among a plurality of signal layers superimposed on the power supply layer 5 has a line width of the signal line. It is designed based on the width W0. The pattern width of the signal layers other than the outermost signal layer, in the illustrated example, the pattern width of the signal line 2 is narrowed according to the distance from the power supply layer 5, and the reference of the pattern width is W4.

The pattern width of each signal layer including the outermost signal layer is determined when there is a pattern of another signal layer between itself and the power supply layer 5 thereunder, that is, when there is an inner layer side pattern, The pattern is reduced according to the area of the pattern. For example, in signal line 1, since there is signal line 2 in region A2, the pattern width is reduced to W1. Further, when there is an inner layer clearance 4 below each signal layer, the pattern width of each signal layer is increased according to the area of the inner layer clearance 4. For example, in signal line 1, region A
4 and A6, the pattern widths are W2 and W3, respectively.
In the signal line 2, the pattern width in the region A9 is reduced from the reference W4 to W5.

[0006]

However, the prior art has the following problems to be improved. That is, the first problem is that the line width of the signal line formed in the signal layer is determined based on the presence or absence of the power supply layer. Is a problem that can be changed. The second problem is that the signal lines are arranged without considering the presence or absence of the ground layer in the lower layer, the line width is frequently changed, and the loss of signal transmission at the changed portion increases. It is.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has been made in consideration of the above problem. Therefore, the present invention is directed to a printed wiring board capable of efficiently changing a line width of a signal line and minimizing a signal transmission loss. It is intended to provide a manufacturing method.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a printed wiring board, wherein a plurality of signal layers, a plurality of ground layers, and a plurality of power supply layers are stacked to achieve the above-mentioned object. A method for manufacturing a printed wiring board comprising: detecting whether or not a signal line formed on a signal layer serving as a design layer overlaps with all formed ground layers; The line width of the line is changed from a reference value so as to obtain a required characteristic impedance in relation to a ground layer closest to the signal line. According to a second aspect of the present invention, there is provided a method for manufacturing a printed wiring board, wherein the position and shape of the signal line pattern and the ground layer are set based on component arrangement position information to be mounted on the printed wiring board according to the first aspect. After that, the presence or absence of the overlap between the signal line pattern and the ground layer is detected. The method for manufacturing a printed wiring board according to claim 3 of the present invention is configured such that, when the signal line according to claim 1 or 2 overlaps with the ground layer so as to intersect or contact with the ground layer, The method is characterized in that the signal line pattern is changed so as to bypass the overlapping portion, and the line width of the signal line is held at a reference value. According to a fourth aspect of the present invention, there is provided a method of manufacturing a printed wiring board, wherein a minimum value and a maximum value are set in a path length capable of forming a detour path of the signal line according to the third aspect. When it is not possible to set a detour route by using the maximum value, the detour route is set by using the maximum value. Further, in the method for manufacturing a printed wiring board according to claim 5 of the present invention, the signal line according to claim 1 or
When overlapping so as to intersect with the ground layer,
The signal line is divided at an intersection with the ground layer, and a line width of a portion of the signal line overlapping the ground layer is changed from a reference value. Further, in the method of manufacturing a printed wiring board according to claim 6 of the present invention, the signal line according to claim 1 or 2 overlaps with the ground layer so that the signal line overlaps with the ground layer. When a detour path for the overlapping portion of the line cannot be formed, the signal line is divided at an intersection with the ground layer,
The line width of a portion of the signal line overlapping the ground layer is changed from a reference value.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. First, regarding the laminated structure of the printed wiring board manufactured according to the present embodiment,
Referring to FIG. 3, the printed wiring board indicated by reference numeral 10 in FIG. 3 has an eight-layer structure, in which one layer is a signal layer A, two layers are a ground layer, and three layers are signal layers B, 4 The layer surface is a power layer, the fifth layer is a ground layer, the sixth layer is a signal layer C,
The seventh layer is a power supply layer, and the eighth layer is a signal layer D.

A manufacturing apparatus for suitably executing a method for manufacturing a printed wiring board according to an embodiment of the present invention will be described with reference to the block diagram of FIG. The manufacturing apparatus includes a data processing unit 100, a display unit 200, and an input unit 30 of a computer that operates under program control.
0.

The data processing unit 100 includes a priority ground layer calculation unit 101, a line width calculation unit 102, a ground layer calculation unit 103, a component arrangement unit 104, a storage unit 105, an operation command input unit 106, Wiring means 107
, A design rule check unit 108, a first wiring correction unit 109, and a second wiring correction unit 110.
Here, the reference width of the signal lines formed on the signal layers A to D is set to a value such that a predetermined characteristic impedance can be obtained when the signal lines do not overlap with the ground layer.

Next, referring to the flowchart of FIG.
A method of manufacturing a printed wiring board using a CAD for designing a printed wiring board will be described. First, step 1
Then, the component placement unit 104 calculates the component placement position on the printed wiring board, stores the component placement position data 1001 in the storage unit 105, and proceeds to the next step 2.

In step 2, the priority ground layer calculation means 101 sets a priority ground layer for the design layer. That is, the priority ground layer calculation unit 101
Calculates the priority order of the ground layers for each signal layer in ascending order of the layers, and stores the priority in the storage unit 105. In the printed wiring board 10 of FIG.
The priority of the ground layer on the layer surface is calculated as the first priority, and priority data 1002 in which the signal layer is the first layer and the ground layer has the first priority relative to the second layer is created and stored. It is stored in the means 105. Next, the three-level ground solid layer is calculated as the second priority and stored in the storage unit 105. Similarly, the priority order of the other ground solid layers is calculated for each signal layer surface of each layer surface, priority data 1002 is created and stored in the storage means 105, and the process proceeds to the next step 3.

In step 3, the line width calculating means 10
2 calculates the line width of the first signal layer A. The line width calculation means 102 calculates the line width of the signal line that obtains the required characteristic impedance for the combination of the ground layer of the second layer and the signal line of the first layer when the copper foil of the ground net exists on the second layer. Record. Further, in the case where the copper foil of the ground net does not exist on the second layer surface, the line width of the signal line for obtaining the required characteristic impedance is calculated and recorded in combination with the signal line of the first layer surface when the ground solid layer exists on the third layer surface. . Similarly, the line width of the signal line for obtaining the required characteristic impedance with respect to the combination of the signal line of the first layer with the ground layers of all other layers is calculated and recorded. further,
After calculating and recording the line width of the signal line that obtains the required characteristic impedance for the combination of the signal line and the ground layer of the other layer on the two-layer surface other than the one-layer surface, the three-layer surface, and all the other-layer surfaces, proceed to the next step Transition.

In step 4, the power / ground layer calculating means 103 calculates the copper foil shape data of the power / ground layer. That is, the ground layer calculation means 10
3 is the component arrangement position data 1001 from the storage unit 105
And read the power supply of the inner layer at the through hole position of the component terminal.
Calculate clearance land data at the ground layer position,
The power / ground layer shape data 1003 including the clearance land data is created and stored in the storage unit 105. Here, when a plurality of power / ground layer shapes intersect, they are combined into an integrated shape and stored, and the process proceeds to the next step 5.

In step 5, the operation command input means 106
Input the coordinate input instruction from the mouse or keyboard of the operator to the start point and the end point of the wiring of the signal layer;
Calculates the wiring route between the start point and the end point, creates the wiring pattern data 1004, records it in the storage means 105, and proceeds to the next step 6. Here, the processing of steps 4 and 5 may be interchanged.

In step 6, the design rule checking means 108 reads the wiring pattern data 1004 of the signal layer and the power / ground layer shape data 1003 stored in the storage means 105, reads the priority data 1002, and reads the wiring pattern. Then, the following calculation is performed to determine the relationship between the copper foil patterns of the power supply / ground layer shape data 1003 existing in the layer in which the priority order data 1002 is designated as the first priority order. In the same way, design rules are checked individually for all design data including negative figures and separate line figures as well as the same foil pattern. That is, the design rule check unit 108 determines, for each power supply / ground layer shape data 1003 existing on the layer surface whose priority order data 1002 is designated as the first priority order for the signal line pattern, for each of the power supply / ground layers. The calculation that classifies the relationship between the copper foil pattern and the signal line pattern into one of four types of “(1) intersect / (2) include / (3) contact / (4) no contact” is performed using the same foil pattern. , Negative patterns, and separate lines. If at least one pattern intersects with the signal line pattern, it is determined to be (1) comprehensively and the intersecting pattern is stored. If it is not determined to be (1), if there is at least one next contacting pattern, it is comprehensively determined to be (3) and the contacting pattern is stored. If both patterns (1) and (3) are not determined and are included in a certain pattern, the pattern is comprehensively determined as (2). If neither (1) nor (2) or (3), it is comprehensively determined as (4). After performing the above determination, the process proceeds to step 7.

In step 7, if the result of step 6 is comprehensively (2), the wiring pattern data 1004 is determined and the processing of step 9 is performed. If the result of step 6 is (1) or (3) overall, the first wiring correction means 109 sets a predetermined detour distance from the area where the power / ground layer pattern of the first priority exists. A detour to calculate the signal line position in the area within the value is calculated, the detour is first set to the minimum value, the detour is calculated, and if a possible detour is calculated, the process returns to step 5, If the calculation cannot be performed, the detour value is set to the maximum value and the detour is calculated again. Here, if the detour can be calculated, the procedure returns to step 5; otherwise, the procedure moves to step 8.

In step 8, the first wiring correction means 10
9 does not calculate the previous detour, and performs the following processing corresponding to (1) of the result of step 6. That is,
The second wiring correction means 110 calculates an intersection between the wiring and the boundary of the copper foil pattern of the power supply / ground layer, and divides the wiring to form an end point of the wiring at the intersection. And FIG.
After changing the line width defined in step 3 for each of the divided wirings as shown in FIG. In addition, here, the value of the allowable range is compared with the line length of the changed line width, and if the value is within the allowable range, the original line width is returned. At this time, if the width of the separate line or the diameter of the clearance land is within the allowable range, as shown in FIG. 4B, if the clearance land continuously exceeds the allowable range due to continuous contact, the line width becomes change.

In the printed wiring board 10 obtained as described above, a wiring result in which the impedance is constant can be obtained. The reason is that the line width is obtained from the existence of the ground layer other than the layer where the wiring exists. Also, CA
Since the wiring line width changes when wiring is added on D, it is possible to efficiently design a high-density printed wiring board with high density while complying with the DRC standard even in the case of a high-density printed wiring board.

Next, another embodiment of the present invention will be described. With reference to the flowchart of FIG. 2, a method of manufacturing a printed wiring board using a CAD for designing a printed wiring board will be described. The processing from step 1 to step 3 is the same as that of the embodiment of the invention. In step 4, the power / ground layer calculating means 103 calculates the copper foil shape data of the power / ground layer. That is, the ground layer calculation unit 103 stores the component arrangement position data 1 from the storage unit 105.
001 is read out, the clearance land data is calculated at the power supply / ground layer position of the inner layer at the through hole position of the component terminal, the power supply / ground layer shape data 1003 including the clearance land data is created, and stored in the storage means 105. Here, when a plurality of power / ground layer shapes intersect, they are combined into an integrated shape and stored. At this time, the shapes are synthesized even when there are overlapping figures such as clearance lands, separate lines, and negative figures.

The processing from step 5 to step 6 is the same as that of the embodiment of the invention. In step 7, when the result of step 6 is (2), the wiring pattern data 1004 is determined, and the process returns to step 5; Is the result of (1) or (3), the first wiring correction means 109 sets the signal in the area within a preset detour distance value from the area where the power supply / ground layer pattern of the first priority exists. Calculate a detour to calculate the line position, first set the detour distance value to the lowest value, calculate a detour, and return to step 5 if a possible detour is calculated, otherwise detour. Set the value to the maximum value and calculate the detour again. When searching for a detour, if it is within the allowable value, it is also allowed to create a wiring that crosses an area where the line width changes. Here, if the detour can be calculated, the process returns to step 5; otherwise, the process proceeds to step 8. In the case of the above (3), since the detour can be calculated, the process does not proceed to Step 8. The processing in step 8 is the same as in the embodiment of the invention.

In this embodiment, the same operation and effect as in the above-described embodiment can be obtained.

[0024]

Since the present invention is configured as described above, it is possible to obtain a wiring result in which the impedance is constant, whereby a high-frequency signal can be passed efficiently, and when a wiring is added on a CAD. Since the wiring line width changes, even in the case of a high-density printed wiring board, it is possible to efficiently design at a high density while observing the DRC standard.
Further, before changing the line width of the signal line, a search for a detour of this signal line is performed, and if a detour is possible, a detour path is set and the line width is not changed, so that the line width is not changed. Can be reduced.

[Brief description of the drawings]

FIG. 1 shows one embodiment of the present invention, and is a block diagram showing a manufacturing apparatus suitably used for carrying out a method of the present invention.

FIG. 2 is a processing flowchart showing an embodiment of the present invention.

FIG. 3 is a schematic diagram showing an example of a laminated state of a printed wiring board to which an embodiment of the present invention is applied.

FIG. 4 shows one embodiment of the present invention, and is a schematic view showing a change in the line width of a signal line.

FIG. 5 is a schematic view showing a conventional method for manufacturing a printed wiring board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Signal line 2 Signal line 4 Inner layer clearance part 5 Power supply layer 10 Printed wiring board 100 Data processing part 101 Priority ground layer calculation means 102 Line width calculation means 103 Ground layer calculation means 104 Component arrangement means 105 Storage means 106 Operation command input means 107 Wiring unit 108 Design rule checking unit 109 First wiring correcting unit 110 Second wiring correcting unit 200 Display unit 300 Input unit W0 Pattern width (reference width) W1 to W5 Pattern width A1 to A9 Area

Claims (6)

[Claims] 1. A method for manufacturing a printed wiring board, comprising a plurality of signal layers, ground layers, and power supply layers, each comprising: a signal line formed on a signal layer serving as a design layer;
The presence / absence of overlap with all the formed ground layers is detected, and when there is overlap, a required characteristic impedance can be obtained by setting the line width of the signal line to the ground layer closest to the signal line. A method of manufacturing a printed wiring board, wherein the method is changed from a reference value. 2. After setting the position and shape of the signal line pattern and the ground layer on the basis of information on the position of components to be mounted on the printed wiring board, detecting whether or not the signal line pattern overlaps the ground layer. The method for manufacturing a printed wiring board according to claim 1, wherein: 3. When the signal line overlaps so as to intersect or contact with the ground layer, the signal line pattern is changed so as to bypass the overlapping portion, and the signal line line is changed. The method for manufacturing a printed wiring board according to claim 1, wherein the width is maintained at a reference value. 4. A minimum value and a maximum value are set for a path length that can form a detour path of the signal line, and when a detour path cannot be set based on the minimum value, a detour path based on a maximum value is set. The method for manufacturing a printed wiring board according to claim 3, wherein the setting is performed. 5. When the signal line overlaps with the ground layer so as to intersect with the ground layer, the signal line is divided at an intersection with the ground layer, and a portion of the signal line overlapping the ground layer is formed. The method according to claim 1, wherein the line width is changed from a reference value. 6. In a case where the signal lines overlap so as to intersect with the ground layer, and when a detour path for the overlapping portion of the signal lines cannot be formed, the signal lines are connected to each other. 3. The method for manufacturing a printed wiring board according to claim 1, wherein the line is divided at an intersection with the ground layer, and a line width of a portion of the signal line overlapping the ground layer is changed from a reference value. .