JP2000357125A - Method and device for buffer memory control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and device for control which convert the memory constitution of a buffer of a data storage system by access patterns of respective data so that the use efficiency of the buffer is optimized. SOLUTION: When a sequential access pattern is detected at a data access request from a host computer 109, the number of segments of the buffer 106 is decreased to alter the buffer memory constitution so that the segment size of the buffer becomes large, thereby achieving optimum sequential access performance. When a nonsequential access pattern is detected, on the other hand, the number of segments of the buffer 106 is increased and the buffer memory constitution is altered so that the data reuse efficiency in the buffer becomes large, thereby increasing the processing efficiency of data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method and a control device for a buffer memory, and more particularly to a control of a buffer memory applied to a change in a data storage access pattern.

[0002]

2. Description of the Related Art An example of changing a control method according to a change in a data storage access pattern is disclosed in JP-A-8-21.
There is known a "method for operating a buffer memory and related devices" disclosed in Japanese Patent Publication No. 2054. This is to monitor the data access request, switch to the buffer overwrite prefetch storage rule if it is detected as a sequential access pattern, and switch to the circular overwrite mode. The mode is switched to the non-sequential or block overwrite mode accordingly. This maximizes the reuse hit of the data block in the buffer.

[0003] Therefore, the "method for operating a buffer memory and related control device" disclosed in Japanese Patent Application Laid-Open No. H8-212054 discloses a method for responding to a data access request within a fixed independent segment. Switching the reading method of the buffer memory,
The configuration of the buffer memory has a single segment configuration composed of a single segment or a multi-segment configuration in which a buffer is divided into a plurality of segments.

[0004]

In a buffer memory configuration of a data storage device, in the case of a single segment configuration, a large amount of data can be stored because a buffer segment size is large for a sequential access pattern. Although very convenient, a non-sequential access pattern has a problem that a buffer mishit is likely to occur at the time of data output, and the data processing efficiency is low.

On the other hand, in the case of a multi-segment configuration,
For non-sequential access patterns, data processing efficiency is high because data in the buffer can be reused, but for sequential access patterns, the buffer segment size is small, so the buffer is likely to become full and overhead increases. There is a problem that the CPU occupancy is deteriorated by the increase. This is remarkable especially when a RAM having a small buffer capacity is used.

[0006] In the "method for operating a buffer memory and related devices" disclosed in Japanese Patent Application Laid-Open No. H8-212054, the buffer memory is configured as a single-segment configuration or a multi-segment configuration. Therefore, the “method for operating a buffer memory and related devices” disclosed in Japanese Patent Application Laid-Open No. H08-212054 also has the above-described problem of the single-segment configuration or the multi-segment configuration.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has an object to automatically adapt a buffer memory configuration according to a change in a requested data access pattern.
In the case of the sequential access pattern, the segment size of the buffer can be increased to prevent the occupancy of the CPU from deteriorating. In the case of the non-sequential access pattern, the efficiency of data reuse can be increased, and It is an object of the present invention to provide a buffer memory control device that can increase efficiency.

[0008]

According to one aspect of the present invention, there is provided a buffer memory control device for determining whether an access pattern of request data is a sequential access pattern or a non-sequential access pattern. It has a pattern determining unit and a buffer memory configuration converting unit that converts the number of segments in the buffer memory according to the access pattern of the requested data.

According to a second aspect of the present invention, in the buffer memory control device according to the first aspect, the access pattern determining unit counts the number of data blocks continuously input to the buffer memory. Unit, and a comparison unit for comparing the number of data blocks counted by the counting unit with an arbitrarily set threshold value. If it is determined that the access pattern is equal to or smaller than the threshold value, it is determined that the access pattern is a non-sequential access pattern.

According to a third aspect of the present invention, in the buffer memory controller according to the first aspect, when the access pattern of the request data is the sequential access pattern, Convert the buffer memory configuration to reduce the number of segments and increase the segment size of the buffer.If the requested data access pattern is a non-sequential access pattern, increase the number of segments in the buffer and reuse the data in the buffer. The buffer memory configuration is converted to increase the efficiency.

According to a fourth aspect of the present invention, there is provided a buffer memory control method, comprising: an access pattern determining step of determining whether a request data access pattern is a sequential access pattern or a non-sequential access pattern; And a buffer memory configuration conversion step of converting the number of segments in the buffer memory.

According to a fifth aspect of the present invention, in the buffer memory control method according to the fourth aspect, the access pattern determining step counts the number of data blocks continuously input to the buffer memory. And a comparing step of comparing the number of data blocks counted by the counting section with an arbitrarily set threshold value. If the threshold value is exceeded, the access pattern is determined to be a sequential access pattern. Judge,
If it is equal to or less than the threshold value, it is determined that the access pattern is a non-sequential access pattern.

According to a sixth aspect of the present invention, in the buffer memory control method according to the fourth aspect, the buffer memory configuration conversion step includes the steps of: Converting the buffer memory configuration to reduce the number of buffer segments and increase the buffer segment size; and, if the requested data access pattern is a nonsequential access pattern, increasing the number of buffer segments and And converting the buffer memory configuration so as to increase the data reuse efficiency.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) An embodiment of a buffer memory control method and a control device according to the present invention will be described below with reference to FIGS. 1, 2, 3 and 4. FIG. FIG.
1 is a block diagram of a data storage device incorporating a buffer memory control device according to Embodiment 1 of the present invention. As shown in the figure, a data storage device incorporating the buffer memory control device of the first embodiment includes a storage medium 101.
Data reading unit 10 for reading data from
2, a signal processing unit 103 that processes a read signal read by the data reading unit 102, an error correction unit 104 that performs error correction, and a buffer memory control unit that controls the operation of a buffer memory as a buffer memory control device. 105, a buffer memory 106 for temporarily storing data by cyclically overwriting in the segment, and an interface 1 for inputting and outputting data
07, a microprocessor 108 for controlling the entire data storage device, and a host computer 109 for issuing a data access request to the storage device.

Here, the buffer memory control device 105
Is an access pattern determining unit 110 for determining whether the access pattern of the request data is a sequential access pattern or a non-sequential access pattern, and a buffer memory configuration conversion for converting the number of segments of the buffer memory according to the access pattern of the request data. The access pattern discriminating unit further includes a counting unit 111 for counting the number of data blocks continuously input to the buffer memory, and the number of data blocks counted by the counting unit 111. And a comparison unit 112 for comparing the threshold value.

Next, the operation will be described. As shown in FIG. 1, the request data from the host computer 109 is:
The data in the storage medium 101 is read by the data reading unit 102 via the interface 107 and the microprocessor 108. The data is transmitted to the signal processing unit 10
After the signal processing in step 3, the error is corrected by the error correction unit 104, and is temporarily stored in the buffer memory 106 controlled by the buffer memory control unit 105 by performing cyclic overwriting within the segment. After that, the data stored in the buffer memory 106 is transferred to the host computer 109 by the interface 107 controlled by the microprocessor 108.

FIG. 2 is an explanatory diagram for explaining the conversion of the configuration of the buffer memory. As shown in FIG. 2, the buffer circuit control unit 105 controls the buffer memory 106 when the access pattern of the request data from the host computer 109 is a sequential access pattern. When the requested data access pattern is a non-sequential access pattern, the number of segments in the buffer is increased, and the multi-segment is set so as to increase the data reuse efficiency in the buffer. Convert to configuration 202.

Here, the access pattern of the request data is determined, for example, by counting the number of data blocks continuously entering the buffer memory as shown in FIG.
By comparing the number of data blocks counted by 1 with the arbitrarily set threshold value by the comparing unit 112 with the number of data blocks counted by the counting unit 111, if the threshold value is exceeded, the access pattern is sequentially changed. It is determined that there is a pattern, and if it is equal to or smaller than the threshold value, it is determined that the pattern is a non-sequential access pattern. Here, the threshold value can be freely set according to various conditions such as the capacity of the buffer memory to be converted or the number of segments.

The multi-segment configuration 2 shown in FIG.
FIG. 3 shows an example of a case where the buffer memory configuration is converted between 01 and the single segment configuration 202.
This will be described with reference to the flowchart of FIG. FIG. 3 shows a multi-segment configuration 20 according to Embodiment 1 of the present invention.
3 is a flowchart illustrating a control method of the buffer memory configured by the first embodiment. First, after the system power is turned on, the buffer memory reads in a multi-segment configuration 201 in response to an access request from the host computer 109. As shown in FIG. 3, in response to the data access request (S1), the A segment 20 being read is read.
3, if there is no buffer hit (S2), switch to the next segment, B segment 204 (S3), and continue to read ahead until the buffer becomes full (S3).
4).

Although the description has been given of the case where a data access request is issued from the host computer 109 while reading the A segment 203, the case where a data access request is issued from the host computer 109 while reading the B segment 204 is described. However, the same operation is possible.

On the other hand, if a buffer hit occurs in the A segment 203 being read in response to the data access request (S1) (S2), the number of data blocks in the continuous access request from the host computer 109 is arbitrarily determined. Comparison with the set threshold is performed (S5), and the number of data blocks is equal to or smaller than the threshold (non-sequential access pattern)
In the case of, the data in the A segment 203 being read is transferred, and the prefetch is continued until the buffer becomes full (S
4). If the number of data blocks is equal to or larger than the threshold (sequential access pattern), the configuration of the buffer memory is converted from a multi-segment configuration having a small buffer segment size to a single segment configuration 202 having a large buffer segment size, Continue reading ahead (S6).

FIG. 4 is a flowchart showing a control method of the buffer memory constituted by the single-segment structure 202 according to the first embodiment of the present invention. When the next access request comes to the buffer memory whose configuration has been converted (S7), the number of consecutive data blocks of the access request is compared with an arbitrarily set threshold value (S8), and the number of data blocks is reduced. If it is equal to or greater than the threshold (sequential access pattern), the data in the single segment 205 is transferred, and the prefetch is continued until the buffer becomes full (S9). When the number of data blocks is equal to or smaller than the threshold value (non-sequential access pattern), the configuration of the buffer memory is converted from the single segment configuration 202 having low data processing efficiency to the multi-segment 201 configuration having high data processing efficiency. Continue reading ahead (S10).

Thus, the buffer memory configuration can be automatically adapted to the buffer memory configuration according to the change in the requested data access pattern. In the case of the sequential access pattern, the number of segments in the buffer memory can be reduced, By increasing the segment size, it is possible to prevent the occupancy of the CPU from being deteriorated. In the case of a non-sequential access pattern, the number of segments in the buffer memory is increased to increase the data reuse efficiency, thereby improving the data processing efficiency.

In the case of a sequential access pattern,
In the single-segment configuration 202, the case where the number of segments is converted to a multi-segment configuration having two segments in the case of a non-sequential access pattern has been described. When the buffer memory configuration is converted and the requested data access pattern is a non-sequential access pattern, the buffer memory configuration is converted so as to increase the number of buffer segments, thereby adjusting the buffer segment size. However, the same effect can be obtained.

[0025]

As described above, according to the buffer memory control method and control apparatus of the present invention, an access pattern determining unit for determining an access pattern of request data and a buffer memory configuration converting unit for converting the configuration of a buffer memory In the case of a sequential access pattern, by reducing the number of segments of the buffer memory and increasing the segment size of the buffer, it is possible to prevent the CPU occupancy from deteriorating. In the case of a non-sequential access pattern,
By increasing the number of segments in the buffer memory and increasing the data reuse efficiency, it is possible to increase the data processing efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data storage device incorporating a buffer memory control device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining conversion of a configuration of a buffer memory according to the first embodiment of the present invention;

FIG. 3 is a flowchart illustrating a control method of a buffer memory configured with a multi-segment configuration according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a control method of a buffer memory configured with a single segment configuration according to the first embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Recording medium 102 Data reading part 103 Signal processing part 104 Error correction part 105 Buffer memory control part Buffer memory 106 Buffer memory 107 Interface 108 Microprocessor 109 Host computer 110 Access pattern discrimination part 111 Count part 112 Comparison part 113 Buffer memory configuration conversion part 201 Multi-segment configuration 202 Single-segment configuration 203 A-segment 204 B-segment 205 Single-segment

Claims (6)

[Claims] 1. A buffer memory control device for controlling an operation of a buffer memory, comprising: an access pattern determining unit for determining whether a request data access pattern is a sequential access pattern or a non-sequential access pattern; A buffer memory control unit for converting the number of segments in the buffer memory according to a pattern. 2. The buffer memory control device according to claim 1, wherein the access pattern determining unit counts the number of data blocks continuously input to the buffer memory, and the data counted by the counting unit. A comparison unit that compares the number of blocks with an arbitrarily set threshold value; if the threshold value is exceeded, the access pattern is sequentially determined; Is a non-sequential access pattern. 3. The buffer memory control device according to claim 1, wherein the configuration conversion unit reduces the number of buffer segments and increases the buffer segment size when the access pattern of the requested data is a sequential access pattern. If the requested data access pattern is a non-sequential access pattern, the buffer memory configuration is changed so that the number of segments in the buffer is increased and the data reuse efficiency in the buffer is increased. A buffer memory control device. 4. A buffer memory control method for controlling an operation of a buffer memory, comprising: an access pattern determining step of determining whether a request data access pattern is a sequential access pattern or a non-sequential access pattern; A buffer memory configuration conversion step of converting the number of segments in the buffer memory according to a pattern. 5. The buffer memory control method according to claim 4, wherein the step of determining an access pattern includes a step of counting the number of data blocks continuously input to the buffer memory, and a step of counting data counted by the counting unit. A comparing step of comparing the number of blocks with an arbitrarily set threshold value, and when the threshold value is exceeded, the access patterns are sequentially determined. Is a non-sequential access pattern. 6. The buffer memory control method according to claim 4, wherein the buffer memory configuration conversion step comprises: when an access pattern of the requested data is a sequential access pattern,
Reducing the number of buffer segments and converting the buffer memory configuration so that the buffer segment size increases; and increasing the number of buffer segments if the requested data access pattern is a non-sequential access pattern.
Converting the buffer memory configuration so as to increase the data reuse efficiency in the buffer.