JP2000357089A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of a CPU by expanding the bus width of instruction read while maintaining compatibility with an existent CPU. SOLUTION: Concerning the existent CPU, the width of an internal data bus is made greater than the basic unit of an instruction, an instruction register 200 is provided for holding the plural units of read instructions and a means for monitoring the quantity of instructions existent in the instruction register is provided. According to the basic unit time (called state) of execution, the existent instruction is divided into the state for only performing the read control of the instruction (first operation) and the state including the calculation of an effective address or control of operation processing of data (second operation) and corresponding to the condition of the read instruction, the state for controlling only the read of the instruction can be omitted (skipped). Thus, the quantity of simultaneously readable instructions can be made greater than the existent CPU by the great bus width and the throughput is improved by the said skip as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer, a microcontroller, and a central processing unit (CPU).
The present invention relates to a technology which is effective when applied to, for example, a microcomputer incorporated in a device integrated into a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A microcomputer comprising a semiconductor integrated circuit has been designed to have an expanded address space, an enlarged instruction set, and a higher speed. Microcomputer CP
Since the function of U is defined by software, it is desirable that the software resources of the existing microcomputer can be effectively used even in a microcomputer which has an expanded address space, an expanded instruction set, and a higher speed. .

[0003] For this reason, as an example of realizing expansion of the address space and expansion of the instruction set while maintaining compatibility at the object level, for example, Japanese Patent Application Laid-Open No. 6-51981, June 1993, Hitachi, Ltd. Issued "H8 / 300
H Series Programming Manual ”. Among them, it is shown that adopting a so-called load store type architecture is effective in expanding an instruction set. Such a load store type architecture is a so-called RISC (Reduced Inst.
With the spread of a "function set computer" type microcomputer, it is increasingly used.

Further, while maintaining compatibility with the above-described CPU which executes basic instructions in two states, the speed is increased so that the basic instructions are executed in one state.
Japanese Patent Application Laid-Open No. 8-263290, March 1995, "H8S / 2600 Series H8" issued by Hitachi, Ltd.
S / 2000 Series Programming Manual ”. In this CPU, the basic unit of an instruction is 16 bits (word) and the data bus width is 16 bits.
Is a bit. That is, one word of instruction can be read by one bus access. In particular, "H8S / 2600 Series H8" issued by Hitachi, Ltd.
S / 2000 Series Programming Manual ”pp
268 to 277 describe the bus state at the time of instruction execution.

[0005] In the above CPU, an inter-register operation instruction having an instruction code length of one word reads an instruction of one word (the next instruction is read because prefetch is performed).
And PC are incremented (+2), and C
The contents of the general-purpose register are read inside the PU, an operation is performed, and the result is written to the general-purpose register.

On the other hand, in an operation instruction for 16-bit immediate data and a general-purpose register, the instruction code length is 2 words because 16-bit immediate data is included in the instruction. The instruction is read twice (the second word of the own instruction and the next instruction) and the PC is incremented twice. This process requires two states. On the other hand, CPU
Internally, 16-bit immediate data and the contents of the general-purpose register are read, an operation is performed, and the result is written to the general-purpose register. The internal operation can be executed in one state as in the case of the inter-register operation instruction. That is,
In one state, only instruction reading and PC increment are performed, and in another state, instruction reading, PC increment and internal arithmetic processing are performed.

Execution of an instruction having an instruction code length of a plurality of words also includes a state in which only instruction read and PC increment are performed, and a state in which instruction read, PC increment, internal arithmetic processing, and data access are performed. .

[0008] By the above-described technique, C per unit time
The processing capability of the PU or the microcomputer is improved. As a result, the control processing of the microcomputer application system can be speeded up, and the speed of the device controlled by the microcomputer can be increased, the function can be increased, the accuracy can be improved, or a conventional semiconductor integrated circuit (microcomputer) can be used. It is possible to reduce the size by integrating the components. In particular, by shortening the response time to the interrupt, it is possible to improve the temporal accuracy in controlling various devices, that is, the so-called real-time property.

[0009]

SUMMARY OF THE INVENTION The present inventor has made it possible to maintain compatibility so that software assets can be effectively used, minimize an increase in logical and physical scale, and increase power consumption. We also studied to minimize the number of data processing units and to enable data processing devices such as microcomputers with built-in devices to process at even higher speeds.

In order to speed up the operation of the CPU, it is necessary to reduce the number of states required for executing one instruction and to increase the operating speed or operating frequency of a single-chip microcomputer such as a semiconductor integrated circuit. ,
Can be roughly divided into The latter operation speed or operation frequency can be realized by miniaturization of a semiconductor integrated circuit, high-speed operation of a transistor, or the like. However, the operating speed or the operating frequency inevitably increases the current consumption. Therefore, in order to minimize the increase in current consumption, it is better to reduce the number of states required for executing each instruction.

It is to be noted that a high-speed, high-performance, and compact device is required for a CPU or a microcomputer having a relatively small address space and a relatively small instruction set. If there is a CPU with a small size, it is desirable to increase the speed for both.

By maintaining compatibility, cross software tools such as an assembler, a C compiler, and a simulator / debugger can be commonly used. That is, since these existing development environments can be used, the development environments can be quickly prepared.

An ordinary microcomputer operates by reading an instruction, so that it is necessary to read the instruction by itself. As described above, data access is also performed, but in order to access data, it is necessary to read an instruction designating this. Also, some instructions do not perform data access. Therefore, in the bus cycle, instruction reading is more common than data access. For example, the instruction read may be 80% and the data access may be 20%.

In order to read an instruction at a high speed, the data bus width may be made larger than the unit word length of the instruction. For example, when the unit word of the instruction is 16 bits, it may be expanded to 32 bits. Instruction reading for two words can be performed by one bus access.

However, even if the reading of instructions is simply performed at high speed, it is meaningless unless instructions corresponding to the read are executed (consumed).

As a microcomputer adopting a 16-bit fixed-length instruction set and a 32-bit data bus,
In the case of configuring a five-stage pipeline, instruction fetch requires 2
Since an instruction can be executed in one bus cycle, an instruction fetch stage can be opened every other time. Memory access can be performed to the empty stage.

However, the present inventor has clarified that the method of increasing the number of bits per instruction read to increase the speed has the following problems.

When the pipeline is deepened, when the flow of the program changes, such as in a branch instruction or interrupt exception handling,
The pipeline after that must be eliminated and a new pipeline refilled. In a microcomputer for controlling equipment, since there are relatively many branch instructions and many interrupts, the number of pipeline stages becomes large, which is not preferable because the execution time of branch instructions and interrupt exception processing cannot be improved.

Although the 32-bit data bus allows four bytes starting from a multiple of 4 to be read or written at one time, compatibility with existing CPUs that read instructions in 16-bit units is maintained. For example, a 16-bit fixed-length instruction cannot be adopted, and a one-word-length instruction and a three-word-length instruction are mixed. In other words, alignment cannot be performed in units of a 32-bit data bus. For example, for an instruction with a 2-word length, it is necessary to determine whether to execute one instruction read or two instruction reads depending on whether the own instruction is at a multiple address of 4 or not. It is considered not to be. If the instruction is read twice, the execution time may be equivalent to that of the existing CPU. Further, determining the address of its own instruction or performing control for performing both one and two instruction reads tends to increase the logical scale.

On the other hand, a so-called microprocessor is described in “Nikkei Electronics”, pp. 68-80, published in January 1995 by Nikkei BP Co., Ltd., “turning into 1998, simplifying hardware to VLIW”, and the like. As described above, the speed is increased as in superscalar and VLIW. In each case, the number of processes that can be executed simultaneously is increased (for example, four parallel processes) to improve the overall processing performance. However, in the above technique, since a plurality of instructions are executed in parallel, the CP of the control circuit
Having a plurality of sets of U resources causes an increase in physical and logical scale.

Further, in a microcomputer (or microcontroller) embedded in a device, the contents of processing are changed while referring to the state of various devices.
Data access is performed to refer to the state of the device, and a branch instruction is executed to change the content of processing.
Therefore, the number of times that a local program is repeatedly executed is less than that of a microprocessor. Further, depending on the control target, there may be a case where there is a restriction on an instruction execution order or a case where there is a restriction on a local instruction execution time. Just because there is no inconsistency in software does not necessarily mean that the order of the instructions can be changed. Furthermore, depending on the system to be controlled, it may be necessary to reduce power consumption.

As described above, since a large number of branch processes are performed, even if a plurality of instructions can be processed in parallel using a technique such as superscalar, there is a branch instruction and the result of the processing must be abandoned. Also occurs. The conditional branch instruction is used until the branch condition referenced by the conditional branch instruction is determined.
Since the branch cannot be determined, the instruction for generating the branch condition referred to by the conditional branch instruction and the conditional branch instruction cannot be executed at the same time, and the subsequent processing cannot be executed. Each time a conditional branch instruction is present, it becomes impossible to execute the instructions in parallel. If branch prediction or speculative execution is performed, the possibility of performing an operation different from the operation to be actually processed cannot be ignored. In the case of device control, a branch destination is often determined from a number of branch destinations by combining conditional branch instructions (constructing a tree shape). It is considered that there are often conditional branches. As a result, the branch prediction tends to have a very low hit ratio. The average processing time may be improved by branch prediction and speculative execution,
It is not expected that the speed of individual local processing can be increased.

That is, even if a plurality of instructions can be executed in parallel, it is likely to be wasted. Logic for parallel execution is wasted, and logical and physical resources cannot be used effectively. In addition, useless logic and useless operation undesirably increase power consumption.

As a result, it is difficult to effectively use software resources for a microcomputer for controlling embedded devices even if parallel processing such as super scalar or VLIW is performed. Is also difficult. At least, it is difficult to increase the speed for the logical and physical scale, and the power consumption increases.

It should be noted that, in the repetitive processing of the same operation and the equipment control such as the motor control, the tendency of the processing performance differs for each CPU or microcomputer.
February, CQ Publishing Co., Ltd. “Interface” pp
134 to 145, "Thorough study of performance of embedded CPU". From this point of view, it is necessary to maintain the compatibility of existing CPUs and microcomputers suitable for embedded control of equipment at appropriate cost, inherit the existing architecture, appropriately increase the cost, and increase the speed. Have been clarified by the present inventors.

An object of the present invention is to increase the speed of a data processing device such as a microcomputer suitable for controlling equipment.

It is another object of the present invention to maintain compatibility with existing CPUs, to enable the use of existing software, and to minimize the increase in logical size while reducing manufacturing costs. An object of the present invention is to improve the processing performance of a CPU by minimizing the increase.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0029]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, an existing data processing device such as C
For the PU, the internal data bus width is made at least larger than the basic unit (eg, word) of the instruction, and the PU has an instruction register capable of holding a plurality of read instructions. Is provided. According to a basic unit time of execution (referred to as a state), an (existing) instruction is subjected to only instruction read control (including increment control of a program counter) (a first operation), an effective address calculation or The state is divided into a state (second operation) including control of data arithmetic processing, and a state in which only read of an instruction is controlled can be omitted according to the state of an already read instruction. In other words, according to the instruction of the monitoring means according to the amount of the instruction already read in the instruction register, the state in which only the instruction is read is omitted (skipped).

The amount of instruction read at the time of execution of each instruction is increased or decreased with respect to the instruction length of its own instruction.
This is controlled according to the number of instructions that have been read or are being read.

According to the above, by making the internal data bus width larger than the basic unit (word) of an instruction, the number of instructions to be read at one time can be made larger than that of an existing CPU.

In the case of the basic execution state, the existing CPU
Similarly to the above, when the instruction is read a number of times corresponding to the own instruction code length and the state is not omitted (skipped), the amount of the instruction code of the executed instruction is determined by the amount of the instruction code of the executed own instruction. By increasing the amount, the read instruction code can be accumulated.

On the other hand, by omitting (skipping) and not reading the instruction, the amount of the instruction code of the executed own instruction is made equal to the amount of the read instruction, and the amount of the read instruction code is reduced. It is possible to reduce the amount of the read instruction code by reducing the amount of the read instruction from the amount of the instruction code of the maintained or executed own instruction.

Thus, while keeping the amount of read instructions within a predetermined range (while balancing the amount of instruction read and the amount of instruction execution), the speed of instruction read is increased, and the overall Instruction execution time can be reduced.

Further, by automatically changing the states to be omitted (skipped), it is possible to cope with a change in the instruction arrangement.

In the instruction register, together with the instruction code,
Information about bit 1 on the address (IAB) of the instruction code may be stored, and the instruction decoder may determine it at the same time. Such a value of bit 1 indicates whether the address of a basic unit such as a word is a multiple of 4 or an even number that is not a multiple of 4. This makes control easier,
An increase in the logical scale of the instruction decoder can be minimized.

Instructions are read in 32-bit units, except for branch instructions and the start address of interrupt exception handling, and the program counter is incremented by +4. When the start address of the branch instruction or the interrupt exception handling is a multiple of 4, similarly, the instruction is read in 32-bit units, and the increment of the program counter is +4.
And Start address of branch instruction or interrupt exception handling is 4
If the address is not a multiple address, the first instruction is read in 16-bit units, and the increment of the program counter is +2. To configure the incrementer to automatically control the increment of +2 or +4 (+ 2 / + 4) of the program counter, for example, when bit 0 is a byte address, bit 1 of the incrementer
To the value obtained by the logical sum of its input and 1.
Carry to bit 1 may be provided.

As described above, except for the read of the start address of the branch instruction and the interrupt exception processing, the instruction is read in units of 32 bits, and the increment of the program counter is controlled by automatically performing + 2 / + 4. And the increase in the logical scale can be suppressed.

The contents of the program counter are stored in the write data buffer, and the write data buffer is stored in FIFO (First-In First-Out).
It is preferable that the circuit has a structure and has a circuit for setting the bit 1 like the incrementer of the program counter. As a result, the discrepancy between the address of the actually read instruction and the contents held in the program counter increases, and even if the instruction is not uniquely determined, the value of the program counter to be saved from the write data buffer at the time of a subroutine branch instruction is determined. Can be easily obtained. In addition, control can be facilitated and an increase in logical scale can be suppressed.

Even when the calculation of the effective address and the data transfer process operate over a plurality of states, the control itself is one.
The actual operation is performed in a plurality of states (for example, the address calculation is performed in the first state, and the read data is stored in the next state) by providing a delay to the control signal.

In the case of a branch instruction or interrupt exception handling, etc., when the prefetch of at least one word is completed, the decoding of the first instruction at the branch destination is started and executed, so that the processing by the branch instruction and interrupt exception handling is performed. Time loss can be minimized, and so-called responsiveness and thus real-time performance can be improved.

An operation for delaying a control signal (for example, storage of read data) by having an independent internal bus or the like can be performed simultaneously even when the next control operation (program counter / increment) overlaps. And the execution means.

An instruction that can be processed in the basic unit time (an instruction having no state that can be omitted) is an arithmetic logic unit (AL
A plurality of calculation means such as U) are provided so as to be able to operate while having an overlapping time. The execution means is configured to have an independent internal bus so that the operation means can operate simultaneously even if the operation of one of the operation means and the operation for reading the instruction overlap. It has a control circuit for controlling each calculation means. One control circuit controls one arithmetic unit to control all instructions, and the other control circuit exclusively controls the other arithmetic unit.

As described above, by providing only a plurality of arithmetic means and control circuits, one control circuit controls all instructions, and the other control circuit exclusively controls the arithmetic means. Thus, an increase in the logical scale can be suppressed.

An instruction code that generates only a control signal, such as a prefix code, reads the instruction, detects that the instruction code is a prefix code, and generates a desired control signal while holding it in the instruction register. By providing a detection circuit and a control signal generation circuit, skipping is enabled, and at the time of skipping, only a control signal is generated. Thereby, the execution time of the instruction can be reduced. Further, since it is sufficient to detect only the prefix code and generate the control signal based on the detected result, the logical scale of the detection circuit and the control signal generation circuit can be minimized.

While maintaining compatibility at the object level,
When there is a CPU having a wide address space (large instruction set) and a CPU having a small address space (small instruction set), the CPU having a wide address space realizes the above-described high speed and has backward compatibility. In addition, the above-described high-speed operation can be similarly performed for an instruction that is also present in a CPU having a small address space. In other words, it is possible to increase the speed of a CPU having a wide address space and a CPU having a small address space by using the same method while maintaining compatibility at the object level. Both the advantages of maintaining compatibility at the object level and the advantage of enabling high speed can be enjoyed.

Since the existing instructions are made executable and the order of the internal operations and the like are made the same, the future expansion margin is not significantly impaired as compared with the existing CPU. For example,
When it becomes possible to add a new instruction to an existing CPU, it is considered that such a technique can be used for a CPU to which the present invention is applied. As long as the compatibility of the instruction set is maintained, the same instruction as that of the existing CPU can be added as a machine language. Also, additional instructions
If it has a plurality of execution states, it can be divided into a part that performs a specific operation and a state that can be omitted, and the latter can be omitted if necessary. At a minimum, instruction reading and program counter increment can be prohibited if necessary.
It can be realized with a processing time equivalent to U. 1 additional instruction
If it can be executed in a state, the speed can be increased by alternate operation of a plurality of arithmetic means (for example, ALU, ALUS).

By using the same instruction set as the existing CPU, development tools such as assembler, C compiler, simulator / debugger, so-called cross software can be shared. By sharing the cross software, the development environment can be quickly set up.

[0050]

FIG. 2 shows an example of a single-chip microcomputer to which the present invention is applied.

Single-chip microcomputer 1
Are the CPU 2 that controls the entire control and the interrupt controller (I
NT) 3, a ROM 4 for storing a processing program of the CPU 2, etc., a RAM 5, a work area for the CPU 2 and a memory for temporarily storing data, a timer 6, a timer 7, a serial communication interface (S
CI) 8, A / D converter 9, system controller (S
YSC) 10, first input / output port (IOP [1]) 11 through ninth input / output port (IOP [9]) 19, and a clock oscillator (CPG) 20. It is formed on one semiconductor substrate (semiconductor chip) by technology.

The single chip microcomputer 1 has a ground level (Vss) as a power supply terminal.
Power supply voltage level (Vcc), analog ground level (AVss), analog power supply voltage level (AVcc),
It has an analog reference voltage (Vref) and further has a dedicated control terminal for reset (RES), standby (STB)
Y), mode control (MD0, MD1), and clock input (EXTAL, XTAL) terminals.

The single-chip microcomputer 1 operates in synchronization with a crystal oscillator connected to the terminals EXTAL and XTAL of the CPG 20 or a reference clock (system clock) generated based on an external clock input to the EXTAL terminal. . One cycle of this reference clock is called a state.

The functional blocks of the single-chip microcomputer 1 are interconnected by an internal bus 21. Internal bus 21 includes an internal address bus, an internal data bus, and an internal controller bus. The internal control bus includes a read signal, a write signal, a bus size signal, a system clock, and the like. CP of internal data bus
The space between the ROM 4 storing the U2 program and the CPU 2 is 32 bits. Although not particularly limited, in the example of FIG. 2, the RAM 5 is also interfaced with a 32-bit bus. In addition, the external bus may be a 32-bit bus.

The internal address bus depends on its phase.
There are two types, AB and PAB, and the internal data bus also has IDB and PDB depending on the phase. For example, in the case of a read, the PAB is delayed by 0.5 state after the IAB. PAB and PDB are synchronized. After PDB, ID
B is delayed by 0.5 state. IAB, PAB, IDB
And PDB are buffered by a bus controller (not shown). These functional blocks and modules are read / written by the CPU 2 via the internal bus. Built-in ROM 4 and RAM 5 are IAB and ID
It is interfaced with the CPU 2 via B and can be read / written in one state. The timer 6, the timer 7, the SCI 8, the A / D converter 9, the IOP [1] 11 to IO
The control registers of the P [9] 19 and the CPG 20 are collectively called internal I / O registers. These are connected to PAB and PDB. Although the bus width of the PDB is not particularly limited, it is 16 bits. This is the internal I / O
Since the registers are dispersed in each functional block, if they are connected by a 32-bit bus, the total wiring length of the bus becomes large, which tends to increase the physical scale, and the internal I / O register ( This is because the meaningful data on each functional block) is 8 to 16 bits, and it is not necessary to access it with 32 bits.

Each of the input / output ports 11 to 19 is connected to an address bus, a data bus, a bus control signal or a timer 6, 7,
It is also used as an input terminal and an input / output terminal of the SCI 8 and the A / D converter 9. That is, timers 6, 7, SCI8, A
The / D converter 9 has an input / output signal, and is input / output to / from the outside via a terminal shared with an input / output port. For example, IOP [5] 15, IOP [6]
16, IOP [7] 17 is also used as input / output terminals of timers 6 and 7, and IOP [8] 18 is also used as input / output terminals of SCI8. The analog data input terminal is IOP [9]
19 is also used.

When the reset signal RES is given to the single-chip microcomputer 1, the single-chip microcomputer 1 including the CPU 2 is reset. When this reset is released, the CPU
2 performs a reset exception process for reading a start address from a predetermined address and starting reading an instruction from the start address. Thereafter, the CPU 2 sequentially executes R
An instruction is read from the OM 4 or the like, decoded, and data processing or the RAM 5, the timer 6,
7, and data transfer with the SCI 8 and the like. That is, CPU2
The instruction stored in the ROM 4 or the like refers to data input from the I / O ports IOP [1] to IOP [9], the A / D converter 9 or the like, or instructions input from the SCI 8 or the like. , And based on the result, I / O ports IOP [1] to IOP [9], timer 6,
7 to output signals to the outside to control various devices.

The statuses of the timers 6 and 7, the SCI 8, and external signals can be transmitted to the CPU 2 as interrupt signals. The interrupt signal is output by a predetermined one of the A / D converter 9, the timer 6, the timer 7, the SCI 8, and the IOP [1] 11 to IOP [9] 19. An interrupt request signal 22 is given to the CPU 2 based on the designation of a predetermined register or the like. When an interrupt factor occurs, the CP
When a U interrupt request is generated, the CPU 2 interrupts the processing being executed, branches to a predetermined processing routine via an exception processing state, performs a desired processing, and clears an interrupt factor.
At the end of the predetermined processing routine, a normal return instruction is placed, and the interrupted processing is resumed by executing this instruction.

FIG. 3 shows a configuration example (programming model) of general-purpose registers and control registers built in the CPU 2.

The CPU 2 has 32-bit general-purpose registers ER0 to ER7. General-purpose registers ER0 to ER
R7 all have the same function and can be used as both an address register and a data register.

As a data register, 32 bits,
Can be used as 16-bit and 8-bit registers. The address register and the 32-bit register are collectively used as general-purpose registers ER (ER0 to ER7). As the 16-bit register, the general-purpose register ER is divided and used as general-purpose registers E (E0 to E7) and general-purpose registers R (R0 to R7). These have the same function, and up to 16 16-bit registers can be used. Note that the general-purpose registers E (E0 to E
7) may be particularly called an extension register. As the 8-bit register, the general-purpose register R is divided into general-purpose registers RH (R0H to R7H) and a general-purpose register RL (R0
L to R7L). These have equivalent functions and can use up to 16 8-bit registers. The method of use can be selected independently for each register.

The general-purpose register ER7 is assigned a function as a stack pointer (SP) in addition to the function as a general-purpose register, and is used implicitly in exception processing and subroutine branching. The exception processing includes the interrupt processing.

PC is a 24-bit counter.
Indicates the address of the instruction to be executed next. Although not particularly limited, all instructions of the CPU 2 are 2 bytes (word:
Since the unit is 16 bits, bit 0 is invalid, and instruction reading is 4 bytes (long word:
32), bit 1 is not used. Also, when the data is saved on the stack, it is treated as a long word size with the upper 8 bits set to 0.

CCR is an 8-bit condition code register, which indicates the internal state of the CPU 2. It is composed of 8 bits including an interrupt mask bit (I) and flags of half carry (H), negative (N), zero (Z), overflow (V) and carry (C).

EXR is an 8-bit register in which control information for controlling exception processing such as interrupts is set, and includes interrupt mask bits (I2 to I0) and trace (T) bits.

For an example of a data configuration on a general-purpose register, a data configuration on a memory space, an addressing mode and a method of calculating an effective address, see, for example, “H8S / 2600 Series H8” issued by Hitachi, Ltd. in March 1995.
This is the same as the CPU described in “S / 2000 Series Programming Manual”.

FIG. 4 shows a configuration example of a general-purpose register and a control register built in another CPU. This has the same configuration as the CPU described in "H8 / 300 Series Programming Manual" issued by Hitachi, Ltd., July 1989, and has 16-bit general registers R0 to R7. The CPU 2 having the programming model of FIG. 3 to which the present invention is applied includes the general-purpose registers and the instruction set of the CPU of FIG. In other words, the CPU 2
Has an upwardly compatible relationship with the CPU having the register and instruction set of FIG.

FIG. 5 shows an example of a machine language instruction format of the CPU 2. The instruction of the CPU 2 is in units of 2 bytes (words). Each instruction is an operation feed (op), a register field (r), and EA
Extension (EA) and condition field (c
c).

Although not particularly limited, the CPU 2
Was published in March 1995 by Hitachi, Ltd. “H8S /
It has the same instruction format as the CPU described in the "2600 Series, H8S / 2000 Series Programming Manual". In particular, basic operation instructions and transfer instructions are 16
It is a bit length (one word).

The operation field (op) indicates the function of the instruction, and specifies the processing content of the operand in the addressing mode. Always include the first 4 bits of the instruction. It may have two operation fields.

The register field (r) specifies a general-purpose register in combination. The register field (r)
Is 3 bits for an address register and 3 bits (32-bit register) or 4 bits (8 or 16-bit register) for a data register. In some cases, there are two register fields, or there are no register fields.

The EA extension (EA) specifies immediate data, an absolute address, or a displacement. 8, 16 or 32 bits. The condition field (cc) specifies a branch condition of a conditional branch instruction (Bcc instruction).

FIG. 1 shows a block diagram of the CPU 2 as an example. The CPU 2 includes a control unit CONT, an execution unit EXEC including the general-purpose registers ER0 to ER7, a program counter PC, and a condition code register CCR.

The control unit CONT controls, for example, F words for three words.
An instruction register 200 comprising an IFO, an instruction register detection circuit (MON) 201, and an instruction register controller (F
IFOCNT) 202, instruction decoder (DEC) 20
3. Sub instruction decoder (DECS) 204 and register selector (SEL) 205 are included. Instruction decoder (DEC)
The sub instruction decoder (DECS) 203 includes, for example, a PLA (Programmable Logic A).
(rray) or wiring logic. An instruction decoder (DEC) 203 supports all instructions and
Performs overall control. Sub-instruction decoder (DECS) 2
04 performs only control for executing an operation such as an inter-register operation instruction at a time overlapping with the instruction decoder (DEC) 203. A part of the output of the instruction decoder 203 is fed back to the instruction decoder 203. This is the stage code (TMG) used for the transition in each instruction code
And a control code (MOD) used between instruction codes. Such a control code is transmitted to an instruction decoder (DEC) 20.
3 and an instruction register detection circuit (MON) 201, and are input to an instruction decoder 203 via a multiplex (MPX) 206. The instruction register detection circuit (MON) 201 has a detection circuit for detecting an inter-register operation instruction and a prefix code, and detects the detection result of the inter-register operation instruction with a signal NXTMON1 and the detection result of the prefix code with a signal NXTMON2. Instruction decoder (D
EC) 203 is instructed. Further, the instruction register detection circuit 201 instructs the decoder 203 by the signal IFMON that the instruction register 200 is being read. The instruction register controller (FIFOCNT) 202
The amount of valid instruction codes held in the instruction register is detected, and the detection result is detected by detection signals FIFOCNT1, FIFOFO.
The instruction is given to the instruction decoder (DEC) 203 by CNT2. The signal detection signals FIFOCNT1, FIFOC
NT2, NXTMON1, NXTMON2, IFMON
Will be described in detail with reference to FIGS. 10 to 13, 22 and 23.

The register selector (RSEL) 205 is
A register selection signal for a general-purpose register or the like is formed based on the outputs of the decoders 203 and 204, and a detection circuit (not shown) is provided when a read and a write of the general-purpose register conflict.

The execution unit EXEC is configured to be able to transfer data in 32-bit units, and includes the general-purpose register and the control register shown in FIG. 3, and the temporary registers TRA and TR.
D, arithmetic logic unit ALU, sub arithmetic logic unit ALU
S, an arithmetic operation unit AU, an incrementer INC, a read data buffer RDB, a write data buffer WDB, and an address buffer AB. These functional blocks are G
B (first internal bus), PCGB (second internal bus),
DB (fifth internal bus), WB (fourth internal bus), P
They are interconnected by an internal bus of CWB (third internal bus).

The internal bus GB is connected to a general-purpose register ER0.
Arithmetic logic unit AL from a predetermined register
Data transfer to U, ALUS, etc., general-purpose register ER0
A predetermined register in ER7 or read data buffer R
DB, arithmetic logic unit ALU to address buffer AB
It is used for transferring addresses to the Internet.

The internal bus PCWB is provided with an address buffer AB and an incrementer I from the program counter PC.
NC, used to transfer an instruction to the write data buffer WDB to an address.

The internal bus DB is connected to a general-purpose register ER0.
Arithmetic logic unit ALU from a predetermined register in ~ ER7
And data transfer to the write data buffer WDB.

The internal bus WB includes an arithmetic and logic unit ALU,
It is used for transferring data from the ALUS or read data buffer RDB to a general-purpose register. Internal bus PCWB
Is the program counter PC from the incrementer INC
Used to transfer the instruction to the address.

The read data buffer RDB is a ROM
4, temporarily storing the read instruction code or data from the RAM 5, the internal I / O register, or an external memory (not shown). Write data buffer WDB is ROM
4. Temporarily store write data to the RAM 5, the internal I / O register, or the external memory, and temporarily store the instruction read address. Read data buffer RDB and write data buffer WDB
2 and an external read / write operation timing of the CPU 2 are adjusted.

The address buffer AB has a function of temporarily storing an address read / written by the CPU 2 and an increment function for the stored content. An address buffer having an increment function is disclosed in
No. 333153.

The incrementer INC is mainly used for addition of PC, and performs + 2 / + 4. The arithmetic unit AU
Is used to generate a branch address of a branch instruction / subroutine branch instruction relative to the program counter. The arithmetic and logic unit ALU is used for various operations specified by instructions, calculation of effective addresses, and the like. The sub-arithmetic-logic operation unit ALUS is used exclusively for operation of an inter-register operation instruction. Whether the instruction to be executed is a register indirect operation instruction is detected by the signal NXTMON1.

The operations of the arithmetic and logic unit ALU and the sub arithmetic and logic unit ALUS are shifted by 0.5 state. The arithmetic and logic unit ALU inputs data during a period when the basic clock (φ) is at a high level, and outputs the result during a period when the basic clock (φ) is at a low level.
On the other hand, the arithmetic operation unit ALUS inputs data during a period when the basic clock (φ) is at a low level, and outputs the result during a period when the basic clock (φ) is at a high level.
The CPU 2 executes instructions in a three-stage pipeline of instruction fetch, decode, and execution. At this time, for example, the addition instruction “ADD.LER0, ER1” and the shift instruction “SHL”
When LER1 "continues, the contents of ER0 and ER1 are synchronized with the high level of the basic clock (φ) and the contents of the bus DB,
The data is read to GB and input to the arithmetic and logic unit ALU. The addition is performed by the arithmetic and logic unit ALU, and the addition result is synchronized with the low level of the basic clock (φ) and the bus W
B. At the low level of the basic clock (φ), read / write of ER1 competes. The contents of bus WB are written to ER1. The contents of ER1 are not read,
Instead, the contents of the arithmetic and logic unit ALU are read to the bus GB and input to the sub arithmetic and logic unit ALUS.
In other words, the arithmetic unit operates in accordance with the order of the instructions and the arithmetic and logic unit A
The LU and the sub-arithmetic logic unit ALUs operate, and the result of one arithmetic logic unit ALU is compared with the result of the other arithmetic logic unit A.
Since it can be used for LUS input, register conflicts can be essentially avoided.

Instructions operate overlapping in the first or last one state of each instruction (an instruction executed in one state is the entire period). Further, during this period, a specific type of operation is performed. (Arithmetic operation), C
A part of the instruction decoding operation of the PU2 may be performed for both arithmetic logic units ALU and ALUS in the overlapped period, and a relatively large instruction decoder (DEC) 203 for controlling other sequential operations is provided. By increasing the sub-instruction decoder (DECS) 204 to be relatively small, it is possible to minimize the increase in logical scale.

Although not particularly limited, the sub-instruction decoder (DECS) 204 includes a sub-arithmetic-logic operation unit ALU
Designation of the type of operation using S (operation control), input / output control of general-purpose registers used in the operation, sub-arithmetic logic operation unit A
The setting control of the condition code register CCR based on the operation result of LUS is performed.

On the other hand, the instruction decoder (DEC) 203
In addition to the above, generation of instruction operation timing, bus control, PC control, calculation of effective addresses, input / output control of general-purpose registers used for calculation of effective addresses, input / output control of data for memory access, control of instruction registers, Performs interrupt control and the like.

Here, the functions of the decoder 203 and the sub-decoder 204 will be supplementarily described. Sub decoder 2
04, when it is detected by the signal NXTMON1 that the instruction is a register indirect operation instruction, the register indirect operation instruction is decoded, and the arithmetic control of the sub-arithmetic logic unit ALUS based on the decoded result is started with a delay of 0.5 state. .

FIG. 6 illustrates the configuration of the ROM 4. The ROM 4 has a maximum of 32 parallel data input / output bits.
The data input / output terminal is connected to the internal data bus IDB. It is configured such that, of consecutive 4 bytes starting from a multiple of four, the byte whose lower address is "0" is higher and the byte whose lower address is "3" is lower.

This ROM 4 collectively stores 32-bit data (long word data) starting from a multiple of 4 in one bit.
Read in state. Further, other 32-bit data starting from an even-numbered address needs to be read twice for each state. Similarly, 16-bit data (word data) starting from an even address can be collectively read in one state. 16 starting from an odd address
Reading of bit data is not permitted. This corresponds to the instruction code being in 16-bit units. The ROM 4 can read 8-bit data (byte data) at an arbitrary address in one state.

That is, when 16-bit instructions are consecutive, two instructions can be read by reading the ROM 4 once. The read / write of the RAM 5 has the same configuration.

FIG. 7 illustrates an addressing mode of the CPU 2. The register indirect (@ERn) specifies an operand on the memory using the contents of the address register (ERn) specified by the register field (r1) of the instruction code as an address.

Post-increment register indirect ($ E
Rn +) is an instruction code register field (r1)
The operand on the memory is designated by using the contents of the address register (ERn) designated by (1) as an address. Thereafter, 1, 2, or 4 is added to the contents of the address register, and the addition result is stored in the address register. By size
1, 2 is added for word size, and 4 is added for long word size.

Pre-decrement register indirect ($ -ER
n) is 1, 2 from the contents of the address register (ERn) specified by the register field (r1) of the instruction code.
Alternatively, an operand on the memory is designated by using the content obtained by subtracting 4 as an address. After that, the subtraction result is stored in the address register. 1 is subtracted for byte size, 2 for word size, and 4 for longword size.

The register indirect with displacement ($ (d: 16, ERn)) corresponds to the address register (E) specified by the register field (r1) of the instruction code.
The operand on the memory is designated by using the content obtained by adding the 16-bit displacement (d) included in the instruction code to the content of Rn) as an address. When adding, 1
The 6-bit displacement is sign-extended.

The absolute address ($ aa: 16) is an absolute address (aa) included in the instruction code and specifies an operand on the memory. Although not particularly limited, 1
In the case of a 6-bit absolute address, the upper 16 bits are sign-extended.

FIG. 8 shows a transfer instruction “MOV.W@aa:
16, Rd ". The operation timing of (1) in FIG.
-1) and (1-2) include a control unit (in particular, the instruction decoder 20).
3) The operation of the CONT is shown, and the operation of the execution unit EXEC is shown in (2) of FIG. Actually, the control unit CO
Since the execution unit EXEC operates based on the control signal output from the NT, there is a time difference between the operation of the control unit CONT and the operation of the execution unit EXEC. In FIG. 8, the time difference is expressed as 0 for convenience. I have. In the operation of the control unit CONT, (1-1) is an operation equivalent to the conventional technology,
(1-2) corresponds to an example of an operation unique to the present invention.

The execution unit EXEC executes the first state ST1
Then, the instruction read (if) of the next instruction and the PC increment (+4: +2 in the prior art) are performed. Second state S
At T2, the EA extension (aa) of this instruction is transferred from the read data buffer to the address buffer via the internal bus (GB), and a bus command for data read is issued. In the third state ST3, the instruction read (if) of the next next instruction and the program counter PC increment (+4: +2 in the prior art) are performed, and the second instruction is executed.
The data read in state ST2 is transferred from the read data buffer to the general-purpose register via the internal bus (WB), the data is checked, and the result is set in the condition code register CCR.

The operation (1-1) of the control unit CONT is controlled in accordance with the operation of the execution unit EXEC.
That is, a control signal for outputting an address and generating a bus command is generated in the second state ST2, and a control signal for storing read data is generated in the third state ST3. In addition, “H8S / 2600 Series H8” issued by Hitachi, Ltd.
In the S / 2000 Series Programming Manual, the PC increment is +2, read data is input from the read data buffer to the arithmetic unit (ALU) via the internal bus (GB), and the arithmetic unit (ALU) remains unchanged. Data is output to the internal bus (WB) and stored in a general-purpose register. Through the arithmetic unit (ALU), the increase of the internal bus is suppressed (three types of GB, DB, and WB), and the data inspection circuit and the flag set circuit of the arithmetic unit (ALU) are shared. These detailed differences are omitted.

In operation (1-2) of control unit CONT, control for data access is performed in second state ST2. That is, in the second state ST2, a control signal for outputting an address, generating a bus command, and storing read data is generated. The operation unit EXEC is first supplied with a control signal for outputting an address and generating a bus command, and stores read data (RDB-R) in the next state.
The control signal of d) is provided.

In the first state ST1 and the third state ST3 of the control unit CONT, only the instruction read (if) and the PC increment (+4) are performed. These first and third
States ST1 and ST3 are an instruction register (FIFO)
It is skipped (skipped) according to the number of instructions that have been read to 200. If the number of read instructions is small, the first state ST1 and the third state ST3 are executed, and instructions longer than the instruction length (two words) of this instruction are read. If the amount of the read instruction is appropriate, one of the first state ST1 and the third state ST3 is executed, and an instruction having the same amount as the instruction length (two words) of the present instruction is read. If there are many instructions that have been read, the first state ST1 and the third state ST3 are not executed, and no instructions are read. Which operation is performed depends on the above-mentioned FIFOCNT1, FIFOCNT,
The instruction decoder 203 determines using a signal such as IFMON.

For example, when this instruction is executed continuously for a plurality of instructions, the first state ST1 and the second state ST
2 (the third state ST3 is omitted). The word size (1) of the third state ST3 of the instruction before receiving the same control as the conventional one shown in (1-1) of FIG.
6 bits) Instruction read and first state ST1 of next instruction
Can be understood to be combined with the long word size (32 bit) instruction read of the first state ST1 according to the present invention which is controlled by the control shown in (1-2) of FIG.

When one of the first state ST1 and the third state ST3 is executed, which one is executed and which is omitted (skipped) is determined by the state of the instruction read before that. At the beginning of the branch destination of the branch instruction,
If the address is not a multiple of 4, only the first word of the instruction is prefetched, and the first state ST1 is executed to wait for the second word of the instruction. Even in the case of a multiple address of 4, the first state ST1 is omitted (skipped) and the third state ST3 is executed because the second word of the instruction has already been read (prefetched) at the same time.

FIG. 9 shows a branch instruction (JMP @aa: 2
The operation timing of 4) is shown. 9A shows the operation of the control unit (particularly, the instruction decoder 203) CONT, and FIG. 9B shows the operation of the execution unit EXEC. 8, the operation of the control unit CONT and the execution unit E
The time difference from the XEC operation is expressed as 0 for convenience.

In FIG. 9, the first state ST1 is for waiting for the completion of the reading of the second word of the own instruction, and can be omitted (skipped) if the second word has been read. Read the instruction at the branch destination twice. The first time, the read instruction is fetched into the CPU 2, but the second time only the instruction read is issued, and the fetch of the read instruction into the CPU 2 overlaps the execution of the next instruction.

At the first time, when the address is a multiple of 4, two words are read, and the PC increment is +4. When the address is not a multiple of 4, one word is read, and the PC increment is +2.

For this reason, the same branch instruction (JMP
If (aa): 24) is present and the branch destination is a multiple address of 4, the execution is started with the read (prefetch) of the second word of the instruction being completed. Can be omitted (skipped). If the branch destination is not a multiple of 4, the execution is started in a state where the reading of the second word of the instruction is not completed, so that the first state ST1 cannot be omitted (skipped).

When a branch instruction is executed, execution of the instruction at the branch destination can be started at the same timing as in the prior art. In the case of branching to a multiple of four, the execution of the instruction at the branch destination can be shortened. Responsiveness such as branch instructions and interrupt exception handling can be maintained and improved.

As described above, a branch instruction is executable irrespective of the address where it is located. Although the number of execution states is different, the number of execution states is at least the same as the conventional one. Rather, there is no need to insert a no-operation instruction, and it is not necessary to put a burden on software.

FIGS. 10 to 13 show timing charts when the program is executed. The execution program is L0 JMP L1 L1 MOV. W ＠ aa1, R0 ADD. W R0, R1 EXTS. LER1 MOV. L ER1, ＠ aa2.

Note that MOV. L ER1, ＠ aa2 is M
OV. It has an instruction code obtained by adding a prefix code to the instruction code of W R1, $ aa2. Such a prefix code generates a control signal and the subsequent instruction code (MOV.WR)
1, .DELTA.aa2).
1981, etc.

In FIGS. 10 to 13, the addresses where the instructions are arranged are different, and the labels L0 and L1 are labeled in FIG.
L0 = 2, L1 = 14, that is, L0. EQU 2 L1. In FIG. 11, L0 = 2, L1 = 12, that is, L0. EQU 2 L1. In FIG. 12, L0 = 0 and L1 = 14, that is, L0. EQU 0 L1. In FIG. 13, L0 = 0 and L1 = 12, that is, L0. EQU 0 L1. EQU 12, The data is common, aa1 = 102, 1
12 = 104, ie, aa1. EQU 102 aa2. EQU 104.

The first state of the branch instruction can be omitted if an instruction code for one word exists in the instruction register (FIFO) 200 (FIFOCNT1 = 1).

The first state of the transfer instruction (MOV.W) can be omitted if the instruction register (FIFO) 200 has an instruction code for one word.

In the third state of the transfer instruction (MOV.W), an instruction code for two words exists in the instruction register (FIFO) 200 (FIFOCNT1 = FIFOCN).
T2 = 1) or the instruction register (FIFO) 2
00 when an instruction code for one word exists and the instruction read is being executed (FIFOCNT1 = IFMON =
In 1), it can be omitted.

The register-to-register operation instruction includes an instruction register (F
(IFO) 200 has an instruction code for two words (FIFOCNT1 = FIFOCNT2 = 1), or an instruction register (FIFO) 200 has an instruction code for one word and the instruction is being read ( When FIFOCNT1 = IFMON = 1, when the next instruction is an inter-register operation instruction or the like (NXTMON1 = IFMON = 1)
1) Instruct the operation of the sub instruction decoder (DECS) 204 and the sub arithmetic logic unit ALUS.

The first state (prefix code, NXTMON2 = 1) of the transfer instruction (MOV.L) can be omitted if an instruction code for one word exists in the instruction register (FIFO) 200. If not omitted, the prefix code is decoded by the instruction decoder, the instruction read and PC increment are performed, and a control signal is generated. If omitted, generate the desired signal from the instruction register,
Input to the instruction decoder.

The second state of the transfer instruction (MOV.L)
The fourth state is the same as the first and third states of the transfer instruction (MOV.W).

In the case of FIG. 10, the operation is as follows.
Slot C2 in cycle T0 of reference clock φ
In the (low-level period of the reference clock φ), the CPU 2
When a branch instruction (not shown) is executed, an instruction fetch (i
f), and outputs an address from the address buffer AB to the address bus IAB. Similarly, slot C in cycle T1
In step 2, a bus command and the next address are output.

On the basis of the contents of the address bus IAB and the bus command, the contents of the internal ROM 4 are obtained on the internal data bus IDB in the slot C2 of the cycle T1. ), The data is latched in the instruction register (FIFO) 200 and the read data buffer RDB. Since the instruction address at this time is not a multiple of 4, only the lower side (bits 15 to 0) of the internal data bus IDB is used. Similarly, the contents of the next address are latched in the instruction register (FIFO) 200 and the read data buffer RDB in the slot C1 of the cycle T2. In this case, since the address is a multiple of 4, the upper (bits 31 to 16) and lower (bits 15 to 0) of the internal data bus IDB are used.

The instruction code (jmp-1) is input to the decoder (DEC) 203 in the slot C1 of the cycle T2, and the contents of the instruction are decoded.

Since the reading of the second word (jmp-2) of the own instruction has not been completed, the first state ST1 is executed.

In the slot C2 of the cycle T2, the bus command is set to no operation, and the read / write is not started.

In the slot C2 of the cycle T3, the contents of the read data buffer RDB (absolute address = 14) are
Via the internal bus GB, the data is stored in the address buffer AB, output to the address bus IAB, issue a bus command, and read the instruction. Similarly, a bus command and the next address are output in slot C2 of cycle T4, and the instruction is read.

The read contents are latched in the instruction register (FIFO) 200 and the read data buffer RDB in the slot C1 in the cycle T5 and the slot C1 in the cycle T6.

The contents of the internal bus GB are also input to the write data buffer WDB and the incrementer INC, and the increment (+ 2 /
+4) is performed.

In the slot C1 of the cycle T4, the result (1) of the increment (+2) by the incrementer INC
6) is the program counter P via the internal bus WB.
Written to C. Similarly, slot C in cycle T5
1, the result (20) incremented (+4) is
The data is written to the program counter PC via the internal bus WB.

The instruction code (mov-1) is input to the decoder (DEC) 203 in the slot C1 of the cycle T5, and the contents of the instruction are decoded.

Since the reading of the second word (mov-2) of the own instruction has not been completed, the first state ST1 is executed.

The bus command and the next address are output in slot C2 in cycle T5, and the instruction is read. In addition, the program counter PC is incremented.

In slot C2 of cycle T6, the contents of read data buffer RDB (absolute address = 102)
Is stored in the address buffer AB via the internal bus GB and is output to the address bus IAB, and at the same time, a bus command is issued to read data. The third state ST3 is omitted (skipped).

The read data is stored in the read data buffer RDB in the slot C1 in the cycle T8, and is written to the general-purpose register ER0 (substantially R0) via the internal bus WB. In addition, the data in the read data buffer RDB is inspected, and the result is reflected in predetermined bits (for example, negative N, zero Z, overflow V) of the condition code register CCR. This operation is performed based on the result of decoding the instruction code (mov-1), but is executed at a time overlapping with the next instruction.

The instruction code (add) is input to the decoder (DEC) 203 in slot C1 of cycle T7,
The contents of the instruction are decoded.

The bus command and the next address are output in slot C2 of cycle T7, and the instruction is read. In addition, the program counter PC is incremented.

In the slot C1 of the cycle T8, the contents of the general-purpose register ER1 (R1) are read out to the internal bus GB.
Input to arithmetic and logic unit ALU. Also, the contents of the general-purpose register ER0 (R0) are read to the internal bus DB, but are read from the read data buffer RDB (the delay time can be minimized) because of a conflict with the write of the previous instruction. Input to arithmetic and logic unit ALU. The arithmetic and logic unit ALU is instructed to add.

At slot C2 in cycle T8, the operation result is stored in general-purpose register ER1 (R1). Further, the operation result is inspected, and the result is reflected on predetermined bits (for example, negative N, zero Z, overflow V, carry C, half carry H) of the condition code register CCR.

Since the next instruction code is an inter-register operation instruction (NXTMON1 = 1), the sub-instruction decoder (DECS) 204 in slot C2 of cycle T7.
, An instruction code (exts) is input.

At the slot C2 in the cycle T8, the contents of the general-purpose register ER0 are read to the internal bus GB. Input to the arithmetic and logic unit ALU. Extension is instructed to the arithmetic and logic unit ALU.

At slot C1 in cycle T9, the operation result is stored in general-purpose register ER0. Further, the operation result is inspected, and the result is reflected in predetermined bits (for example, negative N, zero Z, overflow V) of the condition code register CCR.

In the slot C1 of the cycle T8, the instruction code (movl-1) is input to the decoder (DEC) 203, and the contents of the instruction are decoded.

Since the reading of the second word (movl-2) of the own instruction has not been completed, the first state (prefix code) ST1 is executed.

The bus command and the next address are output in slot C2 in cycle T8, and the instruction is read. In addition, the program counter PC is incremented. Further, it generates a control signal to transmit an instruction (in this case, an instruction of long word size) to the next instruction code.

At slot C1 in cycle T9, the instruction code (movl-2) is input to the decoder (DEC) 203, and the contents of the instruction are decoded.

The reading of the third word (movl-3) of the own instruction has been completed, and the second state ST2 is omitted (skipped). Since the read of the next instruction has not been issued, the fourth state is executed.

The operation of FIG. 11 will be described below solely with respect to differences from FIG. In the slot C1 of the cycle T5, the instruction code (mov-1) is
EC) 203, and the contents of the command are decoded.
At this time, the reading of the second word (mov-2) of the own instruction has been completed, and the first state ST1 is omitted (skipped). Since the read of the next instruction has been issued, the third state ST3 is omitted (skipped).

The instruction code (add) is input to the decoder (DEC) 203 in the slot C1 of the cycle T6.
The contents of the instruction are decoded.

The next instruction code is an inter-register operation instruction, but since the reading of the next instruction has not been completed,
No instruction code (exts) is input to sub-instruction decoder (DECS) 204.

In the slot C1 of the cycle T7, the instruction code (exts) is input to the decoder (DEC) 203, and the contents of the instruction are decoded.

An operation is performed using the arithmetic and logic unit ALU. Since no register conflict occurs, the general-purpose register ER0 is read.

In slot C1 of cycle T8, it is determined that the instruction code (movl-1) is a prefix code (N
XTMON2 = 1), the instruction code (movl-2) is input to the decoder (DEC) 203, and the content of the instruction is decoded. Since the reading of the third word (movl-3) of the own instruction has not been completed, the second state ST2 is executed. The reading of the next instruction has been completed, and the fourth state is omitted (skipped).

The operation of FIG. 12 will be described mainly with respect to differences from FIG. 10 as follows. In the slot C1 of the cycle T2, the instruction code (jmp-1)
EC) 203, and the contents of the command are decoded.
The reading of the second word (jmp-2) of the own instruction has been completed, and the first state ST1 is omitted (skipped). The subsequent operation is the same as in FIG.

The operation of FIG. 13 will be described mainly with respect to the differences from FIG. 10 as follows. As in FIG. 12, the instruction code (jmp
-1) is input to the decoder (DEC) 203, and the contents of the instruction are decoded. The second word (jmp-
Since the read of 2) has been completed, the first state is omitted (skipped). The subsequent operation is the same as in FIG.

In the prior art, the five instructions can be executed in 12 states. In contrast, FIG.
The states are executed in eight states in FIGS. 11 and 12, and seven states in FIG. The number of states required for processing is reduced to 58 to 75%. This is because there is variation depending on whether the branch destination is a multiple address of 4, but when the branch destination is not a multiple address of 4, the upper side of the internal data bus IDB cannot be used, and the throughput of the internal bus decreases.

When it is desired to arrange a desired program at a multiple address of 4 in order to improve the processing speed of a predetermined program, it is possible to provide a control instruction for aligning the multiple address of 4 with the assembler and use this. it can. Such a control command is described in, for example, “H8S, H8 / 300 Series Cross Assembler” issued by Hitachi, Ltd. in May 1992.
p62 and the like. The control instruction for alignment is not converted into a microcomputer instruction, and the change does not significantly impair the program quality or the like.

Further, in the above operation timing example, in the case of a short program, immediately after the branch instruction,
Further, since the branch instruction is executed, the effect of the improvement of the present invention cannot always be said to be maximized.

For example, in the case where only the inter-register operation instruction is continuously executed, two instructions are effectively executed in one state by alternately operating the ALU and the ALUS. Can be shortened to

In addition, since the speed that has been increased by omitting (skipping) the states that can be omitted from the expanded bus width, the instruction read time can be typically halved.
If the instruction read is 80% and the data access is 20%, it can be reduced to 60%. If the instruction read is 70% and the data access is 30%, it can be reduced to 65%.

Although it depends on the contents of the program, an improvement effect of about 50 to 75% can be obtained as a whole program.

FIG. 14 illustrates a block diagram of the incrementer INC. The incrementer INC increments the program counter PC (+ 2 / + 4).

As described above, two sets of arithmetic logic units AL
U and ALUS, but incrementer INC
Are not two sets but one set. Except for the branch instruction and the like, the increment of the program counter PC is +4. Therefore, the lower two bits of the normally input program counter PC are 2'b00.

The incrementer INC includes each bit half adder 300, inputs the internal bus GB, and outputs to the internal bus PCWB. Only for bit 1, the data input is applied to the logical value 1 (+
2) and carry (logical value 1) input (+
2) Do it. That is, +4 is realized by performing +2 twice.

In the case of a branch instruction, if the address of the branch destination is a multiple of 4 (bit 1 is 0), +4 is performed in the same manner as in the case of other than the branch instruction. If the address of the branch destination is not a multiple of 4 (bit 1 is 1), the logical sum circuit 301
Since there is no meaning of +2, only +2 of carry input is performed.

Thus, + 2 / + 4 is automatically selected according to the branch destination address. In other words, the smallest multiple of 4, which is larger than the input content, is output.

FIG. 15 illustrates a block diagram of the write data buffer WDB. Write data buffer WDB
Is the three parts WDB-M, WDB-S and WDB-OUT
The WDB-M can receive an input from the internal bus GB, can transfer the data from the WDB-M to the WDB-S, and can transmit the data from the WDB-M and the WDB-S to the WD.
Transfer to B-OUT is enabled, and WDB-O
Input from the internal buses GB and DB is enabled to the UT. On the other hand, from the WDB-M and WDB-S, the internal bus GB
Can be output to The output to the data bus IDB is W
Performed from DB-OUT.

The value of the program counter PC to be saved is stored in the write data buffer WDB in advance. The value of the program counter PC to be saved is stored in the write data buffer WDB in advance. According to the present invention, according to the present invention, the instruction code length of the instruction itself and the state of the instruction read being executed at the start of the instruction execution (IFMON) are described in the present invention.
The output method of the program counter PC value to be saved is different.

More specifically, if a 1-word instruction is present at an address that is a multiple of 4 and an instruction is being read (IFMON =
1) The value of the program counter PC to be saved is stored in WDB.
-S to the internal data bus IDB. At that time, the bit 1 of the PC value is fixed to 1.

A one-word instruction existing at a multiple address of 4
If the instruction is not being read (IFMON = 0), the value of the program counter PC to be saved is obtained from the WDB-M to the internal data bus IDB. Also, bit 1 of the PC value at that time is fixed to 1 (see T8 in FIG. 21).

If the instruction is being read (IFMON = 1) with a one-word instruction that does not exist at a multiple address of 4, the value of the PC to be saved is obtained from the WDB-S to the internal data bus IDB. At this time, the PC value is not fixed to 1 for bit 1.

If the instruction is not being read (IFMON = 0) for a one-word instruction that does not exist at a multiple address of 4, the value of the program counter PC to be saved is obtained from the WDB-M to the internal data bus IDB. At this time, the PC value is not fixed to 1 for bit 1 (see T9 in FIG. 20).

With a two-word instruction existing at a multiple of four,
If the instruction is being read (IFMON = 1), the program counter PC value to be saved is obtained from the WDB-M to the internal data bus IDB. The bit 1 is not fixed.

A two-word instruction at a multiple address of 4
If the instruction is not being read (IFMON = 0), the value of the program counter PC to be saved from the PC is obtained on the internal data bus IDB. Bit 1 is not fixed (FIG. 19).
T8 part).

If a 2-word instruction that does not exist at a multiple address of 4 is being read (IFMON = 1), the value of the program counter PC to be saved is obtained from the WDB-S to the internal data bus IDB. At that time, the bit 1 of the PC value is fixed to 1.

If the instruction is not being read (IFMON = 0) for a two-word instruction that does not exist at a multiple address of 4, a program counter PC value to be saved is obtained from the WDB-M to the internal data bus IDB. At this time, bit 1 of the PC value is fixed to 1 (see T10 in FIG. 18).

In the program-relative addressing mode, a displacement (relative value) is added based on the address of the next instruction, and the address of the next instruction used for this is a program counter saved at the time of a subroutine branch instruction. Since the value becomes the same as the value of the PC, the contents of the write data buffer WDB can be used. That is, similarly to the above, the address of the next instruction may be appropriately read from the WDB-M, WDB-S or the program counter PC to the internal bus GB, and the displacement and the addition may be performed by the arithmetic and logic unit ALU or the like. Setting the bit 1 to 1 may be performed by the arithmetic and logic unit ALU, on the internal bus GB, or on the write data buffer WDB or the program counter PC.

FIG. 16 shows an example of an arithmetic operation unit AU for calculating a program relative branch address. Arithmetic unit A
U is a value of the program counter PC stored in the write data buffer WDB (also simply referred to as a PC value) prior to the start of execution of the one-word-length program relative branch instruction.
Through the multiplexer MPX. Because it is one word long, the program counter PC is not used. Further, the arithmetic operation unit AU inputs the 8-bit displacement included in the instruction code, which is held in the read data buffer RDB or the instruction register (FIFO) 200, via the internal bus DB. Arithmetic unit AU adds both inputs. When such a branch instruction is present at a multiple address of 4, the control signal pls2 further fixes bit 1 of the PC value to 1, thereby making it possible to simultaneously execute +2 simultaneously.

By having the arithmetic unit AU for calculating the program relative branch address, the branch address can be calculated irrespective of the operation state of the arithmetic and logic unit ALU, and the speeding up of the branch can be realized.

The program-relative addressing mode is not limited to the branch instruction but can be used for a transfer instruction and the like, and the arithmetic and logic unit AU can speed up the calculation of the effective address and thus improve the processing speed of the instruction.

FIG. 17 shows a subroutine branch instruction (JSR
＠Aa: 24) is shown. The representation format in the figure is the same as in the case of FIG. In FIG. 17, the third state ST3 is the same as the branch instruction in FIG. 9 except that a state for stacking the program counter PC is inserted. The first state ST1 is for waiting for the completion of the reading of the second word of the own instruction, and is omitted (skipped) if the second word has been read. Instruction read at branch destination address in second state ST2, third state S
The reading of the next instruction in the stack of T3 and the fourth state ST4 is an operation unique to the subroutine branch instruction, and is not omitted (skipped).

FIGS. 18 and 19 show an example of an execution timing chart of a program including a subroutine branch instruction. In each figure, the following program L0 JMP L1 L1 MOV. The timing when W を aa1, R0 JSR L2 is executed is shown. 18 and 19, the addresses where the instructions are arranged are different.
In FIG. 18, the labels are L0 = 2, L1 = 14, L2 =
40, that is, L0. EQU 2 L1. EQU 14 L2. In FIG. 19, L0 = 2, L1 = 12, L2 = 40, that is, L0. EQU 2 L1. EQU 12 L2. EQU 40.

The subroutine branch instruction has an instruction code having a length of two words.
Because it exists at address 18 (~ 21), it should be saved
The content of the PC value is 22. In FIG. 19, since the subroutine branch instruction exists at the address 16 (to 19), the PC value to be saved is 20. FIG.
8 and 19, the operation timing before execution of the subroutine branch instruction is the same as in FIGS. 10 and 11.

In FIG. 18, slot C1 in cycle T7
The instruction code (jsr-1) is the decoder (DEC) 20
3, the contents of the command are decoded. At this point, the PC value is the address to read the next instruction (24),
The write data buffer WDB-M stores the address (20) at the time of the previous instruction read, and WDB-S stores the address (16) at the time of the previous and previous instruction read.

At slot C2 in cycle T7, WDB-
The contents of M are transferred to WDB-OUT (20).

At the slot C1 in the cycle T9, the stack pointer SP is read out to the internal bus GB, and is input to the arithmetic and logic unit ALU to decrement (-4).

In the slot C2 of the cycle T9, the result of the decrement is read out to the internal bus WB, written to the stack pointer SP, read out to the internal bus GB, stored in the address buffer AB, and stored in the address buffer AB. Output to At the same time, a long word data write bus command is issued.

As for the write data, the contents of WDB-OUT are output with the bit 1 fixed to 1 in slot C1 of cycle T10, and the contents (22) are stored in the stack.

In FIG. 19, slot C1 in cycle T6
The instruction code (jsr-1) is the decoder (DEC) 20
3, the contents of the command are decoded.

At this point, the PC value is the address (20) at which the next instruction is to be read, and the write data buffer WDB-M
Contains the address (16) at the time of the previous instruction read, WDB-
In S, the address (12) at the time of the previous and previous instruction read is stored.

In the slot C2 of the cycle T7, the contents (20) of the PC value are transferred to the WDB-O via the internal bus DB.
Transfer to UT.

In the slot C1 of the cycle T7, the stack pointer SP is read out to the internal bus GB, and is input to the arithmetic and logic unit ALU to decrement (-4). In slot C2 of cycle T7, the result of the decrement is read out to the internal bus WB, and the stack pointer SP
To the internal bus GB, and
The data is stored in the address buffer AB and the internal data bus IA
Output to B. At the same time, a long word data write bus command is issued.

As the write data, the contents of WDB-OUT are output in slot C1 in cycle T8 (bit 1 is not fixed), and the contents (22) are stored in the stack.

FIGS. 20 and 21 show an example of the execution timing of a program including another subroutine branch instruction.

In FIG. 20, as a subroutine branch instruction, the addressing mode is not an absolute address but a memory indirect, and the following program L0 JMP L1 L1 MOV. W ＠ aa1, R0 JSR ＠＠ L3 L3. DATA. A timing diagram when LL2 is executed is shown. In this case, the labels are L0 = 2, L1 = 14, L2 = 40,
L3 = 160, that is, L0. EQU 2 L1. EQU 14 L2. EQU 40 L3. EQU 160. In the memory indirect, the memory is read according to the address (L3) included in the instruction code,
The read content (L2) becomes the branch address.

The timing of FIG. 20 is the same as that of FIG. 10 before execution of the subroutine branch instruction. The instruction code (jsr) is input to the decoder (DEC) 203 in the slot C1 of the cycle T7 in FIG. 20, and the content of the instruction is decoded.

At this point, the PC value is the address (24) at which the next instruction is to be read, and the write data buffer WDB-
M is the address (20) at the time of the previous instruction read, WDB
In -S, the address (16) at the time of the previous and previous instruction read is stored.

In slot C2 of cycle T7, WDB-
The contents of M are transferred to WDB-OUT (20). In the slot C1 in the cycle T9, the stack pointer SP is read out to the internal bus GB, and is input to the arithmetic and logic unit ALU to decrement (-4). In slot C2 of cycle T9, the result of the decrement is read out to the internal bus WB, written to the stack pointer SP, and also read out to the internal bus GB, so that the address buffer A
B and output to the internal data bus IAB. At the same time, a long word data write bus command is issued.

The write data is output with the content of WDB-OUT fixed at bit 1 of the write address at 1 in slot C1 of cycle T10, and the content (22) is stored in the stack.

In FIG. 21, as a subroutine branch instruction, the relative address of the program counter is used as an addressing mode, and after branching with a branch instruction, the following program L0 JMP L1 L1 MOV. The timing when W ＠ aa1, R0 BSR L2 is executed is shown. In this case, the labels are L0 = 2, L1 = 12, L2 = 40, that is, L0. EQU 2 L1. EQU 12 L2. EQU 40. In this case, the displacement of the BSR is 22 (decimal number).

In FIG. 21, before the execution of the subroutine branch instruction, the timing is the same as in FIG. In slot C1 of cycle T6, the write data buffer WD
B and the PC value (16) stored in the read data buffer RDB and the 8-bit displacement (2
2) is input to the arithmetic operation unit AU, and further, the fixation of bit 1 of the PC value to 1 is instructed, the addition is performed, and the addition result (40) is output to the internal bus GB in the slot C2 of the cycle T6. Then, the data is stored in the address buffer AB and output to the internal address bus IAB.

In the slot C2 of the cycle T6, the content (16) of the write data buffer WDB-M is changed to WD
B-OUT and transferred to slot C1 in cycle T9.
Is fixed to 1 and output to the internal data bus IDB. This content (18) is written to the stack as a return address. The fixing of bit 1 to 1 is performed in response to the fact that bit 1 of the address where the BSR exists is 0.

FIGS. 22 and 23 show a decoder (DEC).
A logical description of a part of the decode logic corresponding to the transfer instruction of FIG. The logical description shown in the figure is RTL (Register Transfer Level) or H
It is called DL (Hardware Description Language) description,
It can be developed into a logic circuit by using a known logic synthesis tool. HDL is standardized as IEEE1364. The syntax of the logical description shown here conforms to the case statement, and is always
When the value or signal defined in () following s ＠ changes, the description line below that value is processed. Note that "5'b00001" means 5-bit binary data 00001. IR
[8] means the logical value of the ninth bit from the least significant of the instruction register IR (input value of DEC). The symbol ~ means logical value inversion.

The logical description of FIGS. 22 and 23 corresponds to the logical description for decoding the code of the transfer instruction “MOV.W@aa: 16, Rd”. In the logical description of FIGS. 22 and 23, 16'b0110_101? _? ? 00_? ? ? ? Means the code of the transfer instruction. Byte size when IR [8] = 0, word size when IR [8] = 1,
When IR [7] = 0, transfer from memory to general-purpose register (read type), and when IR [7] = 1, transfer from general-purpose register to memory (write type). In that instruction, the first
Whether to omit the state ST1 and the third state ST3,
Signal FIFOCNT1, FIFOCNT2, IFMON
Is determined according to the condition of That is, in the logical description, a control signal is generated according to the stage code TMG, and the current value of the stage code TMG and the FIFOCNT1, FIFOCNT2, and IFMO at that time are output.
According to the value of N, etc., the next stage code NEXTTT
The value of MG is determined, whereby
It is determined whether the first state ST1 and the third state ST3 are omitted. Referring to FIG. 22, the first state ST1
Is 1, the stage code of the second state ST1 is 17, and the stage code of the third state ST1 is 3.

More specifically, the first logical description in FIG.
The stage code TMG is generated in the portion (1-1). The stage code TMG progresses from 1 → 17 → 3, but FIFOCNT1, FIFOCNT2, IFMON
, The stage code 17 and the stage code 3 are omitted. In the stage code 1, if the second word of the own instruction has been read (FIFOCNT1 = 1),
Controls data read / write. If the second word of the own instruction has not been read in the stage code 1 (FIFOCNT1 = 0), the process proceeds to the stage code 17 to control data read / write.

Bus control is performed in the second part (1-2) of the logical description. nop = 0 starts bus access, nop
= 1 indicates bus access prohibition. Data = 0 indicates an instruction read, and data = 1 indicates a data access.
Byte = 0 indicates a word size, and byte = 1 indicates a byte size. write = 0 is read, wr
te = 1 indicates a write.

In the case of this transfer instruction, when the second word of the own instruction has not been read by the stage code 1, or when the instruction is read by the stage code 3 and the second word of the own instruction has already been read by the stage code 1. , Or the stage code 17 performs data access. Read / write of data access is instructed by IR [7].
In the case of an instruction read, the contents of the internal data bus IDB are stored in the IR and the read data buffer RDB at a predetermined timing. In the case of data read, the contents of the internal data bus IDB are read at a predetermined timing and read data buffer
B. In the case of data write, the contents of the write data buffer WDB are output to the internal data bus IDB at a predetermined timing.

Third Part (1-3) of Logical Description in FIG.
To calculate the effective address. In the case of this transfer instruction, if the second word of the own instruction has already been read in the stage code 1,
Alternatively, the read data buffer R
The 16-bit EA extension part of the instruction code held in the DB is sign-extended to 32 bits by the rdbext signal, and then output to the internal bus GB. When the second word of the own instruction has not been read by the stage code 1, and by reading the PC value to the internal bus PCGB, input to the address bus AB and the incrementer INC, and the internal of the increment result in the stage code 3. Bus PCWB instructs storage in program counter PC. In addition,
When the input from the internal bus PCGB is not instructed to the address buffer AB, the input is made from the internal bus GB. Note that rdbgb is an instruction signal for outputting the other use of the read data buffer RDB to the bus GB.
ext is an instruction signal for sign-extending the read data buffer RDB.

The fourth part (1) of the logical description in FIG.
In -4), transfer data and registers are controlled. In the case of the read type (IR [7] = 0), when the second word of the own instruction has been read by the stage code 1, or the read data is read by the stage code 17 into the read data buffer R
The data is output from the DB to the bus WB and stored in the general-purpose register (Rd). Of the condition code register CCR,
The update of the N, Z, and V flags is instructed. As shown in FIG. 8 and the like, the control of this operation is delayed. The delay circuit itself is not shown.

In the case of the write type (IR [7] = 1), the stage code 1 has already read the second word of its own instruction, or the stage code 17 has the general-purpose register (R
The data is output from d) to the internal bus DB, and in any case, the data is stored in the write data buffer WDB. Further, it instructs updating of the N, Z, and V flags of the condition code register CCR.

FIGS. 24 to 26 show a decoder (DEC).
The logical description of a part of the decode logic for the branch instruction / subroutine branch instruction of FIGS. 9 and 17 included in 203 is shown. The representation format in the figure is the same as that in FIGS. 22 and 23. In the decoding logic of FIGS. 24 to 26, when IR [10] = 0, branch (JMP) and IR [1
0] = 1, the subroutine branch (JSR) is determined.

The stage code TMG is generated in the first part (2-1) of the logical description shown in FIG. The stage code TMG progresses from 1 → 17 → 2 → 3, but F
The stage code 17 is omitted depending on the state of IFOCNT1, FIFOCNT2, and IFMON. In stage code 1, the second word of own instruction has been read (FIF
If OCNT1 = 1), the control of the effective address calculation and the instruction read of the branch destination are performed. In the stage code 1, if the second word of the own instruction has not been read (FIFOC
(NT1 = 0), the process proceeds to the stage code 17, where the effective address is calculated and the instruction at the branch destination is controlled.

The bus control is performed in the second part (2-2) of the logical description shown in FIG. In the case of this transfer instruction, if the second word of the own instruction has not been read in the stage code 1, the bus access is prohibited. If the second word of the own instruction has been read in the stage code 1, or the instruction of the branch destination is read in the stage code 17.
In the case of a subroutine branch, go to stage code 2,
A long word size data write for stacking PC values is performed. In the stage code 2, an instruction read following the already read branch destination instruction is performed.

An effective address is calculated in the third part (2-3) of the logical description shown in FIG. In the case of this transfer instruction, if the second word of the own instruction has already been read by the stage code 1, or the stage code 17 outputs the EA extension part of the instruction code held in the read data buffer RDB to the internal bus GB. , In the address buffer AB. This content is automatically input to the incrementer INC, and increment (+ 2 / + 4) is performed. Further, an instruction to store the increment result in the program counter PC is issued. The stage code 3 instructs output of the PC value to the internal bus PCGB and storage of the increment result from the internal bus PCWB to the program counter PC.

In the fourth part (2-4) of the logical description shown in FIG. 26, transfer data (PC to be stacked) and registers are controlled. When the second word of the own instruction has been read in the stage code 1, or when the stage code 17
Instructs to read the contents of the stack pointer to the internal bus GB. Although not shown, the arithmetic and logic unit ALU is instructed to decrement (−4) by the arithmetic and logic unit ALU.

The result of the decrement in stage code 2 is
An instruction to output from arithmetic logic unit ALU to internal bus GB is provided. As a result, the decrement result is stored in the address buffer AB. In addition, storage from the internal bus WB to the stack pointer SP is instructed.

As described above, the address where the subroutine branch instruction exists is held as A1, and is decoded simultaneously with the instruction code. Using the address information and the signal IFMON indicating that the instruction read is being executed, the value to be transferred to the write data buffer WDB-OUT is PC, WDB-OUT.
M or WDB-S. Further, based on the address information, bit 1 of the output data is set to 1
(+2) is selected.

By such control, the execution can be realized without depending on the arrangement of the instructions and omitting the states of the instructions as appropriate.

It should be noted that the state cannot have an omissible state, and is executed without incrementing the program counter PC by utilizing the alternate operation of the arithmetic and logic unit ALU and the sub-arithmetic and logical unit ALUS. If there is an instruction that cannot be performed, the bus command issuance and the PC increment may be prohibited by referring to the state of the FIFOCNT2. For example, in FIG. 22 to FIG. 26, n in the second portion (1-2, 2-2)
op = 1, and in the third part (1-3, 2-3), in
It is sufficient to set cpc = 0. As a result, the instruction read amount becomes larger than the instruction execution (consumption) amount,
It is possible to prevent the instruction register (FIFO) 200 from overflowing or losing the contents of the program counter PC to be saved due to a subroutine branch instruction or the like.

From the above, the following functions and effects can be obtained. [1] Compared to the existing CPU, the data bus width is expanded without compromising compatibility, the speed of instruction reading is increased, and control of instruction execution is controlled by a state including an operation peculiar to the instruction and a state of the instruction. Divide into states that only perform reads,
The latter can be omitted (skipped). A part of the instruction execution speed is omitted (skipped) to balance the amount of instruction read and the amount of execution, and the instruction execution time is shortened to reduce the instruction execution time. Can be realized. Some instructions can be omitted (skipped), and the instructions can be omitted (skipped) as appropriate according to the number of instructions that have been read. Arbitrary instruction placement (relocatable)
This makes it easy to create a program and eliminates restrictions on development of a C compiler and the like.

[2] For an instruction having an instruction code of one word (basic unit length), such as an operation instruction between registers, which is executed in one state (unit time) and has no states that can be omitted (skipped), A plurality of arithmetic units are provided, and the arithmetic units are operated with a time difference shorter than the execution time of the resources for execution, so that a plurality of register operation instructions and the like are effectively executed simultaneously. Can be. It is possible to omit the instruction reading of one instruction that operates effectively simultaneously, balance the amount of instruction reading and the amount of execution, shorten the instruction execution time, and realize high speed. The instruction decoder must be compatible with all instructions (DE
C203) and one of the arithmetic units that operate effectively and simultaneously are exclusively controlled (SDEC204), thereby minimizing an increase in logic scale, and thus minimizing an increase in manufacturing cost. . By operating the arithmetic units with a time difference, it is not necessary to perform parallel processing, it is possible to easily cope with contention of general-purpose registers, and it is possible to suppress an increase in logic scale. Since the blocks of the instruction decoder and the execution unit EXEC corresponding to all the instructions can share most of the logic of the existing CPU, the design quality can be effectively used to improve the design quality and the development period. Can be shortened.

[3] An instruction code that generates only a control signal, such as a prefix code, can be skipped, and only a control signal can be generated at the time of skipping without using an instruction decoder. The execution time of
Higher speed can be realized.

[4] At the time of branch instruction or interrupt exception processing, the head instruction at the branch destination is read and execution is immediately started, so that responsiveness can be maintained and improved.

[5] The contents of bit 1 of the address bus IAB of the instruction code are stored in the instruction register together with the instruction code, and are simultaneously determined by the instruction decoder 203, thereby facilitating control and simplifying the decoding circuit. ,
An increase in the logical scale can be suppressed.

[6] The increment of the PC after the branch destination instruction is read is automatically switched between + 2 / + 4 by the incrementer INC according to the content of the branch destination address, thereby determining whether the branch destination is a multiple of four. Regardless, uniform processing can be performed, and an increase in logical scale can be suppressed.

[7] P is stored in the write data buffer WDB.
At the time of C increment, the contents of the PC before the increment are stored, and the write data buffer WDB is
By using the IFO structure, it is also possible to fix bit 1 of the write data buffer WDB to a logical value 1, and +2 can be easily realized. A PC value to be saved at the time of a subroutine branch instruction can be easily obtained. In addition, by having an arithmetic operation unit AU for adding the PC value to be saved and the displacement held in the write data buffer WDB and having a path directly input from the write data buffer WDB, preparation for the addressing mode relative to the program is performed. It is possible to increase the speed and, consequently, the processing speed of the instruction. Further, it is not necessary to have a prefetch counter and a program counter separately, and it is not necessary to further have a separate incrementer, so that an increase in logical scale can be suppressed.

[8] When there are a CPU having a wide address space and a CPU having a wide address space while maintaining compatibility, it is possible to realize high speed while maintaining compatibility in both. What is necessary is just to have necessary instructions and addressing modes as needed.

[0225]

[9] Since existing instructions are made executable and the order of internal operations and the like are made the same, the expansion margin in the future is not significantly impaired as compared with the existing CPU. For example, when it becomes possible to add a new instruction to an existing CPU, such a technique is applied to a C to which the present invention is applied.
It is believed that it can also be used for PU. If the instruction set compatibility is maintained, the existing C
The same instructions as the PU can be added. Also, if the additional instruction has a plurality of execution states, the additional instruction can be divided into a part that performs a specific operation and a state that can be omitted, and the latter can be omitted as necessary. At least, the reading of the instruction and the PC increment can be prohibited if necessary, and can be realized with a processing time equivalent to that of the existing CPU. If the additional instruction can be executed in one state, high speed can be realized by alternate operation between ALU and ALUS.

[10] By using the same instruction set as the existing CPU, development tools such as assembler, C compiler, simulator / debugger, so-called cross software can be shared. By sharing the cross software, the development environment can be quickly set up. In addition, resources required for development of the development environment can be suppressed, and unnecessary costs can be avoided for the user by using the existing development environment.

The invention made by the present inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the present invention can be applied to a completely new microcomputer besides maintaining compatibility. An instruction set, that is, an instruction type, an addressing mode type, a combination thereof, and the like can be arbitrarily set. The general-purpose register does not need to be commonly used for addresses and data, and may be partially or entirely dedicated to addresses or data. The data size of the general-purpose register can be arbitrarily set.

The type of the prefix code is not particularly limited.
The prefix code may include other control information in addition to the information indicating the long word. Further, the basic unit of the instruction code does not need to be limited to 16 bits, and may be an arbitrary bit width such as 8 bits or 32 bits. The width of the data bus is not limited to 32 bits, but may be 64 bits. The basic unit of the instruction may be quadruple instead of twice.

The capacity of the instruction register (FIFO) is not limited to three words. At least two words are required.
If the capacity is large, even if there is an instruction that does not have an omissible state, it is possible to balance the amount of instructions by increasing the state of the stored instruction to be omitted in the subsequent instruction execution. However, even if the capacity is increased, the read instruction becomes useless at the time of execution of the branch instruction. Therefore, it is better not to increase the amount of the instruction existing in the instruction register in a normal or steady state.

In the present invention, parallel processing is not performed. However, the present invention can be configured in combination with parallel processing. Some instructions may be processed in parallel. The number of arithmetic units and instruction decoders can be arbitrarily set. The other functional blocks of the single-chip microcomputer are not restricted at all.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer in the field of use as the background has been described. However, the present invention is not limited to this. Alternatively, a data processing device is also applicable, and the present invention can be applied at least to a data processing device that decodes and processes instructions and performs arithmetic processing.

[0233]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the internal data bus width (for the existing CPU) is made at least larger than the basic unit (word) of the instruction, and an instruction register for holding the read instruction (plural units) is provided. Provide a means to monitor the amount of instructions present in the registers,
According to the basic unit time (state) of execution, the state is divided into a state in which only control of instruction reading (and PC increment) is controlled, and a state including control of effective address calculation and data arithmetic processing. For example, even when the calculation of the effective address and the data transfer process operate over a plurality of states, the control itself is performed at once, and the actual operation is performed in a plurality of states (for example, by providing a delay to the control signal). The address calculation is performed in the first state, the read data is stored in the next state, and the operation for delaying the control signal (for example, storing the read data) overlaps with the next control operation (PC increment). The execution means is configured to be able to operate simultaneously. The state for controlling only the reading of the instruction can be omitted, and the state for controlling only the reading of the instruction can be omitted according to the amount existing in the instruction register (according to the instruction of the monitoring unit) (skip). Do).

Thus, by making the internal data bus width larger than the basic unit (word) of an instruction, the number of instructions to be read at one time can be made larger (than the existing CPU). When the instruction is read a number of times corresponding to the instruction code length of the own instruction (as in the case of the existing CPU) and skipping (skip) is not performed, the amount of instruction code of the executed instruction is By increasing the amount, the amount of the read instruction code can be accumulated, while the omission (skip) is performed and the instruction is not read, so that the amount of the instruction code of the executed own instruction and the amount of the read instruction Make the amount equal, maintain the amount of read instruction code, or reduce the amount of read instruction Since the amount of instruction codes can be reduced, the speed of instruction reading can be increased while keeping the amount of read instructions within a predetermined range (while balancing the amount of instruction reading and the amount of instruction execution). , The overall execution time can be reduced. Further, by automatically changing the states to be omitted (skipped), it is possible to cope with a change in instruction arrangement.

While maintaining compatibility at the object level,
When there is a CPU having a wide address space (large instruction set) and a CPU having a small address space (small instruction set), the CPU having a wide address space realizes the above-described high speed and has backward compatibility. In addition, the above-described high-speed operation can be similarly performed for an instruction that is also present in a CPU having a small address space. In other words, it is possible to increase the speed of a CPU having a wide address space and a CPU having a small address space by using the same method while maintaining compatibility at the object level. Both the advantages of maintaining compatibility at the object level and the advantage of enabling high speed can be enjoyed.

By using the same instruction set as the existing CPU, development tools such as assembler, C compiler, simulator / debugger, so-called cross software can be shared. By sharing the cross software, the development environment can be quickly set up.

[Brief description of the drawings]

FIG. 1 shows a CPU to which a data processing device according to the present invention is applied.
It is a block diagram of.

FIG. 2 is a block diagram of a single-chip microcomputer to which the data processing device according to the present invention is applied.

FIG. 3 is an explanatory diagram of a programming model related to a general-purpose register and a control register built in the CPU of FIG. 1;

FIG. 4 is an explanatory diagram of a programming model related to a general-purpose register and a control register built in another CPU.

FIG. 5 is an explanatory diagram of an example of a machine language instruction format in the CPU 2 of FIG. 1;

FIG. 6 is an explanatory diagram showing an example of a ROM.

FIG. 7 is an explanatory diagram of an addressing mode of a CPU.

FIG. 8: Transfer instruction “MOV.W@aa: 16, Rd”
6 is an operation timing chart of FIG.

FIG. 9 is an operation timing chart of a branch instruction “JMP $ aa: 24”.

FIG. 10 is a timing chart showing an example of a program execution timing by a CPU.

FIG. 11 is a timing chart illustrating the execution timing of a program having a different instruction arrangement address from that of FIG. 10;

FIG. 12 is a timing chart illustrating execution timings of programs having different instruction arrangement addresses from those of FIGS. 10 and 11;

FIG. 13 is a timing chart illustrating execution timings of programs having different instruction arrangement addresses from those of FIGS. 10 to 12;

FIG. 14 is a block diagram illustrating an example of an incrementer.

FIG. 15 is a block diagram illustrating an example of a write data buffer.

FIG. 16 is a block diagram showing an example of an arithmetic operation unit for calculating a program relative branch address.

FIG. 17 shows a subroutine branch instruction “JSR”
It is a timing chart which illustrates operation timing of "aa: 24".

FIG. 18 is a timing chart illustrating the execution timing of a program including a subroutine branch instruction.

FIG. 19 is a timing chart illustrating the execution timing of a program including a subroutine branch instruction.

FIG. 20 is a timing chart illustrating the execution timing of a program including another subroutine branch instruction.

FIG. 21 is a timing chart illustrating the execution timing of a program including another subroutine branch instruction.

FIG. 22 is an explanatory diagram exemplifying a part of the logical description of the decoding logic by the decoder for the transfer instruction of FIG.

23 is an explanatory diagram exemplifying a logical description of a part of decode logic by a decoder for the transfer instruction in FIG.

FIG. 24 is an explanatory diagram exemplifying a part of the logic description of the decoding logic by the decoder for the branch instruction / subroutine branch instruction in FIGS. 9 and 17 together with FIGS. 25 and 26;

FIG. 25 is an explanatory diagram exemplifying a part of the logic description of the decoding logic by the decoder for the branch instruction / subroutine branch instruction of FIGS. 9 and 17 together with FIGS. 24 and 26;

FIG. 26 is an explanatory diagram exemplifying a part of the logic description of the decoding logic by the decoder for the branch instruction / subroutine branch instruction of FIGS. 9 and 17 together with FIGS. 24 and 25;

[Explanation of symbols]

Reference Signs List 1 single-chip microcomputer 2 CPU 4 ROM 200 instruction register 202 instruction register controller 203 instruction decoder 204 sub-instruction decoder 205 register selector FIFOCNT1, FIFOCNT2 instruction code amount detection signal ER0 to ER7 general-purpose register PC program counter ALU arithmetic logic unit ALUS sub-arithmetic Logical operation unit AU arithmetic operation unit INC incrementer WDB write data buffer RDB read data buffer AB address buffer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 15/78 510 G06F 15/78 510G 510A

Claims (21)

[Claims] 1. A data processing device which reads an instruction code having a basic unit bit number and operates according to a basic unit time, comprising: a data bus having a bit number larger than the basic unit bit number; and a data bus connected to the data bus. An instruction code input means for inputting an instruction code from a data bus and capable of holding a plurality of instruction codes; a monitoring means for monitoring a state of the instruction code held in the instruction code holding means; Control means for decoding an instruction code obtained from the means and controlling an instruction execution operation, wherein the control means controls a part or all of the instruction execution operation based on the instruction code for each basic unit time. The operation is divided into two operations, a first operation for reading an instruction code and a second operation for performing other operations. When including bets, in response to said monitored state by the monitoring means, the data processing device, characterized in that to prevent the execution of the first operation. 2. The method according to claim 1, wherein the state of the instruction code is a retained amount of the instruction code. When the retained amount is large, execution of the first operation is suppressed, and when the retained amount is small, the first operation is executed. 2. The data processing device according to claim 1, wherein 3. The method according to claim 2, wherein the second operation, which has a data transfer instruction as an executable instruction and is controlled by the control means in response to an instruction code of the data transfer instruction, includes a transfer source address for generating a transfer source address. A generating operation and a transfer data storing operation for storing the transferred data, wherein the control unit performs the same basic unit for generating the control information for the transfer source address generating operation and the transfer data storing operation. 2. The data processing device according to claim 1, wherein the data is generated in time, and the transfer source address generating operation and the transfer data storing operation are executed in different basic unit times. 4. A read data buffer comprising: a register; a flag; a read data buffer; and an internal bus connected to the register and the read data buffer. 4. The data processing apparatus according to claim 3, wherein data is temporarily stored, and the stored data is output to said internal bus, and said register means is capable of storing the contents of said internal bus. 5. The read data buffer means for temporarily storing the transferred data, inspecting the stored data, and reflecting an inspection result on the flag means. 5. The data processing device according to 4. 6. A program counting means, wherein the control means reads or writes the program counting means as the first operation, and stores the transferred data in the register means or the flag means. 6. The data processing apparatus according to claim 4, wherein the data is reflected in parallel with the data. 7. A program counting means, comprising: an arithmetic operation means capable of incrementing the contents of the program counting means, wherein the value incremented by the arithmetic operation means is a first value corresponding to the size of the data bus. 2. The data processing device according to claim 1, wherein the value is a value selected from a value and a second value smaller than the first value according to the input value. 8. An instruction having a branch instruction as an executable instruction,
At the time of execution of the branch instruction, after reading the instruction code of the branch destination, the arithmetic operation means selects the value to be incremented to the first value or the second value according to the input value. 8. The data processing device according to claim 7, wherein 9. An instruction having an instruction that does not take a branch as an executable instruction, wherein when executing the instruction that does not take a branch, the arithmetic operation means sets the value to be incremented to the first value. 8. The method according to claim 7, wherein
Or the data processing device according to 8. 10. A data processing device which reads an instruction code having a basic unit bit number and operates according to a basic unit time, comprising: a data bus having a bit number larger than the basic unit bit number; and a data bus connected to the data bus. Command code input means for inputting an instruction code from a data bus and holding a plurality of instruction codes; first control means and second control means for decoding the instruction code and controlling an instruction execution operation; A first arithmetic and logic operation unit and a second arithmetic and logic operation unit whose operation phases are shifted from each other and operate in accordance with the basic unit time, wherein the first control unit controls a first arithmetic and logic unit And the second control means controls a second arithmetic and logic unit. The first control means includes a function of the second control means. The first control means and the second control means 2 Control means is operable to overlapping time, data processing apparatus, wherein the first control means performs a control of said second control means. 11. A monitor for monitoring a state of an instruction code stored in the instruction code storage unit and generating a control signal according to a monitoring result, wherein the instruction code storage unit stores the stored instruction code. Inspect the contents of the code, generate a detection signal when a predetermined instruction is detected, the first control means, when the detection signal is in a predetermined state, all or a part of the predetermined instruction code, 11. The data according to claim 10, wherein the data is supplied to the second control means, and when the control signal generated by the monitoring means is in a predetermined state, the control by the second control means is permitted. Processing equipment. 12. A computer system comprising: a program counting means; and an arithmetic operation means capable of incrementing the contents of the program counting means, wherein the arithmetic operation means has a phase different from that of the first arithmetic logic unit. 12. The data processing device according to claim 10, wherein the data processing device operates in synchronization with a unit time. 13. A data processing apparatus which operates by reading an instruction code composed of a basic unit bit number, comprising: a data bus having a bit number larger than the basic unit bit number; and a data bus connected to the data bus. Instruction code holding means capable of holding a plurality of instruction codes, monitoring the status of the instruction codes held in the instruction code holding means, decoding the instruction codes and executing the instructions Control means for controlling an operation, wherein the control means controls a read operation of an instruction code to be executed later, and when a predetermined instruction code is decoded, an instruction code according to a monitoring result by the monitoring means. A data processing device characterized in that the read amount of the data can be changed. 14. A branch instruction as an executable instruction, wherein the control means reads an instruction at a branch destination when decoding and executing an instruction code of the branch instruction, and reads the instruction at the branch destination. 14. The data processing apparatus according to claim 13, wherein the content of the instruction read at the branch destination is decoded when the content is input. 15. An arithmetic and logic unit having a first arithmetic and logic unit, a second arithmetic and logic unit, arithmetic operation means, register means, program counting means, read data buffer means, and address buffer means, and at least the address buffer means. A first internal bus connecting the program counting means, the register means, the first arithmetic and logic unit, the second arithmetic and logic unit, and the arithmetic operation means; and at least the address buffer means and the program count. Means, a second internal bus connecting the arithmetic operation means, at least a fourth internal bus connecting the read data buffer means and the register means, and connecting at least the program counting means and the arithmetic operation means And a third internal bus, wherein the register by the first bus is provided. Means for transferring to the second arithmetic and logic unit and transferring from the program count means to the address buffer means by the second bus in parallel. Data transferred from the read data buffer means to the register means by a bus and transfer from the arithmetic operation means to the program count means by the fourth bus in parallel. Processing equipment. 16. A fifth internal bus for coupling said register means, said first arithmetic and logic unit, and a second arithmetic and logic unit, wherein said fifth means is provided from said register means by said first bus. To the arithmetic and logic unit and another transfer from the register means to the first arithmetic and logic unit by the fifth bus can be performed in parallel. A transfer from the register means to the second arithmetic and logic unit by a bus and another transfer from the register means to the second arithmetic and logic unit by the fifth bus can be performed in parallel. The data processing device according to claim 15, wherein: 17. The first internal bus is further coupled to the read data buffer means, wherein the transfer from the register means to the first arithmetic and logic unit by the first bus; The transfer from the read data buffer means to the register means by the bus is detected, output from the register means to the first bus is inhibited, and the first data is transferred from the read data buffer to the first bus. 17. The data processing apparatus according to claim 15, further comprising control means for instructing output to a bus. 18. The second internal bus is further coupled to the write data buffer means, and when the data is transferred from the program count means to the address buffer by the second bus, the data is transferred to the write data buffer means. 18. The data processing apparatus according to claim 15, wherein the data processing is performed. 19. The write data buffer means having a lower bit correcting means, wherein the lower bit can be corrected by the correcting means when outputting the contents transferred from the program counting means. 19. The data processing device according to claim 18, wherein 20. An apparatus according to claim 1, further comprising another arithmetic operation means, wherein said another arithmetic operation means is coupled to said first internal bus and said write data buffer means. 20. The data processing device according to 18 or 19. 21. A plurality of register means, wherein the register means can use the entire area or an area divided into two to hold data, and has an address having a larger number of bits than one of the divided bits. And the same instruction code as another data processing device having a register corresponding to the one of the divided bits and including the instruction execution function of the other data processing device. And wherein an instruction using the entire register can be executed.
6. The data processing device according to 5.