JP2000357023A - Clock control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock control system for appropriately controlling whether or not a clock signal is to be supplied to a processor corresponding to the operating state of a device. SOLUTION: A device 1 for periodically accessing a system memory outputs a signal under Device operation showing a state under operating and a Device Request signal for requesting operation start to a device state monitoring circuit 3. On the other hand, the device state monitoring circuit 3 asserts an Enable signal during the operation of the device or asserts a Disable signal in the other case. When Stop Grant is asserted, a clock control circuit 5 asserts only STOPCLK for stopping only the internal clock of the processor and when the Stop Clock is asserted, PCLKSTP is asserted for stopping this STOPCLK and an external clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control system suitable for a low power consumption operable computer system including a processor having a cache memory for temporarily storing data in a system memory. In particular, a device that executes access to the system memory in response to a start command from the processor and a device that periodically generates access to the system memory after receiving the start command from the processor are implemented. The present invention also relates to a clock control system capable of appropriately controlling whether a clock signal is supplied to a processor in a computer system.

[0002]

2. Description of the Related Art In recent years, various personal computers (personal computers) called desktop type or notebook type have been developed. Many computers of this type have a function of partially stopping the clock inside the processor or temporarily stopping the clock supply from outside the processor for the purpose of reducing power consumption.

[0003] In particular, the reduction in power consumption when the clock supply to the processor is stopped is highly effective, and affects the operating time of a notebook-type personal computer that can be driven by a battery. This clock control is performed when the current job does not exist in the system and no input from an input device such as a keyboard occurs, but the detection and the clock stop control are dedicated software. This is done by a low power driver. This low power driver constantly monitors whether the system is currently idle or in operation, and if idle, activates the clock stop function.

A PLL (Ph) is internally provided in the processor.
There is an “ase locked loop” circuit, and this PLL circuit creates an internal clock. This internal clock operates at least several times the frequency of a clock supplied from the outside.

This PLL circuit requires several milliseconds to several tens of milliseconds after the external clock is supplied to the processor until the internal clock is oscillated stably. Therefore, when the clock to the processor is stopped by the stop control (processor clock stopped state), the operation is restarted by a key input or the like, and the system waits several milliseconds until the internal clock operates again stably.

[0006] By the way, it is natural that recent processors incorporate a cache memory, but there is also a problem due to the relationship between the above-mentioned clock stop and the cache memory built into the processor.

For example, when a memory access from an external device to an area cached in the processor occurs while the processor clock is stopped, a cache invalidation process (cache snoop) in the processor must be performed. No. However, the internal clock of the processor is stopped, and it is necessary to wait for a few ms until the internal clock operates stably by operating the external clock. Therefore, there is a problem that the performance is reduced as a result.

As a countermeasure against such a problem, there is a method in which a part of the internal clock of the processor is gated and stopped without stopping the clock supply to the processor.
According to this method, all circuits can be recovered in a few clocks from a state in which circuits in the processor are partially stopped. In this way, for example, when a device other than the processor periodically accesses the memory, the process of invalidating the cache memory inside the processor and the system memory access can be executed without waiting.

However, in this method, there are contradictory factors that the power consumption increases due to the increase in the number of operating parts and the battery driving time is shortened.

[0010] For this reason, the low power consumption driver controls the clock according to the rules shown in FIG. 5 after grasping the devices connected to the system and the operating states thereof. More specifically, when the system becomes idle and the clock of the processor can be stopped (that is, when it is determined that the system does not need to operate for a few milliseconds before re-operation), By issuing a processor clock stop instruction, a clock stop operation (STOPPCLOCK) of the processor is realized.

If there is a device that operates periodically, an instruction to partially stop the processor clock is issued to the processor to cause a transition to a partial clock stop operation (STOPGRANT) of the processor.

As described above, the STOPPCLOCK / STO
Regarding the PGRANT / normal supply state, the low power consumption driver, which is software, operates the device by directly switching the hardware setting after investigating the connection state of the device.

[0013]

When a device, such as a USB host controller (USB-HC), which may periodically perform a memory transfer, is connected to the system, the clock of the processor is controlled. When the suspension is performed, the recovery time from the suspension of the processor clock is longer than the regular access time of the USB-HC (the problem of the stable operation of the PLL). is there. Therefore,
In this case, the clock for the processor could not be stopped, and only STOPGRANT had to be used.

A mode for not operating is defined in the USB-HC. In this mode, the USB-HC does not perform memory access. However, when the low power consumption driver does not have a means for detecting this, even if the USB-HC does not perform the memory access, it cannot be determined that the system is idle. Therefore, regardless of the operating state, the clock to the processor cannot be stopped only by the presence of the USB-HC, and the STOPG
Only RANT had to be used.

Further, from the STOPPCLOCK state, ST
When transiting to the OPGRANT state, several hundred ms of switching time was wasted because the operating state was detected by software such as a low power consumption driver.

The present invention has been made in view of such circumstances, and has been described in connection with a device for executing access to a system memory in response to a start command from a processor, or after receiving a start command from a processor. It is an object of the present invention to provide a clock control system capable of appropriately controlling whether a clock signal is supplied to a processor even in a computer system in which a device for periodically generating access to a system memory is mounted.

[0017]

SUMMARY OF THE INVENTION To achieve the above-mentioned object, the present invention is directed to a device, such as some DMA devices, that accesses system memory in response to a boot command from a processor. Between receiving the start command from the processor and ending the access to the system memory, outputting an in-operation signal indicating that the access to the system memory is being performed. The CPU controls whether or not a clock signal is supplied to the processor by detecting with hardware, and therefore, has a low power consumption including a processor with a built-in cache memory for temporarily storing data in the system memory. A power-operable computer system that responds to a start command from the processor. The clock control system of the computer system devices to perform the access to the system memory is implemented, the device,
Between receiving a start command from the processor and ending access to the system memory, providing an active signal output unit that outputs an active signal indicating that an access operation to the system memory is being performed, A low-power-consumption operation request circuit for outputting a low-power-consumption operation request signal for causing the computer system to perform a low-power consumption operation; an in-operation signal from the device; and a low-power consumption operation request from the low-power consumption operation request circuit. A low power consumption control circuit for outputting a low power consumption control signal for controlling a low power consumption operation of the computer system according to a signal; and the processor according to a low power consumption control signal from the low power consumption control circuit. A clock control circuit for outputting a clock control signal for controlling whether or not a clock signal is supplied to the Characterized in that it Bei.

According to the present invention, a processor having a built-in cache memory for controlling whether or not a clock signal is supplied to a processor in accordance with an operation state of a device which accesses a system memory in response to a start command from the processor To prevent the clock control efficiency from deteriorating only due to the presence of these devices, and eliminate the overhead due to software control.

Further, according to the present invention, after receiving a start command from a processor such as a USB device,
During operation indicating that access to the system memory is being performed from the time when the device that regularly accesses the system memory is requested to access the system memory to the time when the access to the system memory is completed. A signal is output and the presence / absence of the output of the signal during operation is detected by hardware to control the supply / non-supply of the clock signal to the processor. For this purpose, the data in the system memory is temporarily stored. A low power consumption operable computer system having a processor with a built-in cache memory for executing a command to periodically generate access to the system memory after receiving a start command from the processor. In the clock control system of the computer system An in-operation signal that outputs an in-operation signal indicating that an access operation to the system memory is being performed during a period from when the device requests access to the system memory to when the access to the system memory is completed. An output means for outputting a low power consumption operation request signal for operating the computer system at low power consumption; a low power consumption operation request signal from the device and a low power consumption operation request signal from the device; A low power consumption control circuit that outputs a low power consumption control signal for controlling a low power consumption operation of the computer system in response to a low power consumption operation request signal; and a low power consumption control signal from the low power consumption control circuit. Clock for outputting a clock control signal for controlling whether or not a clock signal is supplied to the processor according to Characterized by comprising a control circuit.

According to the present invention, after the start command from the processor is received, the supply or non-supply of the clock signal to the processor is controlled in accordance with the operation state of the device for periodically generating access to the system memory. To prevent a computer system having a processor with a built-in cache memory from deteriorating clock control efficiency solely due to the presence of these devices, and to eliminate the overhead required for clock control due to software control. Realize.

[0021]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a clock control system according to an embodiment of the present invention.

In FIG. 1, a periodic access device 1 is a device that accesses a system memory periodically, for example, and causes a cache invalidation process inside a processor. This Periodic access device 1 is a Dedicated device that asserts “1”.
A device in-operation signal is output to the device state monitoring circuit 3 during the operation, and a device for requesting an operation start is output.
e Request signal is output to the device state monitoring circuit 3.

The Control register 2 is a group of control registers in the system, and is a Clock control enable for transmitting a clock control signal to the processor.
Signal is being output.

The device state monitoring circuit 3 is a circuit for monitoring the operation state of the device, which asserts the Enable signal when the device is operating and the Disable signal when the device is not operating. Here, only the Periodic access device 1 is connected to the input side of the device state monitoring circuit 3, but the system does not include the Periodic access device 1.
When there are a large number of riodic circuits and devices that operate for a long period of time, their device operation status is connected to the device state monitoring circuit 3 and placed under monitoring management.

The processor clock stop request generation circuit 4 periodically or by software
The clock stop request signal is asserted by the access.

The two control signals (Stop Grant Request,
Stop Clock Request is asserted in a matrix as shown in FIG. 2 by the circuit configuration shown in FIG. This clock control circuit 5 has Stop G
If rand is asserted, only STOPCLK is asserted, while if Stop Clock is asserted, both STOPCLK and PCLKSTP are asserted.

The processor clock receiving unit 6
After receiving the STOPCLK, the processor transitions to the processor-defined low power consumption mode.

The clock generator 7 is connected to a PC
When the LKSTOP signal is asserted, the clock supplied to the processor is stopped.

FIGS. 3 and 4 show STOPCLK and PC.
The timing of assertion and deassertion with LKSTOP is shown.

First, referring to FIG. 3, Stop Gr
When it is detected that the device that describes the timing of the ant cycle is not operating, Stop Gr
The ant Request is asserted ((1) in FIG. 3).

This Stop Grant Requests
Some time after t was asserted, this time STO
PCLK is asserted and the system stops at Stop Gra.
Transition to the nt cycle ((2) in FIG. 3).

In this state, the device requests operation start (D
device Request), and S
The top Grant Request is deasserted ((3) in FIG. 3).

Subsequently, the Stop Grant Re
In response to the quest deassertion, STPCLOCK is deasserted ((4) in FIG. 3).

In response to the STPCLOCK deassertion, the device starts operating (FIG. 3, (5)).

Then, since the device has started its operation, it deasserts Device Request ((6) in FIG. 3).

In this Stop Grant cycle,
Since PCLKSTOP is not asserted, the clock supply to the processor is not stopped.

Next, referring to FIG.
The timing of the ock cycle will be described.

When it is detected that the device is not operating, the Stop Clock Request is asserted ((1) in FIG. 4).

This Stop Clock Requests
Some time after t was asserted, this time STO
PCLK is asserted ((2) in FIG. 4).

Further, in response to the assertion of STOPCLK, PCLKSTOP is asserted, and the system operates at St.
The state transits to the op Clock state. That is, PC
When LKSTOP is asserted, the clock (P
CLK) stops ((3) in FIG. 4).

In this state, when the Device Request for starting the operation of the device is asserted, the Stop Clock Request is deasserted in response to the assertion ((4) in FIG. 4).

Subsequently, the Stop Clock Re
In response to the quest deassertion, PCLKSTP is deasserted ((5) in FIG. 4). At this time, the clock to the processor returns.

After deassertion of PCLKSTP, STCLK
OPCLK is deasserted ((6) in FIG. 4).

In response to the STOPCLK deassertion, the device starts operating (FIG. 4 (7)).

Then, since the device can start the operation, it deasserts Device Request ((8) in FIG. 4).

As described above, the device output from the device
The device status monitoring circuit 3 monitors the ce operation signal and the Device Request signal, and the clock control circuit 5 as hardware controls the clock supply to the processor according to the monitoring result of the device status monitoring circuit 3. Accordingly, appropriate clock control can be realized even if there is a device in which access is periodically generated in the system without generating overhead such as software control.

[0048]

As described in detail above, according to the present invention, the operating state of a device is monitored by hardware,
In order to control the clock supply to the processor, it was not possible to know in detail the operation state and the operation start state of the device, so there are devices in the system where access occurs periodically. This solves the problems of conventional clock control by software, such as poor clock control efficiency and increased overhead due to software control.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a clock control system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a signal input to a clock control circuit according to the embodiment;
Control signals (Stop Grant Requests)
FIG. 9 is a diagram illustrating a matrix of asserts of t, Stop Clock Request).

FIG. 3 is a timing chart of a stop grant cycle of the embodiment.

FIG. 4 is a timing chart of a Stop Clock cycle of the embodiment.

FIG. 5 is a diagram for explaining clock control by a conventional low power consumption driver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Periodic access device 2 ... Control register 3 ... Device state monitoring circuit 4 ... Processor clock stop request generation circuit 5 ... Clock control circuit 6 ... Processor clock receiving part 7 ... Clock generator

Claims (3)

[Claims] 1. A low power consumption operable computer system comprising a processor having a cache memory for temporarily storing data in a system memory, wherein the computer system is responsive to a start command from the processor. In a clock control system of a computer system in which a device for performing an access to a system memory is mounted, the system may be configured to receive a start command from the processor to end the access to the system memory. A low-power operation request for outputting a low-power operation request signal for causing the computer system to perform low-power operation; A circuit; an active signal from said device; A low power consumption control circuit that outputs a low power consumption control signal for controlling a low power consumption operation of the computer system according to a low power consumption operation request signal from the low power consumption operation request circuit; A clock control circuit, comprising: a clock control circuit that outputs a clock control signal for controlling whether a clock signal is supplied to the processor according to a low power consumption control signal from a control circuit. 2. A low power consumption operable computer system comprising a processor having a built-in cache memory for temporarily storing data in a system memory, wherein the computer system receives a start command from the processor. In a clock control system of a computer system in which a device for periodically generating access to the system memory is mounted, from a request for access to the system memory to the device to a termination of access to the system memory. Operating signal output means for outputting an operating signal indicating that an access operation to the system memory is being performed, and outputting a low power consumption operation request signal for causing the computer system to operate at low power consumption. Low power consumption operation request circuit and operation from the device A low power consumption control circuit for outputting a low power consumption control signal for controlling a low power consumption operation of the computer system in response to a signal and a low power consumption operation request signal from the low power consumption operation request circuit; A clock control system comprising: a clock control circuit that outputs a clock control signal for controlling whether a clock signal is supplied to the processor in accordance with a low power consumption control signal from the power consumption control circuit. 3. The low power consumption operation request circuit is driven and controlled to output the low power consumption operation request signal when the computer system is detected to be in an idle state. 3. The clock control system according to claim 1, wherein: