JP2000353387A - Semiconductor memory provided with back bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress needless current consumption by making quickly a back bias potential the prescribed setting potential at the time of increasing area of a chip and after supplying a power source. SOLUTION: When a back bias potential VBB is high and a detection signal 8 of a detecting circuit 1 is made H, an oscillator circuit 2 generates an oscillator signal 9, a VBB generating circuit 3 lowers VBB. An external power source VCC and a boosting potential VBT are connected to a power source terminal 10 of the VBB generating circuit through transfer gates 6, 7 respectively. VBTSEL is inputted to a Nch gate of a transfer gate 6, and VBTSEL is inputted to Pch gate through an inverter 5. VBTSEL is inputted to a Nch gate and a Pch gate of a transfer gate 7, a higher potential is connected always to the power source terminal 10 of the VBB generating circuit 3. Comparing with the VBB generating circuit using one kind of power source at the time of driving, VBB can be raised to the setting potential more quickly in this device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of controlling the substrate potential of a memory array section to GND for stable operation of the memory array section.
The present invention relates to a semiconductor memory device provided with a back bias circuit for holding a lower back bias potential (hereinafter, referred to as VBB).

[0002]

2. Description of the Related Art In a DRAM (Dynamic Random Access Memory), the substrate potential of the array portion is further lower than GND, mainly for the stable operation of the memory array portion (hereinafter simply referred to as the array portion). V
BB).

FIG. 12 is a block diagram of a circuit group for providing the VBB to the substrate. The external power supply potential VCC is input to a VBB detection circuit 101, an oscillator circuit 102, and a VBB generation circuit 103. VBB generated by the VBB generation circuit 103 is input to the detection circuit 101,
Is higher than the set potential, the detection circuit 101 sets the detection signal 104 to High (hereinafter, referred to as H).
When the detection signal 104 becomes H, the oscillator circuit 102 operates and outputs an oscillator signal 105. The VBB generation circuit 103 operates according to the oscillator signal 105, and lowers VBB. When VBB is lowered by the VBB generation circuit 103 and becomes lower than the set potential, the detection signal 104 becomes Low (hereinafter, referred to as L), and the operation of the oscillator circuit 102 and the operation of the VBB generation circuit 103 are stopped.

FIG. 13 is a circuit diagram showing a configuration of the detection circuit 101. VBB is input to the gate of the P-channel transistor row 107, and is connected in series with the P-channel transistor row 106 whose GND is connected to the gate. Node 1 between transistor array 106 and transistor array 107
09 is connected to the input terminal of the inverter 108.

In the detection circuit 101, when the back bias potential VBB rises and the potential at the node 109 exceeds the threshold value of the inverter 108, the output of the inverter 108 is inverted and the detection signal 104 becomes H. When VBB is lowered and the potential of the node 109 falls below the threshold value of the inverter 108, the output of the inverter 108 is inverted and the detection signal 104 becomes L. The VBB potential input to the gate of the transistor array 107 at the moment when the output of the inverter 108 is inverted is the set potential of VBB in the chip.

FIG. 14 is a circuit diagram showing a configuration of the oscillator circuit 102. The detection signal 104 is an odd-numbered NAND
Entered in column 110. The detection signal 104 is the NAND string 1
10 is input to one input terminal and the detection signal 104 becomes H, the oscillator signal 105 from the NAND string 110 is output.
Is output.

FIG. 15 is a circuit diagram showing a configuration of VBB generating circuit 103. FIG. 16 is a timing chart of each terminal and signal of the circuit shown in FIG. The oscillator signal 105 is input to the inverter 111. The output 117 of the inverter 111 is input to the inverter 112 and the capacitor 113. The other pole 119 of capacitor 113 is connected to the gate and drain of transistor 115 and to the drain of transistor 116. The output 118 of the inverter 112 is connected to the capacitor 114, and the other pole 120 of the capacitor 114 is input to the gate of the transistor 116. When the oscillator signal 105 is input, the VBB generation circuit 103
And the capacitor 114 alternately repeat the pumping operation to lower the potential of the terminal VBB to -VCC + VTP (VTP is the threshold value of the transistor 115).

[0008]

However, DRA
In M, all the power supplies used therein are DR
After the moment when power is turned on from outside (power on),
It is necessary to reach the set potential within a certain time. The back bias potential VBB must also satisfy this condition.

However, recently, as the chip area has increased,
The capacity added to the array substrate to maintain the substrate potential at VBB has increased. Since the absolute value of the power supply has also decreased, it has become difficult to make VBB reach the set potential within a certain time after power-on.

In order to satisfy the above conditions, the capability of the VBB generation circuit must be increased. In order to increase the performance of the VBB generating circuit, it is effective to increase the size of the circuit or increase the power supply for driving the circuit. But,
Enlarging the circuit requires a large area on the chip, is disadvantageous, and increases current consumption. One way to increase the power supply for driving the circuit is to use a step-up power supply VBT.
Use of the generator circuit causes a load on the circuit that generates the VBT, and increases current consumption.

In addition, once VBB reaches the set potential, when VBB is pulled again in a steady state thereafter, not so much capability is required in many cases. In this case, as in the case immediately after power-on, driving the VBB using a large circuit or a VBT having a high absolute value consumes useless current.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and even when the area of a chip is increased, the back bias potential can be quickly set to a predetermined potential after the power is turned on, and unnecessary current consumption can be achieved. It is an object of the present invention to provide a semiconductor memory device provided with a back bias circuit capable of suppressing the occurrence of a bias.

[0013]

A semiconductor memory device provided with a back bias circuit according to the present invention generates a back bias potential VBB and a boost bias potential VBT by inputting an external power supply VCC. A boosted potential generating circuit, the external power supply VCC and the boosted potential VBT
And a signal VBTSEL for controlling the selection means to select the external power supply VCC immediately after power-on and then select the boosted potential VBT. And a signal generation circuit that generates

In this case, the signal generation circuit includes a VBT
And a comparator for comparing VCC with VCC.
A pair of transfer gates to which an output signal of the comparator is input and connected between the back bias generation circuit, the boosted potential generation circuit, and an external power supply terminal, wherein the comparator satisfies VBT <VCC Only the transfer gate between the external power supply terminal and the back bias generation circuit is turned on, and only the transfer gate between the boosted potential generation circuit and the back bias generation circuit is turned on when VBT ≧ VCC. It can be configured as follows.

Further, the signal generation circuit includes a reference voltage VR.
A comparator for comparing EF with VBB, wherein the selection means receives the output signal of the comparator, and is connected between the back bias generation circuit, the boosted potential generation circuit, and an external power supply terminal. A pair of transfer gates, wherein the comparator turns on only the transfer gate between the external power supply terminal and the back bias generation circuit when VREF <VBB, and the boosted potential generation circuit when VREF ≧ VBB It is also possible to turn on only the transfer gate between the circuit and the back bias generation circuit.

According to another aspect of the present invention, there is provided a semiconductor memory device provided with a back bias circuit, a boosted potential generating circuit for receiving an external power supply VCC to generate a boosted potential VBT, and a back bias potential driven by the external power supply VCC. VBB
1 and a back bias potential VB driven by the boosted potential VBT.
A second back bias generation circuit for generating B2, and first and second output circuits for detecting a substrate potential VBB and outputting signals for controlling the first and second back bias generation circuits based on the detection result. A substrate potential detection circuit;
The second substrate potential detection circuit stops the operation of the second back bias generation circuit when the substrate potential VBB becomes lower than VBB2.

According to another aspect of the present invention, there is provided a semiconductor memory device including a back bias circuit, a boosted potential generating circuit receiving an external power supply VCC and generating a boosted potential VBT, and a back bias driving circuit driven by the external power supply VCC. Potential V
A first back bias generation circuit for generating BB1, a second back bias generation circuit for generating a back bias potential VBB2 driven by the boosted potential VBT,
A first and a second substrate potential detection circuit for detecting a substrate potential VBB and outputting a signal for controlling the first and second back bias generation circuits based on the detection result, respectively. Of the substrate potential VB
The operation of the first back bias generation circuit is stopped when B becomes lower than VBB1.

In the semiconductor memory device having these back bias circuits, it is preferable that the output VBB2 of the second back bias generation circuit is set to a potential at which the substrate potential VBB cannot reach a steady state.

In the present invention, the control of the back bias generation circuit is changed between immediately after power-on and in a steady state, so that the transistor size is not increased and the current consumption is suppressed as much as possible. VBB can reach the set potential immediately (within a certain time) immediately after power-on.

Specifically, the power supply for driving the VBB generating circuit is switched between immediately after power-on and in a steady state,
Change the circuit size of the BB generation circuit.

That is, an object of the present invention is to make a back bias reach a set potential within a certain time after power-on in a DRAM provided with a back bias circuit, and to further suppress the current as much as possible under such conditions. And a signal for selecting which power supply is used to drive the back bias generation circuit among the power supplies existing in the DRAM.
The capability of the back bias generation circuit is switched between a period until the voltage reaches the set potential and a period during the steady state.

According to the specification of the DRAM, the back bias (hereinafter referred to as VBB) potential must reach a set potential within a certain time after power-on. For this reason, the capability of a back bias generation circuit (hereinafter, VBB generation circuit) for generating a back bias must be improved. However, the VBB generation circuit increases the size of a transistor by pulling with a power supply having a larger absolute value. You can improve your ability without any. In DRAM,
Usually, there are an external power supply potential (hereinafter, referred to as VCC) and a boosted potential (hereinafter, referred to as VBT) created using the external power supply potential. In a steady state, the relationship of VBT> VCC holds, but since VBT is created by VCC,
After power-on of the DRAM, there is a certain period during which the relationship of VBT <VCC is satisfied. Taking advantage of this, in the present invention, two power supplies are compared, and a VBB generating circuit is driven by using a higher power supply, so that the VBB reaches the set potential more quickly. Things.

In the invention according to claim 2 of the present application, a signal called VBTSEL for switching the power supply for driving the VBB generating circuit is provided, and a circuit for generating VBTSEL is provided. The VBB generation circuit is driven, and after a predetermined time, the driving power supply of the VBB generation circuit is switched from VCC to VBT by VBTSEL, and the VBB generation circuit is driven using VBT. As a result, the VBB generation circuit can always be driven using a high power supply after power-on.

However, in the case of a DRAM in which the absolute value of VCC is considerably larger than the absolute value of VBB, the state after VBB reaches the set potential (steady state) is changed to VBT (> VCC) switched in FIG. Driving the VBB generation circuit by using the power supply is often too wasteful in current consumption because of its excessive capability.

Therefore, in the invention according to claim 3 of the present application, in the steady state, the method of driving using the VBT after power-on is switched to VCC again. As a result, current consumption can be suppressed.

In the invention according to claims 4 and 5 of the present application, VBB
Two generator circuits are arranged, one is driven by VCC, and the other
The table is driven by the VBT. In the present invention, the aforementioned claim 1
Although the area of the circuit increases as compared with the inventions of the third to third aspects, it is effective if there is sufficient area, and the VBB can reach the set potential more quickly after power-on.

Further, in the invention according to the fourth and fifth aspects, operating two VBB generating circuits having different power supplies in a steady state wastes current consumption because the capability is too large. Therefore, in the present invention, using the configuration of the circuit group shown in FIG. 6, in the steady state, the operation of one of the two VBB generating circuits is stopped, and only one operates. As a result, current consumption can be suppressed. However, in this case, which VBB generation circuit should stop operating differs depending on the magnitude of VCC.

That is, in the invention according to claim 4 of the present application, VC
The absolute value of C is considerably larger than the absolute value of VBB.
This is a case of a RAM, and in a steady state, the operation of the second VBB generating circuit driven by using the VBT is stopped. In this steady state, it is sufficient to operate the first VBB generating circuit driven by using VCC, and the operation is sufficient.
Operating the second VBB generation circuit driven by using the VBT also requires extra capacity. In this case, current consumption can be suppressed by stopping the operation of the VBB generation circuit driven using the VBT.

Conversely, in the case of a DRAM whose absolute value of VBB is close to the absolute value of VCC, the operation of the first VBB generating circuit driven using VCC is stopped. This is because, in a steady state, even if the VBB generating circuit is driven using VCC, almost no performance can be obtained in the circuit. In this case, current consumption can be reduced by stopping the operation of the first VBB generation circuit driven using VCC.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a semiconductor memory device provided with a back bias circuit according to a first embodiment of the present invention.

VBB is a back bias potential, VCC is an external power supply, and VBT is VC
This is a boosted potential boosted based on C. VBB is input to the detection circuit 1, and the detection signal 8 of the detection circuit 1 is input to the oscillator circuit 2. The oscillator signal 9 from the oscillator circuit 2 is input to the VBB generation circuit 3.

When VBB rises and the detection signal 8 of the detection circuit 1 becomes High (hereinafter referred to as H), the oscillator circuit 2 generates an oscillator signal 9, and the VBB generation circuit 3 lowers VBB. VCC and VBT are supplied to VBB generation circuit 3 via transfer gates 6 and 7, respectively.
Are connected to the power terminal 10. Transfer gate 6
VBTSEL is input to the Nch gate of
VBTSEL is input to the gate via the inverter 5. In the Nch gate of the transfer gate 7,
VBTSEL is input via the inverter 5 and Pch
VBTSEL is input to the gate.

FIG. 2 shows the VBTS in the first embodiment.
2 shows a circuit for generating EL. Element 11 is composed of VBT and VC
This is a comparator for comparing the magnitude of C. When the condition of VBT <VCC is satisfied, VBTSEL = Low (hereinafter, referred to as L) is output. When the condition of VBT> VCC is satisfied,
VBTSEL = H is output. When VBTSEL is L, the transfer gate 7 is turned on in FIG. 1, so VCC is input to the terminal 10. When VBTSEL is H, the transfer gate 6 is turned on. Is entered.

FIG. 3 shows VCC and VBT after power-on.
It is a graph which shows transition of a graph. Since VBT is a potential generated from VCC, VCC rises earlier after power-on. In FIG. 3, VBT and VCC
Is the same potential as t1, if before time t1, VBT <VCC, and VBTSEL = L
Becomes At a time after the time t1, VBT> VCC, and VBTSEL = H.

In the semiconductor memory device of the first embodiment configured as described above, comparing VCC and VBT, the higher potential is always connected to the power supply terminal 10 of the VBB generating circuit 3. For this reason, VBB is used by using only one type of power supply.
VBB is faster than when the generator is driven.
Can reach the set potential.

Next, a second embodiment of the present invention will be described. The semiconductor memory device including the back bias circuit of the present embodiment has a basic configuration similar to that of the first embodiment shown in FIG. 1, but differs from the first embodiment in a circuit for generating VBTSEL. FIG. 4 shows a circuit for generating the VBTSEL of the second embodiment.

In this embodiment, a potential VREF terminal to be compared with the VBB terminal is newly provided. The element 12 has VBB and V
This is a comparator for comparing the magnitude with REF, where VBB> V
If the condition of REF is satisfied, VBTSEL = L is output, and if the condition of VBB <VREF is satisfied, VBTS
EL = H is output.

When VBTSEL is L, the transfer gate 7 is turned on in FIG. 1 and VCC is input to the terminal 10. When VBTSEL is H, the transfer gate 6 is turned on. Is V
BT is input.

FIG. 5 shows VBB, VCC,
It is a graph which shows transition of VBT. In this second embodiment, VBT> VCC, and the time t
In 2, the value of VREF is set in advance so that the comparator 12 outputs VBTSEL = H. In FIG. 5, before the time t2, VREF <VBB, and therefore VBTSEL = L. In the time after time t2, VREF> VBB, and VBTSE
L = H.

Next, the operation of the second embodiment configured as described above will be described. In the first embodiment described above, after power-on, the VBB generation circuit could be driven using a power supply having an absolute value as large as possible. However, in the first embodiment, immediately after the time t1 in FIG.
L = H, and at this moment, VBT is consumed as a power supply of the VBB generation circuit and drops. Therefore, VBT <VC
C, and the output of the comparator 11 is again inverted. afterwards,
If VBT> VCC due to a decrease in VBB, the output of the comparator 11 is again inverted. By repeating this operation, around time t1, the output of the comparator 11 in FIG. 2 is frequently inverted, and as a result, current consumption increases. Further, since the power supply to be driven is switched in a short period of time, the operation of the VBB generating circuit becomes unstable.

To make up for the disadvantages of the first embodiment,
In the second embodiment, VBT> VCC, and after a while, the driving power supply of the VBB generating circuit is changed to VBT.
The circuit configuration is such that it switches to As a result, since the output of the comparator is not inverted frequently, unnecessary current consumption can be suppressed, and the driving power supply of the VBB generating circuit can be prevented from being frequently replaced.

However, in the second embodiment, since the time for switching the power supply for driving the VBB generation circuit from VCC to VBT becomes slower than in the first embodiment, VBB is set to the set potential after power-on. The time to reach is longer than in the first embodiment. However, even when the second embodiment is used, the VBB can reach the set potential more quickly than when the VBB generation circuit is driven using only one type of power supply.

Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing a semiconductor memory device provided with a back bias circuit according to the third embodiment. In FIG. 6, VBB is a back bias potential, VCC is an external power supply, and VBT is a boosted potential that is boosted by the boosted potential generating circuit 4 based on VCC.

In this embodiment, two VBB detection circuits 21 and
2 That is, the back bias potential VBB is input to the two detection circuits 21 and 22, and the detection signal 27 from the detection circuit 21 is input to the oscillator circuit 23. An oscillator signal 28 from the oscillator circuit 23 is input to VBB generation circuits 24 and 25. VCC is input to the power supply terminal 30 of one VBB generation circuit 24, and the other VB
The boosted potential VBT from the boosted potential generating circuit 26 is input to the power supply terminal 31 of the B generating circuit 25. The signal 29 output from the detection circuit 22 is input to the VBB generation circuit 25.

In the detection circuit 21, VBB> VBB
Under the condition of L1, the detection signal 27 becomes H. In the detection circuit 22, the detection signal 29 becomes H under the condition of VBB> VBBL2. At this time, VBBL1 <VBB
L2, and VBBL1 is the set potential of VBB.

FIG. 7 is a circuit diagram showing a configuration of VBB generating circuit 24. The oscillator signal 28 is output from the inverter 41
Is input to The output 47 of the inverter 41 is input to the inverter 42 and the capacitor 43. Capacitor 4
The other pole 49 of 3 is connected to the gate and drain of the transistor Tr45 and the drain of Tr46. The output of the inverter 42 is connected to one pole of the capacitor 44, and the other pole 50 of the capacitor 44 is connected to the gate of the transistor Tr46.

FIG. 8 is a circuit diagram showing a configuration of VBB generating circuit 25. The oscillator signal 28 and the detection signal 29 are
Input to NAND 51. The output of the NAND 51 is input to the inverter 52 and the capacitor 53. The other pole 59 of the capacitor 53 is connected to the gate and the drain of the transistor Tr55 and to the drain of the transistor Tr56. Inverter 5
2 is input to the capacitor 54 and the output of the capacitor 5
The other pole 60 of 4 is connected to the gate of the transistor Tr56.

Next, the operation of the circuits shown in FIGS. 6 to 8 will be described. FIG. 9 shows VBB, VBBL1 and VBB.
It is a graph which shows the potential relationship of BBL2. VBB = V
The time to become BBL2 is defined as t3. FIG. 10 is a timing chart of the present embodiment.
9 shows operations of main nodes in the circuits of FIG.

After the power is turned on, the signals 27 and 29 output from the detection circuits 21 and 22 both become H in a time until t3 when the condition of VBB> VBBL2 is satisfied. Since the signal 27 is H, the oscillator circuit 23 outputs
Is output. In the VBB generation circuit 24, the capacitors 43 and 44
Alternately repeat the pumping operation to lower the potential of the terminal VBB1 to -VCC + VTP (VTP is the threshold value of Tr45). In the VBB generation circuit 25,
Since the detection signal 29 is H, the VBB generation circuit 24
Similarly to the above, when the oscillator signal 28 is input, the capacitors 53 and 54 alternately repeat the pumping operation, and the potential of the terminal VBB2 is set to -VBT + VTP (V
TP is lowered to Tr59).

Next, VBB further decreases, and the time t3
, And when the condition of VBB <VBBL2 is satisfied, the signal 29 output from the detection circuit 22 becomes L. Signal 27 is H
Remains. When the signal 29 becomes L, the terminal 57 in FIG. 8 becomes H, the terminal 58 becomes L, and the terminal 60 becomes -VBT.
, The transistor Tr56 turns on, and the terminal 59
Becomes GND. At this time, the transistor Tr55 is turned off. VBB2 is disconnected from the terminal 59, and the operation of the VBB generation circuit 25 stops. Since the oscillator signal is continuously input to the terminal 28, the VBB generation circuit 24 continues to operate.

Next, the operation of the semiconductor memory device having the back bias circuit of the third embodiment configured as described above will be described. In this embodiment, the VBB generation circuit 2
4 and 25 are arranged and driven by different power supplies, so that VBB <VCC
The generation circuit 24 lowers VBB with a large current capability,
In the time when BT> VCC, the VBB generation circuit 2
5 lowers VBB with large current capability. as a result,
VBB can reach the set potential faster than in the case where only one of the VBB generation circuits exists.

However, in the case of a DRAM in which the absolute value of VCC is extremely large as compared with the absolute value of VBB, in a steady state, it is sometimes sufficient to operate the VBB generating circuit 24 driven by using VCC. . In this case, if the VBB generating circuit 25 driven by using the VBT is operated in addition to the circuit 24, the capability becomes too large,
Unnecessary current will be consumed.

In the present embodiment, VBBL2 is
Is set to a potential that cannot reach the steady state, in the steady state, the VBB generating circuit 25 driven using VBT does not operate, and only the VBB generating circuit 24 driven using VCC operates. In fact, at steady state, V
If only the BB generating circuit 24 operates and the capacity is sufficient, according to the present embodiment, the operation of the VBB generating circuit 25 is stopped, so that unnecessary current consumption can be suppressed.

Next, a fourth embodiment of the present invention will be described. FIG. 11 is a block diagram showing a semiconductor memory device provided with a back bias circuit according to the fourth embodiment. FIG. 11 shows a third embodiment in which VBT is connected to the power supply terminal 30 of the VBB generation circuit 24 and VCC is connected to the power supply terminal 31 of the VBB generation circuit 25 in FIG.

That is, in FIG. 11, the back bias potential VBB is input to the two detection circuits 71 and 72, and the detection signal 77 from the detection circuit 71 is input to the oscillator circuit 73. The oscillator signal 78 from the oscillator circuit 73 is input to the VBB generation circuits 74 and 75. VBT is input to a power supply terminal 80 of one VBB generation circuit 74, and a power supply terminal 81 of the other VBB generation circuit 75 is
VCC is input. The signal 79 output from the detection circuit 72 is input to the VBB generation circuit 75. Other configurations are the same as in the third embodiment.

The operation of the fourth embodiment is almost the same as the operation of the third embodiment. The difference is that, in the fourth embodiment, the operation of the VBB generation circuit 75 driven by using VCC is stopped and only the VBB generation circuit 74 driven by using VBT operates under the condition of VBB <VBBL2. is there.

In the fourth embodiment, as in the third embodiment, two VBB generation circuits are arranged and driven by different power supplies, so that the VBB generation circuit can be generated during the time when VBT <VCC. Circuit 75 has a large current capability and VBB
At the time when VBT> VCC,
The BB generation circuit 74 lowers VBB with a large current capability. As a result, the VBB can reach the set potential faster than in the case where only one of the VBB generation circuits exists.

However, in the case of a DRAM in which the absolute value of VBB in the steady state is close to the absolute value of VCC, in the steady state, the VBB generating circuit 25 of FIG. 6 operates between the node 49 and the node VBB1 shown in FIG. , The transistor Tr45 may not be turned on. this is,
The potential of the node 49 shown in FIG.
Because it is CC. In this case, the VBB generation circuit 25
Since almost no VBB can be pulled, operating this circuit consumes useless current, and the third embodiment cannot be applied.

However, in the fourth embodiment, VBBL
If 2 is set to a potential that cannot reach the normal state,
In the steady state, the VBB generating circuit 75 driven using VCC does not operate, and only the VBB generating circuit 74 driven using VBT operates, so that unnecessary current consumption can be suppressed.

A well-known example for switching the power supply for driving the VBB generating circuit is disclosed in JP-A-5-274876. In this known example, two VBB generation circuits are installed,
Each generating circuit is driven by an external power supply and an internal step-down power supply, respectively. Assuming that VBB rises above a set value during RAS active, a VBB generating circuit driven by an external power supply having a large absolute value is operated during RAS active, and a VBB generating circuit driven by an internal step-down power supply during periods other than RAS active Just working. As an effect, current consumption in periods other than RAS active can be suppressed.

In this known example, when RAS is active, V
Although the performance of the BB generation circuit is increased, the present invention is to increase the performance of the VBB generation circuit from power-on to a steady state. In the configuration, even in the known example,
Although two VBB generation circuits are provided and are common in the third and fourth embodiments of the present invention in this respect, the known example takes out a RAS active signal and switches the VBB generation circuit by this signal. According to the present invention, a signal obtained by monitoring VBB by a detection circuit is extracted, and the signal
This is for switching the B generation circuit. Therefore, the purpose, configuration, and operation of the present invention are different from those of the known art described in the above publication.

[0062]

As described above, according to the first to third aspects of the present invention, after the power of the semiconductor memory device is turned on,
The VBB generating circuit is driven by the external power supply VCC having a high potential, and after the boosted potential VBT exceeds VCC, the VBB generating circuit is driven by the VBT. Can be Further, the circuit scale does not increase and the current consumption does not increase.

According to the invention of claims 4 to 6, after the power supply of the semiconductor memory device is turned on, the two VBB generating circuits are driven to pull the substrate potential to a minus value, and in a steady state, VCC or VBT Drives only one VBB generating circuit, the back bias potential VBB can be set to the set potential immediately after power-on without increasing the circuit scale and current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor memory device provided with a back bias circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a VBTSEL signal generation circuit of the first embodiment.

FIG. 3 is a graph showing transitions of VCC and VBT in the first embodiment.

FIG. 4 is a circuit diagram showing a VBTSEL signal generation circuit of a semiconductor memory device including a back bias circuit according to a second embodiment of the present invention.

FIG. 5 shows VCC, VBT and VBB of the second embodiment.
It is a graph which shows transition of a graph.

FIG. 6 is a block diagram showing a semiconductor memory device having a back bias circuit according to a third embodiment of the present invention.

FIG. 7 is a transistor-level circuit diagram of a VBB generation circuit 24 according to the third embodiment.

FIG. 8 is a transistor-level circuit diagram of a VBB generation circuit 25 according to the third embodiment.

FIG. 9 shows VBB, VBBL1, and VB of the third embodiment.
FIG. 4 is a diagram illustrating a potential relationship of BL2.

FIG. 10 is a timing chart around a time t3 according to the third embodiment of the present invention.

FIG. 11 is a block diagram of a semiconductor memory device including a back bias circuit according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram showing a semiconductor memory device provided with a conventional back bias circuit.

FIG. 13 is a circuit diagram of a conventional detection circuit 101 at a transistor level.

FIG. 14 is a circuit diagram of a conventional oscillator circuit 102 at a transistor level.

FIG. 15 is a transistor-level circuit diagram of a conventional VBB generation circuit 103.

FIG. 16 is a timing chart showing the operation of the conventional device.

[Explanation of symbols]

1, 21, 22, 101: VBB detection circuit 2, 23, 102: Oscillator circuit 3, 24, 25, 103: VBB generation circuit 4, 26: Boost potential generation circuit 8, 27, 29, 104: Detection signal 9, 28, 105: Oscillator signal 6, 7: Transfer gate 11, 12: Comparator 5, 41, 42, 52, 108, 111, 112: Inverter 43, 44, 53, 54, 113, 114: Capacitor 45, 46, 55, 56, 106, 107, 115, 1
16: Pch transistor 51, 110: NAND

Claims (6)

[Claims] 1. A back bias generation circuit that generates a back bias potential VBB, a boosted potential generation circuit that receives an external power supply VCC to generate a boosted potential VBT, and drives one of the external power supply VCC and the boosted potential VBT Selection means for selectively inputting the potential as the potential to the back bias generation circuit; and signal generation for generating a signal VBTSEL for controlling the selection means so as to select the external power supply VCC immediately after turning on the power and then select the boosted potential VBT. A semiconductor memory device provided with a back bias circuit, comprising: 2. The signal generating circuit according to claim 1, wherein said signal generating circuit is a comparator for comparing VBT and VCC, and said selecting means receives said output signal of said comparator and receives said back bias generating circuit, said boosted potential generating circuit, and an external circuit. A pair of transfer gates respectively connected between the power supply terminal and the power supply terminal, wherein the comparator turns on only the transfer gate between the external power supply terminal and the back bias generation circuit when VBT <VCC, 2. The semiconductor memory device according to claim 1, wherein only a transfer gate between the boosted potential generation circuit and the back bias generation circuit is turned on when VBT ≧ VCC. 3. The signal generating circuit according to claim 1, wherein the signal generating circuit includes a reference voltage VREF.
And a comparator for comparing VBB with VBB, wherein the selecting means comprises:
A pair of transfer gates to which an output signal of the comparator is input and respectively connected between the back bias generation circuit, the boosted potential generation circuit, and an external power supply terminal, wherein the comparator has a relation of VREF <VBB Only the transfer gate between the external power supply terminal and the back bias generation circuit is turned on, and only the transfer gate between the boosted potential generation circuit and the back bias generation circuit is turned on when VREF ≧ VBB. A semiconductor memory device comprising the back bias circuit according to claim 1. 4. An external power supply VCC is input and the boosted potential V
A boosted potential generating circuit for generating BT, and the external power supply VC
A first back bias generating circuit driven by C to generate a back bias potential VBB1;
A second back bias generation circuit driven by BT to generate a back bias potential VBB2, and a substrate potential VB
B, and a first and a second substrate potential detection circuit for outputting signals for controlling the first and second back bias generation circuits based on the detection result, respectively.
The substrate potential VBB is VBB2
A semiconductor memory device comprising a back bias circuit, wherein the operation of the second back bias generation circuit is stopped when the voltage becomes lower. 5. An external power supply VCC is input and a boosted potential V
A boosted potential generating circuit for generating BT, and the external power supply VC
A first back bias generating circuit driven by C to generate a back bias potential VBB1;
A second back bias generation circuit driven by BT to generate a back bias potential VBB2, and a substrate potential VB
B, and a first and a second substrate potential detection circuit for outputting signals for controlling the first and second back bias generation circuits based on the detection result, respectively.
The substrate potential VBB is VBB1.
A semiconductor memory device comprising a back bias circuit, wherein the operation of the first back bias generation circuit is stopped when the voltage becomes lower. 6. The back bias circuit according to claim 4, wherein the output VBB2 of the second back bias generation circuit is set to a potential at which the substrate potential VBB cannot reach a steady state. Semiconductor memory device provided.