JP2000349853A - Data transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a memory cost by minimizing a capacity of a cache memory saving temporarily transmission data received by a receiver side transmitter in the case of transmitting data requiring a high capacity. SOLUTION: Transmitters 2, 6 at a transmitter side and a receiver side via a general public telephone network 1 are provided with NAND type (including AND type) flash memories 3, 3 to store transmission data D, D' as memory devices. The transmitter side transmits the transmission data D with a data quantity equal to a minimum delete unit of the NAND type (including AND type) flash memory 3 as one block of the transmission unit through a transmission line 5, the receiver side temporarily writes the received data D' sequentially to the NAND type (including AND type) flash memory 3 entirely according to its block address independently of the presence of an error, deletes only transmission data Der of a block where an error takes place to make the block idle, requests again the transmission data Der of the block, the transmitter side re-transmits the transmission data Der, and the receiver side writes the transmission data Der of the re-transmitted block to an idle block of the NAND type (including AND type) flash memory 3 according to a procedure under the control of each CPU 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of data transmission using a communication line such as a wireless telephone line of a portable terminal such as a PHS or a general public telephone line, and more particularly to a data transmission method relating to error correction of transmission data. About.

[0002]

2. Description of the Related Art Generally, wireless telephone lines such as PHS, general public telephone lines, ISDN (Integrated Services Digital
In data transmission using a full-duplex communication line capable of transmitting data in both directions at the same time, such as a network, a high level data transmission procedure (HDLC) is used.
Ontrol procedures) are performed according to a predetermined data transmission procedure (protocol).

In the above-described predetermined data transmission procedure, error detection data for determining whether or not transmission data is transmitted correctly, and a group of transmission data in which information for transmission control and the like are arbitrary information. Are added before and after as redundant information to form a transmission unit (frame).

For the error detection data, for example, a CRC (cyclic code) is calculated as error detection data on the transmission side and added to the end of the transmission data of each frame, and the CRC of the reception data is calculated and decoded on the reception side. A CRC method for determining whether the transmission data is correct or not (error detection) is typical.

[0005] The receiving side compares the error detection data calculated by itself based on the received data with the error detection data of the transmitting side added to the transmission data, thereby performing error detection. When it is determined that there is an error, the address information of the erroneous frame data is sent to the transmitting side (retransmission request), and the transmitting side transmits the frame data of that portion again in response to the retransmission request. I have.

In digital data transmission using the above communication line, the data amount is several tens KByte to several hundred Kbytes.
Data transmission units (frames) are tens to hundreds of Bytes, as they have been considered on the premise of e-mails and still images of about Byte.
As shown in FIG. 8 for explaining error correction when an error occurs, the SRA
After being stored in a cache memory 11 such as M or NOR type (including DINOR type) flash memory, it is stored in a large capacity storage element such as a NAND type (including AND type) flash memory 12.

What is necessary is that the flash memory 12 of a NAND type (including an AND type) having a low cost and a large capacity is generally used.
Although it is fast to read and write data sequentially from a certain address, random access takes a long time. Therefore, the transmission data must be sequentially stored in the order of the frame. However, if, for example, an error occurs in the data in the frame (N + 3) during the transmission, the frame (N + 3) is skipped, and a series of data frames are sent later according to a retransmission request from the receiving side to the transmitting side. , The retransmission frame (N + 3) is interrupted, so that the order of frames to be sequentially stored in the flash memory 12 of the receiving-side transmission device 6 is out of order. Therefore, as shown in FIG.
Since it is necessary to write to the flash memory 12 (including the AND type), the data is once stored in the cache memory 11 and then rearranged before writing.

[0008] The capacity of the cache memory 11 requires the amount of data sent from the transmission side between the time when the reception side transmission device 6 receives the error frame and the time when the frame is retransmitted. Furthermore, considering the case where frame errors occur intermittently, more capacity is required. If errors occur frequently and the cache memory capacity becomes insufficient, sequential data will be sent to the sender until an error frame is received. This would require the transmission to be interrupted. In this regard, assuming that one frame is 128 bytes on a 64 Kbps transmission path, the cache memory capacity generally required for one error frame is about 20 frames (2 KB).
yte) is needed more.

[0009]

[Problems to be Solved by the Invention] Several Mbyt of music software etc.
When transmitting a data amount of e to several tens of Mbytes, the capacity of the cache memory 11 of the receiving-side transmission device 6 (both in the case of a system in which the transmitting side and the receiving side transmit data bidirectionally) should be as small as possible. Desirable in cost.

However, as described above, the NAND type (including the AND type) flash memory 12 requires one block (generally 16 KB) to rewrite the written data.
The memory cell must be erased and rewritten anew in units of yte), and random writing is slow while sequential writing is fast.
Therefore, if an error frame occurs and is directly written to the NAND flash memory (including the AND type) on the receiving side, the error frame cannot be rewritten later. The transmitted transmission data is separately saved in the cache memory 11 until the correct data corresponding to the error frame is retransmitted and received, and when the data is successfully received, the data is transferred to the NAND type (including the AND type) flash memory 12 in the address order. It will be written. Thus, a large-capacity cache memory 11 for saving the received data frame until a correct data frame corresponding to the error frame is retransmitted from the transmission side is required.

The present invention has been made in view of the above circumstances, and when transmitting large-capacity data such as music data using a communication line such as a PHS portable terminal, the receiving-side transmission device 6
The present invention provides a data transmission method including a new error correction procedure capable of minimizing the capacity of the cache memory 11 for temporarily saving the transmission data received in step (1) and suppressing the loading cost.

[0012]

According to the present invention, there are provided (1) transmission apparatuses 2 and 6 on the transmission side and the reception side shown in FIG.
Of the NAND type (AN
D-type flash memory 3 (including D-type), and the transmission-side transmission device 2 stores transmission data D stored in the NAND-type (including AND-type) flash memory 3 in the NAND format.
Data (including the AND type) in the flash memory 3 is transmitted to the receiving-side transmission device 6 as one block of the transmission unit as the minimum unit of erasing, and the receiving-side transmission device 6 transmits all the received data D 'in block address units. In the NAND
Type (including the AND type) flash memory 3, the transmission error is detected, and the transmission data D ′ written in the NAND type (including the AND type) flash memory 3 is used to determine the block in which the error has occurred. Only the transmission data Der is erased to make an empty block, and the transmission data Der of the block in which the error has occurred is requested to be retransmitted to the transmission side transmission device 2. The transmission side transmission device 2 generates the error in response to the retransmission request. Only the transmission data Der of the retransmitted block is retransmitted, and the receiving-side transmission device 6 writes the retransmission transmission data Der of the block into the empty block of the NAND type (including the AND type) flash memory 3 according to a procedure. The above problem is solved by the data transmission method described above.

(2) A NAND type flash memory 3 (including an AND type) is provided in a memory device for storing transmission data of the transmission devices 2 and 6 on the transmission side and the reception side shown in FIG.
3 and the transmission-side transmission device 6 has its NAND type (AND
The transmission data D stored in the flash memory 3 (including the flash memory 3) is converted to a data amount equivalent to the minimum erasing unit of the NAND type flash memory 3 (including the AND flash memory) by the transmission unit 1
The data is transmitted to the receiving-side transmission device 6 as a block, and the receiving-side transmission device 6 temporarily writes all the received data D 'in the NAND flash memory 3 (including the AND type) sequentially in block address units, and then transmits the data to the transmission side. The device 2 detects a transmission error by the error detecting means and retransmits the transmission data Der of the block in which the error has occurred to the reception side transmission device 6, and then the reception side transmission device 6 transmits the retransmitted transmission data Der.
In which the data of the NAND type (including AND type) flash memory 3 indicated by the block address attached to the transmission data is erased to make it an empty block, and then the retransmitted transmission data Der is written into the empty block. The above problem is solved by a data transmission method characterized by following.

The flash memory, which is a component of the transmission device (terminal device) for realizing the data transmission method of the present invention, is a conventional EPROM (Erasable and Pro
grammable Read Only Memory) or EEPROM (Electr
This is a type of non-volatile memory LSI, which is the same as an erasable programmable read only memory (IC), and has a block erase function. For example, a group of memory cells having consecutive addresses is stored in one page (512 bytes / byte).
This is a memory device that forms one block with 32 pages = 16 Kbytes, and is based on reading / writing in page units and erasing in block units. Generally, there are two types of flash memories, NOR type and NAND type (including AND type). NAND type (including AND type) is not suitable for random access but is inexpensive.
It is suitable for storing data to be sequentially written / read, such as for large-capacity file storage such as a memory card. On the other hand, the NOR type has a configuration close to that of an SRAM and is capable of high-speed random access by assigning an address to one byte or one word, and is used for high-speed working storage such as for downloading a program, but is generally expensive.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION When transmitting a large amount of data such as music software from a transmitting side transmitting apparatus to a receiving side transmitting apparatus using a general public telephone network, an SR when a transmission error occurs.
Two embodiments of a data transmission method according to the present invention that can minimize a cache memory such as an AM will be described with reference to the drawings.

FIG. 1 is a block diagram of a transmission system for realizing a data transmission method according to claim 1 of the present invention.
FIG. 2 is a block diagram of a transmission system for realizing a data transmission method according to claim 2 of the present invention. FIG. 3 is an example of a format of transmission data according to the present invention. 4 to 7 are diagrams for explaining an error processing procedure in the data transmission method according to the present invention.

First, as shown in FIG. 1, in a system for transmitting data from a transmitting side transmitting apparatus 2 to a receiving side transmitting apparatus 6 via a general public telephone network 1 of a full duplex communication line,
A memory device for storing transmission data D or D 'of each of the transmission devices 2 and 6 on the transmission side and the reception side includes NAND type (including AND type) flash memories 3 and 3 (equivalent). Reference numeral 2 denotes the transmission data D stored in the NAND flash memory 3 (including the AND flash memory).
4 is transmitted as a block of a transmission unit to the receiving-side transmission device 6 via the transmission-side line 5, and the receiving-side transmission device 6 transmits the received data D 'in FIG.
As shown in FIG. 3, the NAND type (A
The flash memory 3 (including the ND type) is temporarily written and transmission errors are detected.
Transmission data D 'of the block in which the error has occurred among the transmission data D' written in the flash memory 3 (including the D type).
er is erased to make it an empty block, and the transmission data Der of the block in which the error has occurred is transmitted to the transmission side transmission device 2.
The transmission line 2 retransmits the transmission data Der of the block in which the error has occurred in response to the retransmission request, and the reception side transmission device 6 transmits the retransmitted block. Data Der is transferred to the NAND type (AN
Each of the CPUs 9 on the transmission side and the reception side is controlled so as to follow the procedure of writing to the empty block location of the flash memory 3 (including the D type).

That is, as shown in FIGS. 4 to 7, the block in which an error has occurred in the transmission data D 'once written in the NAND type (including the AND type) flash memory 3 of the receiving side transmission device 6. Only the data Der of (N + 3) is deleted to make it an empty block, and the transmission data of the block (N + 3) in which the error has occurred is requested to be retransmitted to the transmission device 2 (see FIGS. 4 and 5). The side transmission device 2 responds to the request and the block (N
+3) transmission data (see FIG. 6), and the receiving-side transmission device 6 stores the error-free reception data Dco of the retransmitted block (N + 3) in the NAND flash memory 3 (including the AND type). It is controlled by the CPU 9 so as to follow the procedure of writing to the block location (see FIG. 7).

According to the above procedure, the cache memory capacity (100) as the data buffer 10 which only saves the error-free received data Dco retransmitted during the erasing of the transmission data Der of the block in which the error is detected.
The transmission data can be efficiently and sequentially stored in the NAND type flash memory 3 (including the AND type) according to the address, thereby minimizing the capacity of the cache memory.

Next, in the data transmission method according to the second aspect of the present invention, the difference between whether the transmission error detection means is performed on the reception side or the transmission side, and the transmission data includes the transmission side error detection data The data transmission method is the same as that described above except that it differs depending on whether or not the data transmission method is used.

That is, assuming that a communication line for which full duplex is secured (whether wireless or wired), as shown in FIG. The transmission devices 2 and 6 include NAND flash memories 3 and 3 in the memory device for storing the transmission data of the transmission devices 2 and 6.
The transmission data D stored in the flash memory 3 (including the ND type) is converted into a block of the transmission unit with a data amount equivalent to the minimum erasing unit of the NAND type flash memory 3 (including the AND type). The transmission device 6 on the receiving side sequentially writes all the received data D 'in the NAND type (including the AND type) flash memory 3 sequentially in block address units. The transmission data Der of the block in which the error has occurred is retransmitted to the reception-side transmission device 6 after being detected by the error detection means described later, and then the reception-side transmission device 6 transmits the retransmitted transmission data Der to the block address attached to the transmission data. The data in the NAND type (including the AND type) flash memory 3 shown in FIG. The transmission and reception CPUs 9 are controlled so as to follow the procedure of writing the transmission data Der thus obtained.

Here, the error detecting means performed by the transmitting side transmission device 2 can be realized by the following procedure. That is, the transmission-side transmission device 2 calculates transmission-side error detection data (ERDt: for example, a CRC error code (1 Byte)) by a predetermined algorithm, stores it in a memory device (for example, a memory in the CPU 9) (not shown), and The transmission data D is added to the terminal adapter (abbreviated) in a format in which the redundancy is reduced without adding the synchronization signal (SYNC) and the block address (8 bytes) as shown in FIG. 3 but without adding the transmission side error detection data (ERDt). TA) 8 to the receiving-side transmission device 6 via the sending-side line 5, and the receiving-side transmission device 6 converts the received reception data D ′ into reception-side error detection data (ERD).
r) is calculated by the same algorithm as that on the transmission side, and the result is returned at least once or more to the transmission side transmission apparatus 2 on the return side line 7, and the transmission side transmission apparatus 2 returns the received reception side error detection data (ERDr). ) And the transmission-side error detection data (ERDt) stored in the memory device are sequentially compared. If there is the same data, it is determined that there is no transmission error, and if there is no same data, it is determined that there is a transmission error. Device 2
Is controlled by the CPU 9. Note that the numbers (FO to F127) in the frame in FIG. 3 are frame numbers of the transmission data D, and one frame is 128 bytes, and 128 frames constitute one block (16392 bytes) of a transmission unit. It is also assumed that 1 byte of error detection data (ERDt, ERDr) is generated for 128 bytes.

According to the above data transmission method, there is no need for a retransmission request from the receiving side to the transmitting side, and redundancy can be reduced and transmission can be performed efficiently.

It should be noted that the above-described data transmission method according to the present invention is particularly effective when the electric field strength is stable in a wireless telephone line such as a PHS terminal or a portable telephone. In other words, transmission errors in a wireless telephone line such as a PHS in such a state usually occur on a large scale for several seconds, so that the transmission data is divided into small pieces like data transmission by a conventional modem. The transmission method according to the present invention, which collectively transmits data in units of blocks, can perform transmission more efficiently than the transmission procedure. Furthermore, when data is streamed for a long time like data of music software, there is an advantage that the redundancy is reduced and the transmission efficiency is increased.

On the other hand, when data is transmitted using a PHS terminal or the like, a small-scale transmission error for a short time sometimes occurs only when the electric field strength is weak. The transmission method is not suitable for use (it is wasteful to correct a slight error in block units), and it is preferable to reduce the transmission unit as in data transmission by a conventional modem. When connecting to a data internet or the like, data communication itself is performed intermittently, and the computer itself performs multiple task processes in parallel, so the data transmission unit is finely divided and other processes are performed. It is preferable to secure

Therefore, by combining the conventional data transmission method with the data transmission method of the present invention, first,
The data transmission unit is finely divided and the transmission state is checked while the data transmission is started by the normal HDCL procedure. If the transmission state is found to be stable, it is automatically switched to the data transmission in block units according to the present invention. It is believed that a multi-procedure transmission method can be a more efficient data transmission method.

[0027]

According to the data transmission method of the present invention, the capacity of the cache memory for temporarily saving the transmission data can be minimized, so that the loading cost can be reduced and the transmission efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a transmission system for implementing a data transmission method according to claim 1 of the present invention.

FIG. 2 is a block diagram of a transmission system for realizing a data transmission method according to claim 2 of the present invention.

FIG. 3 is a format example of transmission data according to the present invention.

FIG. 4 is a diagram illustrating a stage of once writing all blocks in an error handling procedure of data transmission in the data transmission method according to the present invention.

FIG. 5 is a diagram for explaining a stage of an erasure / retransmission request.

FIG. 6 is a diagram for explaining a retransmission stage.

FIG. 7 is a diagram illustrating a step of writing a block of retransmitted transmission data.

FIG. 8 is a diagram illustrating error correction when an error occurs in a conventional data transmission method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 General public telephone network 2 Transmission side transmission device 3 Memory device (NAND type (including AND type) flash memory) 5 Transmission side line 6 Receiving side transmission device 7 Return side line 8 Terminal adapter (TA) 9 CPU 10 Data buffer ( Cache memory with minimized capacity 11 Cache memory 12 NAND type (including AND type) flash memory SYNC Synchronization signal D Transmission data D 'Reception data Der Transmission data of block in which error occurred Dco Retransmission reception data without error ERDt Error detection data on the sending side (CRC error code) ERDr Error detection data on the receiving side (CRC error code)

Claims (2)

[Claims] 1. A memory device for storing transmission data of each transmission device on a transmission side and a reception side includes a NAND type (including an AND type) flash memory.
The transmission data stored in the AND type (including the AND type) flash memory is transferred to the NAND type (including the AND type).
The data amount equivalent to the minimum unit of erasure of the flash memory is transmitted to the receiving-side transmission device as one block of the transmission unit, and the receiving-side transmission device sequentially receives all the received data in block address units in the NAND type (including the AND type). Once writing to flash memory and detecting transmission error,
Next, of the transmission data written in the NAND type (including the AND type) flash memory, only the transmission data of the block in which an error has occurred is erased to make it an empty block, and the error has occurred in the transmission side transmission device. In response to the retransmission request, the transmission device on the transmission side retransmits only the transmission data of the block in which the error has occurred, and the transmission device on the reception side transmits the transmission data of the retransmitted block to the NAND type ( A data transmission method according to a procedure of writing to the empty block of a flash memory (including an AND type). 2. A memory device for storing transmission data of each transmission device on a transmission side and a reception side is provided with a NAND type (including an AND type) flash memory, and the transmission side transmission device has an N-type flash memory.
The transmission data stored in the AND type (including the AND type) flash memory is transferred to the NAND type (including the AND type).
The same amount of data as the minimum unit of erasure of the flash memory is transmitted as one block of the transmission unit to the receiving-side transmission device, and the receiving-side transmission device sequentially transmits all the received data to the NAND flash (including the AND flash) in block address units. The data is temporarily written into the memory, and then the transmission device detects a transmission error by the error detecting means, and retransmits the transmission data of the block in which the error has occurred to the reception device. Then, the reception device transmits the retransmitted transmission data. Data is represented by a NAND type (AND) indicated by a block address attached to the transmission data.
A data transmission method comprising erasing data of a flash memory (including a type) into an empty block, and then writing the retransmitted transmission data in the empty block.