CN116701047A - Error correction decoding data generation method and device, electronic equipment and readable storage medium - Google Patents
Error correction decoding data generation method and device, electronic equipment and readable storage medium Download PDFInfo
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- G—PHYSICS
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
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Abstract
The embodiment of the invention provides an error correction decoding data generation method, an error correction decoding data generation device, electronic equipment and a computer readable storage medium. The method comprises the following steps: reading storage data from the flash memory particles to a first internal cache based on the flash memory bus timing module; performing type analysis on the stored data to obtain data type information; under the condition that the data type information characterizes the stored data as soft data information, the stored data is read from the first internal cache and is subjected to soft decoding to obtain error correction decoding data; under the condition that the data type information characterizes the stored data as original data information, the stored data is read from the first internal cache to the system cache based on the data transmission control module, and the stored data in the system cache is operated to obtain soft data information. According to the scheme provided by the embodiment of the invention, two different error correction decoding data generation modes can be compatible, different types of memories can be well adapted, and convenience is brought to users.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a method and apparatus for generating error correction decoding data, an electronic device, and a computer readable storage medium.
Background
The flash memory may have bad blocks or ring bits when shipped, and life loss and error bit increase characteristics may also occur with the increase of the service time, so that the data needs to be protected by using an error correction algorithm. When writing data, executing an error correction algorithm to encode, adding check information, and writing the original data and the check information into the flash memory; when the data is read, the original data and the check information are read from the flash memory, an error correction algorithm is executed for decoding, if the decoding is passed, the original data is correct, otherwise, the original data may have an error condition. The error correction decoding process can be divided into hard decoding and soft decoding, and soft decoding has strong error correction capability and requires input data with a specific format, which is called soft data information. At present, two types of flash memories exist in the market, one type can directly read soft data information from the flash memory through a command, the other type can only provide original data information, and the soft data information can be generated after specific operation is carried out on the original data information; however, there is no related flash memory controller in the market at present that can simultaneously satisfy the data generation modes of the above two types of flash memories, so that the two different data generation modes cannot be compatible.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art.
Therefore, the invention provides the error correction decoding data generation method which can be compatible with two different error correction decoding data generation modes, is well suitable for different types of memories, and brings convenience for users.
The invention also provides a device applying the error correction decoding data generation method.
The invention also provides an electronic device applying the error correction decoding data generation method.
The invention also provides a computer readable storage medium applying the error correction decoding data generation method.
An embodiment of the present invention provides an error correction decoding data generating method applied to a memory controller, where the memory controller includes a flash memory bus timing module, a first internal buffer, a system buffer, an error correction control module and a data transmission control module, and the method includes:
reading storage data from flash memory particles to the first internal cache based on the flash memory bus timing module;
performing type analysis on the stored data to obtain data type information;
reading the stored data from the first internal cache based on the error correction control module and performing soft decoding on the stored data to obtain error correction decoded data under the condition that the data type information characterizes the stored data as soft data information;
and under the condition that the data type information characterizes the stored data as original data information, reading the stored data from the first internal cache based on the data transmission control module to the system cache, performing operation processing on the stored data in the system cache to obtain the soft data information, transferring the soft data information to the first internal cache, reading the soft data information from the first internal cache based on the error correction control module, and performing soft decoding on the soft data information to obtain the error correction decoding data.
According to some embodiments of the invention, the memory controller further includes a second internal buffer, and after obtaining the error correction decoded data, the method further includes:
the error correction decoding data are transferred to the second internal cache;
and reading the error correction decoding data from the second internal buffer memory based on the data transmission control module to the system buffer memory.
According to some embodiments of the invention, the reading the stored data from the first internal cache based on the error correction control module includes:
and under the condition that the amount of the cached data in the first internal cache meets a first preset condition, reading the stored data from the first internal cache based on the error correction control module.
According to some embodiments of the invention, the reading the soft data information from the first internal buffer based on the error correction control module includes:
and under the condition that the buffer data amount in the first internal buffer memory meets a second preset condition, reading the soft data information from the first internal buffer memory based on the error correction control module.
According to some embodiments of the invention, the transferring the soft data information to the first internal cache includes:
and transmitting the soft data information from the system cache to the first internal cache based on a data transmission control module.
According to some embodiments of the invention, the memory controller further comprises a protocol interface control module and a processor, the method further comprises, before reading the memory data from the flash memory granule to the first internal cache based on the flash bus timing module:
receiving an operation instruction sent by an external host terminal based on the protocol interface control module and analyzing the operation instruction to obtain operation analysis information;
the operation analysis information is transferred to the system cache;
and reading and executing operation analysis information in the system cache based on the processor.
According to some embodiments of the invention, after the data transmission control module reads the error correction decoded data from the second internal buffer to the system buffer, the method further includes:
and reading the error correction decoding data from the system cache based on the processor, and performing decoding operation according to the error correction decoding data.
An apparatus for generating error correction decoded data according to an embodiment of a second aspect of the present invention is applied to a memory controller, where the memory controller includes a flash memory bus timing module, a first internal buffer, a system buffer, an error correction control module, and a data transmission control module, and the apparatus includes:
the first processing module is used for reading storage data from the flash memory particles to the first internal cache based on the flash memory bus time sequence module;
the second processing module is used for carrying out type analysis on the stored data to obtain data type information;
the third processing module is used for reading the stored data from the first internal cache based on the error correction control module and performing soft decoding on the stored data to obtain error correction decoded data when the data type information characterizes the stored data as soft data information;
and the fourth processing module is used for reading the stored data from the first internal cache based on the data transmission control module to the system cache under the condition that the data type information characterizes the stored data as original data information, performing operation processing on the stored data in the system cache to obtain the soft data information, transferring the soft data information to the first internal cache, reading the soft data information from the first internal cache based on the error correction control module, and performing soft decoding on the soft data information to obtain the error correction decoded data.
An electronic device according to an embodiment of a third aspect of the present invention includes: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the error correction decoding data generation method as described above when executing the computer program.
A computer-readable storage medium according to an embodiment of the fourth aspect of the present invention stores computer-executable instructions that, when executed by a control processor, implement the error correction decoded data generation method as described above.
The error correction decoding data generation method according to the embodiment of the invention has at least the following beneficial effects: in the process of generating error correction decoding data, reading storage data from flash memory particles to a first internal cache based on a flash memory bus time sequence module; then, carrying out type analysis processing on the stored data to obtain data type information; under the condition that the data type information characterizes the stored data as soft data information, reading the stored data from a first internal cache based on an error correction control module and performing soft decoding on the stored data to obtain error correction decoding data; and under the condition that the data type information characterizes the stored data as original data information, reading the stored data from the first internal cache based on the data transmission control module to the system cache, performing operation processing on the stored data in the system cache to obtain soft data information, transferring the soft data information to the first internal cache, reading the soft data information from the first internal cache based on the error correction control module, and performing soft decoding on the soft data information to obtain the error correction decoded data. Through the technical scheme, two different error correction decoding data generation modes can be compatible, different types of memories can be well adapted, and convenience is brought to users.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the disclosed embodiments.
FIG. 1 is a flow chart of a method for generating error correction decoded data according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for generating error correction decoded data according to another embodiment of the present invention;
FIG. 3 is a specific flow chart of S310 provided by one embodiment of the present invention;
FIG. 4 is a specific flowchart of S320 provided by one embodiment of the present invention;
FIG. 5 is a flowchart showing an embodiment of S320 according to the present invention;
FIG. 6 is a flow chart of a method for generating error correction decoded data according to another embodiment of the present invention;
FIG. 7 is a flow chart of a method for generating error correction decoded data according to another embodiment of the present invention;
FIG. 8 is a flow chart of an error correction decoding data generation and decoding process provided by an embodiment of the present invention;
FIG. 9 is a schematic diagram of a memory controller according to one embodiment of the present invention;
fig. 10 is a schematic diagram of the construction of an error correction decoded data generating apparatus according to an embodiment of the present invention;
fig. 11 is a schematic diagram of the configuration of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
The invention provides an error correction decoding data generation method, a device, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: in the process of generating error correction decoding data, reading storage data from flash memory particles to a first internal cache based on a flash memory bus time sequence module; then, carrying out type analysis processing on the stored data to obtain data type information; under the condition that the data type information characterizes the stored data as soft data information, reading the stored data from a first internal cache based on an error correction control module and performing soft decoding on the stored data to obtain error correction decoding data; and under the condition that the data type information characterizes the stored data as original data information, reading the stored data from the first internal cache based on the data transmission control module to the system cache, performing operation processing on the stored data in the system cache to obtain soft data information, transferring the soft data information to the first internal cache, reading the soft data information from the first internal cache based on the error correction control module, and performing soft decoding on the soft data information to obtain the error correction decoded data. Through the technical scheme, two different error correction decoding data generation modes can be compatible, different types of memories can be well adapted, and convenience is brought to users.
Embodiments of the present invention will be further described below with reference to the accompanying drawings.
As shown in fig. 1, fig. 1 is a flowchart of a method for generating error correction decoded data according to an embodiment of the present invention. The method is applied to a memory controller, and the memory controller comprises a flash memory bus time sequence module, a first internal cache, a system cache, an error correction control module and a data transmission control module, and comprises, but is not limited to, step S100, step S200, step S310 and step S320.
Step S100, based on a flash memory bus time sequence module, reading storage data from flash memory particles to a first internal cache;
step S200, performing type analysis on the stored data to obtain data type information;
step S310, when the data type information represents that the stored data is soft data information, the stored data is read from the first internal cache based on the error correction control module and is subjected to soft decoding to obtain error correction decoding data;
step S320, when the data type information represents that the stored data is the original data information, the stored data is read from the first internal cache based on the data transmission control module to the system cache, the stored data in the system cache is operated to obtain soft data information, the soft data information is transferred to the first internal cache, the soft data information is read from the first internal cache based on the error correction control module, and the soft data information is subjected to soft decoding to obtain error correction decoding data.
It should be noted that, during the process of generating the error correction decoding data, the memory data is read from the flash memory granule to the first internal cache based on the flash memory bus timing module; then, carrying out type analysis processing on the stored data to obtain data type information; under the condition that the data type information characterizes the stored data as soft data information, reading the stored data from a first internal cache based on an error correction control module and performing soft decoding on the stored data to obtain error correction decoding data; and under the condition that the data type information characterizes the stored data as original data information, reading the stored data from the first internal cache based on the data transmission control module to the system cache, performing operation processing on the stored data in the system cache to obtain soft data information, transferring the soft data information to the first internal cache, reading the soft data information from the first internal cache based on the error correction control module, and performing soft decoding on the soft data information to obtain the error correction decoded data. Through the technical scheme, two different error correction decoding data generation modes can be compatible, different types of memories can be well adapted, and convenience is brought to users.
As shown in fig. 9, the memory controller includes a flash memory bus timing module, a first internal buffer, a system buffer, an error correction control module, and a data transmission control module, and is used for performing data read-write operation processing on flash memory particles. The flash memory bus time sequence module is used for reading storage data from flash memory particles, the first internal cache and the system cache are both used for storing data, the error correction control module is used for performing soft decoding processing, and the data transmission control module is used for performing control transmission processing on related data. The first internal cache referred to in this embodiment is the internal cache 2 in fig. 9.
It is noted that, based on the flash bus timing module, the memory data is read from the flash memory granule to the first internal cache; then, carrying out type analysis on the read storage data to obtain data type information; wherein the data type information may characterize the stored data as soft data information or raw data information.
It should be noted that, when the data type information indicates that the stored data is soft data information, the error correction control module reads the stored data from the first internal buffer and performs soft decoding on the stored data to obtain error correction decoded data. Under the condition that the data type information characterizes the stored data as original data information, reading the stored data from a first internal cache based on a data transmission control module, and transferring the stored data to a system cache; in the system cache, operation processing is carried out on the stored data, original data information is converted into soft data information, then the obtained soft data information is stored in the first internal cache, then the error correction control module reads the soft data information from the first internal cache, and soft decoding processing is carried out on the soft data information, so that corresponding error correction decoding data can be obtained. Through the technical scheme, two different error correction decoding data generation modes can be compatible, different types of memories can be well adapted, and convenience is brought to users.
As shown in fig. 8, specifically, the flash memory bus timing module sends a command to read soft data information from the flash memory granule, the soft data information directly enters the internal buffer 2, after the buffer data amount satisfies the condition, the error correction control module reads data from the internal buffer 2 and starts soft decoding, and the decoded data is output to the internal buffer 1. And the data transmission control module is used for controlling the decoded data to be transmitted to the system cache for standby through the bus. In addition, when the flash memory bus timing module sends a command to read original data information from the flash memory particles and store the original data information into the internal cache 2; because the original data information can not be directly sent to the error correction control module for soft decoding, at the moment, the data transmission control module transmits the original data information to the system cache; the original data in the system cache is subjected to operation processing to obtain soft data information; the data transmission control module transmits the software data information from the system cache to the internal cache 2; after the buffer data quantity meets the condition, the error correction control module reads data from the internal buffer 2 and starts soft decoding, and the decoded data is output to the internal buffer 1; and finally, the data transmission control module controls the decoded data in the internal buffer 1 to be transmitted to the system buffer for standby through a bus.
In addition, in an embodiment, as shown in fig. 2, the memory controller further includes a second internal buffer, and may further include, but is not limited to, step S400 and step S500 after obtaining the error correction decoded data.
Step S400, the error correction decoding data are transferred to a second internal buffer;
step S500, based on the data transmission control module, the error correction decoding data is read from the second internal buffer memory to the system buffer memory.
It should be noted that, after the error correction decoded data is obtained, the error correction decoded data may also be restored to the second internal buffer; and then reading error correction decoding data from the second internal buffer memory to the system buffer memory based on the data transmission control module, and preparing for subsequent soft decoding.
In addition, in an embodiment, as shown in fig. 3, the step S310 may include, but is not limited to, step S311.
In step S311, in the case that the amount of buffered data in the first internal buffer meets the first preset condition, the stored data is read from the first internal buffer based on the error correction control module.
It should be noted that, when the amount of the buffered data in the first internal buffer meets the first preset condition, the stored data may be read from the first internal buffer based on the error correction control module. The buffer data amount in the first internal buffer memory meeting the first preset condition may be that the buffer data amount in the first internal buffer memory reaches a preset threshold.
In addition, in an embodiment, as shown in fig. 4, the step S320 may include, but is not limited to, step S321.
In step S321, in the case that the amount of buffered data in the first internal buffer meets the second preset condition, the soft data information is read from the first internal buffer based on the error correction control module.
It should be noted that, when the amount of buffered data in the first internal buffer meets the second preset condition, the soft data information may be read from the first internal buffer based on the error correction control module. The buffer data amount in the first internal buffer memory meeting the second preset condition may be that the buffer data amount in the first internal buffer memory reaches a preset threshold.
In addition, in an embodiment, as shown in fig. 5, the step S320 may further include, but is not limited to, step S322.
In step S322, the soft data information is transferred from the system cache to the first internal cache based on the data transfer control module.
It should be noted that the data transmission control module may transmit soft data information from the system buffer to the first internal buffer, and is ready for a subsequent soft decoding process.
In addition, in an embodiment, as shown in fig. 6, step S110, step S120, and step S130 may be further included, but are not limited to, before performing step S100.
Step S110, receiving an operation instruction sent by an external host terminal based on a protocol interface control module and analyzing the operation instruction to obtain operation analysis information;
step S120, the operation analysis information is transferred to a system cache;
step S130, reading and executing operation analysis information in the system cache based on the processor.
It should be noted that, firstly, based on the protocol interface control module, the operation instruction sent by the external host end is received, and the operation instruction is analyzed to obtain the operation analysis information; then the operation analysis information is transferred to a system cache; finally, based on the processor, reading and executing the operation analysis information in the system cache; the operation instruction may include a read operation and a write operation, among others.
In addition, in an embodiment, as shown in fig. 7, step S600 may be further included, but is not limited to, after the above-mentioned step S500 is performed.
Step S600, the error correction decoding data is read from the system cache based on the processor, and the decoding operation is performed according to the error correction decoding data.
It should be noted that, the error correction decoded data is read from the system cache based on the processor, and the decoding operation processing is performed according to the error correction decoded data, so as to implement the soft decoding processing.
In some embodiments of the present invention, as shown in fig. 10, an embodiment of the present invention further provides an error correction decoding data generating apparatus 10, applied to a memory controller, where the memory controller includes a flash memory bus timing module, a first internal buffer, a system buffer, an error correction control module, and a data transmission control module, the apparatus includes:
a first processing module 100, configured to read the storage data from the flash memory granule to a first internal cache based on the flash memory bus timing module;
the second processing module 200 is configured to perform type analysis on the stored data to obtain data type information;
the third processing module 300 is configured to, in a case where the data type information indicates that the stored data is soft data information, read the stored data from the first internal cache based on the error correction control module and perform soft decoding on the stored data to obtain error correction decoded data;
the fourth processing module 400 is configured to, when the data type information indicates that the stored data is original data information, read the stored data from the first internal buffer based on the data transmission control module to the system buffer, perform operation processing on the stored data in the system buffer to obtain soft data information, transfer the soft data information to the first internal buffer, read the soft data information from the first internal buffer based on the error correction control module, and perform soft decoding on the soft data information to obtain error correction decoded data.
The specific embodiment of the error correction decoding data generating apparatus 10 is basically the same as the specific embodiment of the error correction decoding data generating method described above, and will not be described here again.
In some embodiments of the present invention, as shown in fig. 11, an embodiment of the present invention further provides an electronic device 700, including: the memory 720, the processor 710, and the computer program stored on the memory 720 and executable on the processor 710, the processor 710 implements the error correction decoding data generation method in the above-described embodiments when executing the computer program, for example, performs the method steps S100 to S320 in fig. 1, the method steps S400 to S500 in fig. 2, the method step S311 in fig. 3, the method step S321 in fig. 4, the method step S322 in fig. 5, the method steps S110 to S130 in fig. 6, and the method step S600 in fig. 7 described above.
In some embodiments of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, for example, by one of the processors in the above-described apparatus embodiments, which may cause the processor to perform the error correction decoding data generation method in the above-described embodiment, for example, perform the method steps S100 to S320 in fig. 1, the method steps S400 to S500 in fig. 2, the method step S311 in fig. 3, the method step S321 in fig. 4, the method step S322 in fig. 5, the method steps S110 to S130 in fig. 6, and the method step S600 in fig. 7 described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.
Claims (10)
1. The method for generating error correction decoding data is characterized by being applied to a storage controller, wherein the storage controller comprises a flash memory bus time sequence module, a first internal cache, a system cache, an error correction control module and a data transmission control module, and the method comprises the following steps:
reading storage data from flash memory particles to the first internal cache based on the flash memory bus timing module;
performing type analysis on the stored data to obtain data type information;
reading the stored data from the first internal cache based on the error correction control module and performing soft decoding on the stored data to obtain error correction decoded data under the condition that the data type information characterizes the stored data as soft data information;
and under the condition that the data type information characterizes the stored data as original data information, reading the stored data from the first internal cache based on the data transmission control module to the system cache, performing operation processing on the stored data in the system cache to obtain the soft data information, transferring the soft data information to the first internal cache, reading the soft data information from the first internal cache based on the error correction control module, and performing soft decoding on the soft data information to obtain the error correction decoding data.
2. The method of generating error correction decoded data as claimed in claim 1, wherein said memory controller further comprises a second internal buffer, and wherein after obtaining said error correction decoded data, said method further comprises:
the error correction decoding data are transferred to the second internal cache;
and reading the error correction decoding data from the second internal buffer memory based on the data transmission control module to the system buffer memory.
3. The error correction decoded data generation method according to claim 1, wherein said reading the stored data from the first internal buffer based on the error correction control module comprises:
and under the condition that the amount of the cached data in the first internal cache meets a first preset condition, reading the stored data from the first internal cache based on the error correction control module.
4. The method of generating error correction decoded data according to claim 1, wherein said reading the soft data information from the first internal buffer based on the error correction control module comprises:
and under the condition that the buffer data amount in the first internal buffer memory meets a second preset condition, reading the soft data information from the first internal buffer memory based on the error correction control module.
5. The method of generating error correction decoded data as claimed in claim 1, wherein said transferring said soft data information to said first internal buffer comprises:
and transmitting the soft data information from the system cache to the first internal cache based on a data transmission control module.
6. The error correction decoded data generation method of claim 2, wherein said memory controller further comprises a protocol interface control module and a processor, said method further comprising, prior to reading memory data from a flash memory granule to said first internal cache based on said flash bus timing module:
receiving an operation instruction sent by an external host terminal based on the protocol interface control module and analyzing the operation instruction to obtain operation analysis information;
the operation analysis information is transferred to the system cache;
and reading and executing operation analysis information in the system cache based on the processor.
7. The method for generating error correction decoded data as claimed in claim 6, wherein said method further comprises, after said error correction decoded data is read from said second internal buffer to said system buffer based on said data transmission control module:
and reading the error correction decoding data from the system cache based on the processor, and performing decoding operation according to the error correction decoding data.
8. An apparatus for generating error correction decoded data, the apparatus being applied to a memory controller, the memory controller including a flash memory bus timing module, a first internal cache, a system cache, an error correction control module, and a data transmission control module, the apparatus comprising:
the first processing module is used for reading storage data from the flash memory particles to the first internal cache based on the flash memory bus time sequence module;
the second processing module is used for carrying out type analysis on the stored data to obtain data type information;
the third processing module is used for reading the stored data from the first internal cache based on the error correction control module and performing soft decoding on the stored data to obtain error correction decoded data when the data type information characterizes the stored data as soft data information;
and the fourth processing module is used for reading the stored data from the first internal cache based on the data transmission control module to the system cache under the condition that the data type information characterizes the stored data as original data information, performing operation processing on the stored data in the system cache to obtain the soft data information, transferring the soft data information to the first internal cache, reading the soft data information from the first internal cache based on the error correction control module, and performing soft decoding on the soft data information to obtain the error correction decoded data.
9. An electronic device, comprising:
memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the error correction decoding data generation method according to any one of claims 1 to 7 when the computer program is executed.
10. A computer-readable storage medium storing computer-executable instructions which, when executed by a control processor, implement the error correction decoding data generation method of any one of claims 1 to 7.
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