JP2000349687A - Digital matched filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital matched filter whose power consumption can be reduced while maintaining accuracy of synchronization acquisition in a reception station of a mobile communication system on the basis of the direct spread spectrum system. SOLUTION: The digital matched filter uses sub matched filters MF1-MFm corresponding to 1-m-bit signals resulting from level-shifting a received signal, correlation with a spread code is calculated and the correlation value is outputted to a threshold value discrimination section 23. The threshold value discrimination section 23 compares a threshold value set in advance in response to the number of bits of the sub matched filters MF1-MFm with outputs of the sub matched filters MF1-MFm and a sum matched filter control section 24 selects any of the sub matched filters MF1-MFm whose output exceeds the threshold value and the number of processed bits of which is minimized as a sub matched filter to be operated in the reception state. Thus, the power consumption can be reduced by decreasing properly the processed bit number of the matched filter while keeping detection accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization acquisition circuit provided in a reception circuit of a mobile communication system based on a direct spread spectrum communication system, and more particularly to a digital communication system capable of reducing power consumption while maintaining detection accuracy. The present invention relates to a matched filter, a receiver, and a communication system.

[0002]

2. Description of the Related Art In a mobile communication system based on a direct spread spectrum communication system, as shown in FIG.
, The original signal is spread by a spreading code, while the receiver 71 despreads the received signal using the same spreading code replica as the transmitter 70 to extract the original signal. As such a despreading technique on the receiver side, a digital matched filter that is generally superior in detection speed is used. An example of such a digital matched filter is described in "Digital matched filter technology in spread spectrum communication and its problems" (Toshio Tajika, IEICE Technical Report SST62-21).

As shown in FIG. 8, a despreading circuit 80 in a receiver includes a digital matched filter 81 and a cyclic integration section 8.
2. It is composed of a synchronization acquisition determination unit 83 and a control unit 84.

[0004] Each component will be specifically described below. The digital matched filter 81 receives the input of the received signal, outputs a correlation value of the spread code with the replica signal as a despread signal, and according to a control signal from the control unit 84, a spread code register value (tap coefficient). Is rewritten or the received signal accumulation register is updated.

The cyclic integration 82 is a digital matched filter
The correlation value output by 81 is averaged by integrating over several period sections of the spreading code, and is used to improve noise removal / peak detection accuracy. When the S / N is good (the signal energy is much higher than the noise energy), it is easy to detect the correlation value peak, but the S / N
Is poor (the energy of the signal is not much different from the energy of the noise), it can be expected that this cyclic integration will improve the detection accuracy of the correlation value peak. An example of a digital matched filter using cyclic integration is "DS / GMSK / PSK system using 4-phase correlator and LS for spread spectrum demodulation.
I "(Yasuhiro Yano, Hisao Tajika, Tadashi Fujino, IEICE Technical Report SST96-26)
It is described in.

[0006] The synchronization acquisition determining section 83 determines whether or not the correlation integral value output from the cyclic integration section 82 exceeds a threshold value set in advance, and exceeds the threshold value. In this case, the control unit 84 outputs a signal ("1") indicating that the signal has exceeded, and otherwise outputs a signal ("0") indicating the signal to the control unit 84.

[0007] If the signal input from the synchronization acquisition determining section 83 is “1”, the control section 84 pulls the phase difference of the spread code within an error of 1 / operating frequency of the digital matched filter 81. As a result (coarse synchronization), the control signal is output to the digital matched filter 81. Next, a configuration example of a conventional digital matched filter 81 will be described with reference to FIG.
Here, it is assumed that the spreading code is already known, and one cycle of the spreading code output from the spreading code replica generator 90 is used as the tap coefficient of the digital matched filter 81 via the input spreading code register 91 via the operation spreading code register 91. It shall be stored in 92. In the digital matched filter 81, the received signal quantized to n bits (n ≧ 1) is oversampled at M times the chip rate (M ≧ 2), and the received signal is stored in the received signal accumulation register 93 by (spreading code length) × M pieces are sequentially accumulated.
Here, the spreading code length is the number of chips for one cycle of the spreading code. Then, a correlation value between the received signal accumulation register 93 and the tap coefficient is calculated by the multiplication unit 94 and the addition unit 95, and the correlation value is output to the cyclic integration unit 82 and averaged. The cyclic integration value is output to the synchronization acquisition determination unit 83, and the detection of the correlation peak and the determination of the completion of the coarse synchronization acquisition are performed by comparing the threshold values. After the completion of the coarse synchronization acquisition, the spread code timing is tracked to demodulate the original signal.

[0008]

Generally, since a digital matched filter is a transversal filter,
If the number of processing bits of the input signal is increased in order to increase the correlation peak detection accuracy, there is a problem that the amount of multiplication and addition processing increases and power consumption increases.

In the conventional digital matched filter 81, the number of bits of the input signal is fixed regardless of the transmission path environment. As a result, the detection accuracy of the correlation peak of the digital matched filter 81 is maintained and the power consumption is reduced. It is difficult to achieve both, and it has been a hindrance to reducing the power consumption of the entire receiving circuit.

[0010] The present invention has been made in view of the above problems, and an object of the present invention is to provide a digital matched filter capable of reducing power consumption while maintaining detection accuracy.

[0011]

According to a first aspect of the present invention, a digital matched filter calculates a correlation value between an m-bit input signal and a spreading code, and determines whether a transmission path environment is good or bad. Judge and m if the transmission path environment is good
It is characterized in that a correlation value between an input signal having a smaller number of bits than a bit and a spreading code is calculated.

Thus, when the transmission path environment is favorable, the number of input bits can be reduced and the digital matched filter can be operated with the optimum number of processing bits in terms of power consumption. On the other hand, power consumption can be reduced while maintaining the correlation peak detection accuracy.

Here, the case where the transmission path environment is favorable means a state where the influence of white Gaussian noise or Rayleigh fading added to radio waves on the transmission path is small.

According to a second aspect of the present invention, in the digital matched filter, a first sub-matched filter for calculating a correlation value between an m-bit input signal and a spreading code, and a bit smaller than m bits A second sub-matched filter for calculating a correlation value between the number of input signals and the spreading code, and determining whether the transmission path environment is good or not, and when the transmission path environment is good, the second sub-matched filter. And a control unit for selecting use of the filter.

Thus, when the transmission path environment is favorable, it is possible to select the second sub-matched filter having a small number of processing bits and operate the digital matched filter with the optimum number of processing bits in terms of power consumption. Therefore, power consumption can be reduced while maintaining the correlation peak detection accuracy for a favorable transmission path environment.

According to a third aspect of the present invention, in the digital matched filter according to the first aspect, a plurality of second sub-matched filters are provided, and each of the second sub-matched filters is an input to be processed. The number of bits of the signal is different, and the control unit selects one of the first or the plurality of second sub-matched filters according to the degree of the quality of the transmission path environment. I have.

Thus, by selecting one of the plurality of second sub-matched filters in accordance with the degree of pass / fail of the transmission path environment, the digital matched filter with the optimum number of processing bits in terms of power consumption can be obtained. Since the filter can be operated, power consumption can be reduced while maintaining the correlation peak detection accuracy for a favorable transmission path environment.

According to a fourth aspect of the present invention, in the digital matched filter according to the second aspect, the control unit includes a first filter.
A first threshold value judging section for comparing a correlation peak threshold value preset according to the sub-matched filter with an output of the first sub-matched filter, and a second sub-matched filter A second threshold value judging section for comparing a correlation peak threshold value set in advance with the output of the second sub-matched filter, and outputs of the first and second sub-matched filters Selects the second sub-matched filter when the respective correlation peak thresholds are exceeded, and when only the output of the first sub-matched filter exceeds the corresponding correlation peak thresholds And a sub-matched filter control unit for selecting the first sub-matched filter.

In this way, when the transmission path environment is favorable, the digital matched filter is operated with the optimum number of processing bits in terms of power consumption by selecting the second sub-matched filter having a small number of processing bits. Therefore, it is possible to reduce power consumption while maintaining correlation peak detection accuracy in a favorable transmission path environment.

According to a fifth aspect of the present invention, in the digital matched filter according to the fourth aspect, a plurality of groups each including a second sub-matched filter and a second threshold value judging section are provided. The sub-matched filters 2 have different numbers of input signal bits to be processed, respectively.
Correspondingly, the correlation peak threshold values respectively set in the second threshold value judgment units are also different, and the submatched filter control unit It is characterized in that a sub-matched filter having the minimum number of bits of the input signal is selected from the filters.

Thus, by selecting one of the plurality of second sub-matched filters in accordance with the degree of pass / fail of the transmission path environment, the digital matched filter with the optimum number of processing bits in terms of power consumption can be obtained. Since the filter can be operated, power consumption can be reduced while maintaining the correlation peak detection accuracy for a favorable transmission path environment.

The invention described in claim 6 is the invention according to claims 1 to 5
In the digital matched filter according to any one of the above, the received signal quantized into n bits is converted into the m-bit (m ≦ n) input signal and the input signal having a bit number smaller than m bits. Circuit is provided.

Thus, the number of bits to be processed by the digital matched filter can be controlled, so that the selecting operation can be performed regardless of the number of bits of the received signal.

[0024] The invention according to claim 7 is the invention according to claims 2 to 5.
The digital matched filter according to any one of the above, wherein the spread code replica generator, the input spread code register, and the operation spread code register are shared between the first and second sub-matched filters. And

Thus, the circuit scale can be reduced because the circuits are shared.

The invention described in claim 8 is the invention according to claims 2 to 5
In the digital matched filter according to any one of the above, the control unit executes the selecting operation at predetermined intervals.

With this, the digital matching filter can be operated with the optimum number of processing bits in terms of power consumption by executing the selection operation under a constantly changing transmission path environment. , Power consumption can be reduced while maintaining the correlation peak detection accuracy.

The invention according to claim 9 is the invention according to claims 4 and 5.
In the digital matched filter according to any one of the above, the sub-matched filter control unit operates a control counter that generates a pulse signal at predetermined intervals, and operates all the sub-matched filters each time the pulse signal is received. And a sub-matched filter selecting unit for executing the selecting operation.

With this, the digital matching filter can be operated with an optimal number of processing bits in terms of power consumption by executing the selection operation under a constantly changing transmission path environment. , Power consumption can be reduced while maintaining the correlation peak detection accuracy.

According to a tenth aspect of the present invention, in the digital matched filter according to any one of the first to ninth aspects, a mode selection circuit for switching whether or not to execute the selection operation is provided. It is characterized by.

According to this, it is possible to select the use of the conventional digital matched filter and the use of the digital matched filter according to any one of claims 1 to 9 according to the communication situation. When the transmission path environment is unstable, if the conventional digital matched filter is selected, synchronization loss due to the shortage of the number of processing bits can be prevented, that is, communication cutoff can be prevented, and when the transmission path environment during communication is stable and good, If the use of the digital matched filter according to any one of claims 1 to 9 is selected, the digital matched filter can be operated with an optimum number of processing bits in terms of power consumption. Power consumption can be reduced while maintaining.

According to an eleventh aspect of the present invention, a receiver is provided with the digital matched filter according to any one of the first to tenth aspects.

Thus, it is possible to provide a receiver that can reduce power consumption while maintaining the correlation peak detection accuracy.

According to a twelfth aspect of the present invention, a communication system includes the receiver according to the eleventh aspect.

Thus, it is possible to provide a communication system that reduces power consumption while maintaining correlation peak detection accuracy.

[0036]

FIG. 1 is a block diagram showing a configuration of a despreading circuit 10 including a digital matched filter according to an embodiment of the present invention. The despreading circuit 10 includes a digital matched filter 11, a cyclic integration unit 12, a synchronization acquisition determination unit 13, and a control unit 14.

FIG. 2 shows the configuration of the digital matched filter 11. In the initial operation, the received signal quantized to n bits (n ≧ 1) is level-shifted to _{1 to m} bits by the level shifter 21 and input to the matched filter bank 22 as signals S _{1 to} Sm. Here S _m represents a signal of m bits. Note that the level shifter 21 corresponds to a “circuit” according to claim 6.

The matched filter bank 22 includes a number of sub-matched filters MF corresponding to the output signals of the level shifter 21.
Consists _{1 ~MF m,} the correlation output of each sub-matched filter MF ₁ ~MF _m is the corresponding threshold comparator threshold determination unit 23
Each is compared with the correlation peak threshold is preset in the CMP ₁ ~CMP _m.

[0039] Each comparator CMP ₁ ~CMP _m is correlation output is generated a detection pulse DET ₁ ~DET _m if it becomes larger than the threshold value, and outputs it to the sub-matched filter control unit 24. The sub-matched filter control unit 24 operates a suitable _one of the sub-matched filters MF _{1 to} MF _m of the matched filter bank 22 according to this signal, and stops the other sub-matched filters. Is output to the matched filter bank 22. Note that the sub-matched filter MF _{m corresponds} to the “first sub-matched filter” in the present invention, and the sub-matched filters MF _{1 to} MF _m−1 correspond to the “second sub-matched filter” in the present invention. .

The output of the correlation value of the selected sub-matched filter is averaged by the cyclic integration section 12, and then output to the synchronization acquisition determination section 13. Correlation peak detection and coarse synchronization are performed by comparing the cyclic integration threshold. Judge the completion of capture. After the completion of the coarse synchronization acquisition, the spread code timing is tracked, and the original signal is demodulated. Next, the matched filter bank 22 will be specifically described with reference to FIGS.

FIG. 3 shows the configuration of the matched filter bank 22. Matched filter bank 22, the input signal S ₁ to S sub match corresponding to _m preparative filter MF ₁ ~MF _m, spreading code replica generator 33, an input spreading code register 34 and the arithmetic spread code registers from the level shifter 21 Consists of 35. Sub matched filter MF ₁ ~MF _m are each received signal storage registers 30-1 to 30-m, a multiplication unit 31-1 to 31-m and the adder unit 32-1 to 32-m. Spreading code replica generator 33, an input spreading code register 34 and the arithmetic spreading code register 35 is shared by the sub-matched filter MF ₁ ~MF _m.

The sub-matched filters MF ₁ to MF _m are supplied from the level shifter 21 with corresponding input signals S _{1 to} S of ₁ to _m bits.
_m is input and stored for one cycle of the spread code in the received signal accumulation registers 30-1 to 30-m at the same sampling rate (usually twice or more the chip rate). The spread code that is correlated with the received accumulated signal is stored in the input spread code register 34 for the serial signal output from the spread code replica generator 33, and is used for calculation when one cycle of the spread code is stored. The signal is passed to the spreading code register 35, and the correlation operation is started. The value of the arithmetic spreading code register 35 is
In sub matched filter MF ₁ ~MF _m, multiplication unit 31-1～3 the value stored in the reception signal storage registers 30-1 to 30-m
1-m, and the multiplication result is added to adders 32-1 to 32-m
Is input to

The adders 32-1 to 32-m add up the multiplication results, so that the spread code replica stored in the arithmetic spread code register 35 and the corresponding received signal accumulation registers 30-1 to 30-m are added. Are calculated with respect to the input signals S _{1 to} S _m stored in. Then, the correlation value is determined by a threshold determination unit.
Output to 23.

As shown in FIG.
Comparators CMP _{1 to} CMP _m are provided. Each comparator CMP _{1 to} CMP _m
Have corresponding sub-matched filters MF _{1 to} MF _m
Are input and compared with a preset threshold value. Each threshold value, under the same receiving conditions, is set to the correlation peak value required for synchronization establishment when sub matched filter MF ₁ ~MF _m is operated either singly. Each of the comparators CMP _{1 to} CMP _m outputs a detection pulse to the submatched filter control unit 24 when the correlation output value exceeds the threshold value. Note that the threshold value judgment unit 23 and the sub-matched filter control unit 24 correspond to the “control unit” in the present invention.

In the configuration described above, the oversampling
The number of samplings is 2, the spreading code length is 8, and the received signal is quantized.
4 bits and sub-matched filter MF₁~ MF_FourInput
The number of signal bit steps is 4 (n = 4, m = 1, 2,
3 and 4).
This will be described with reference to FIG. FIG. 4 is an explanatory diagram showing the operation of this circuit.
And shows a waveform example of each signal. Input signal S₁~ S_Fouras well as
The received signal accumulation register is a sub-matched filter MF₁~ M
F_FourSince the timing is common between the
Have been. Referring to FIG.
1 bit × 16 (oversampling number × spreading code
Length) For sample: C8-C8-C7-C7-C6-C6-C5-C5-C4-C4-C3-C3-C2-C2-C1-C1 are stored (C1 to C8 are each "1") Or "0"). Also
Input signal S after bell control ₁~ S_FourIs a periodic value of RC1 to RC8
Is repeated. RC1 to RC8 are signal S₁~ S_Four1 representing
~ 4 bit value, each of which is set by the spreading code C1 ~ C8
It is assumed that they are spread. A to I are the timings shown
Sub-matched filter MF₁~ MF_FourReceiving in
Expressing the values stored in the signal accumulation registers 30-1 to 30-4
The received signal accumulation registers 30-1 to 30-4
Signal S at the rising edge of the clock signal ₁~ S_FourSequentially stored
You.

That is, in FIG. 4, the received signal accumulation registers 30-1 to 30-4 store 16 samples of the input signals S _{1 to} S ₄ , specifically, A: RC5-RC5-RC4-RC4- RC3-RC3-RC2-RC2-RC1-RC1-RC8-RC8
-RC7-RC7-RC6-RC6 B: RC6-RC5-RC5-RC4-RC4-RC3-RC3-RC2-RC2-RC1-RC1-RC8
-RC8-RC7-RC7-RC6 C: RC6-RC6-RC5-RC5-RC4-RC4-RC3-RC3-RC2-RC2-RC1-RC1
-RC8-RC8-RC7-RC7 D: RC7-RC6-RC6-RC5-RC5-RC4-RC4-RC3-RC3-RC2-RC2-RC1
-RC1-RC8-RC8-RC7 E: RC7-RC7-RC6-RC6-RC5-RC5-RC4-RC4-RC3-RC3-RC2-RC2
-RC1-RC1-RC8-RC8 F: RC8-RC7-RC7-RC6-RC6-RC5-RC5-RC4-RC4-RC3-RC3-RC2
-RC2-RC1-RC1-RC8 G: RC8-RC8-RC7-RC7-RC6-RC6-RC5-RC5-RC4-RC4-RC3-RC3
-RC2-RC2-RC1-RC1 H: RC1-RC8-RC8-RC7-RC7-RC6-RC6-RC5-RC5-RC4-RC4-RC3
-RC3-RC2-RC2-RC1 I: RC1-RC1-RC8-RC8-RC7-RC7-RC6-RC6-RC5-RC5-RC4-RC4
-RC3-RC3-RC2-RC2 is stored.

Here, since the timing matches the value stored in the arithmetic spreading code register 35 in the state of “G”, the correlation output values of the submatched filters MF _{1 to} MF ₄ are “G”.
It can be estimated that the peak occurs in the state of. The signals DET _{1 to} DET ₄ represent detection pulses output from the threshold determination unit 23, and each of the signals DET _{1 to} DET ₄ has a 1 to 4 bit sub-matched filter MF ₁
~MF represents the detection pulse for the correlation output of _4.

Here, FIG. 4A shows that the power of the noise is large,
FIG. 4 shows a waveform example of signals DET _{1 to} DET _{4 in} a severe transmission path environment such as a high Rayleigh fading speed.
(b) is a signal DET ₁ in a relatively good transmission path environment.
Shows an example of the waveform of ~DET _4.

The correlation peak detection pulse in 3-bit sub-matched filter MF ₃ and 4-bit sub-matched filter MF ₄ in the case of (a) is obtained, in the case of (b), 2-bit sub-matched filter MF ₂ , 3-bit submatched filter MF ₃
And a correlation peak detection pulse obtained by the 4-bit sub-matched filter MF _4. That is, in the case of (a), the receiving condition is relatively inferior to the case of (b), so that it is understood that the processing bit precision of the sub-matched filter for the received signal is required to be 3 bits or more.

FIG. 5 shows the sub-matched filters MF _{1 to} MF ₄ operated with the detection pulses and the threshold value comparators CMP _{1 to} CM
₄ shows the relationship of P4. Here, the sub-matched filters MF _{1 to} MF ₄ and the threshold decision unit comparator CM are output by the signals DET _{1 to} DET _4.
Carry out the ON / OFF control of P ₁ ~CMP _4. When the signal DET ₁ ~DET ₄ are all "1", and stops the sub-matched filter MF ₂ ~MF ₄ operating the MF _1. Similarly, the signal DET ₁ ~DET ₃ "0" by the signal DET ₄ is "1" stops sub matched filter MF ₁ ~MF ₃ operating the MF ₄ For. In the default state, the signal DE
T perform a re-calculation as invalid _{1 ~DET 4.} By performing such control, while maintaining the correlation peak detection accuracy,
Under a better transmission path environment, a sub-matched filter with a smaller number of processing bits is used, so that power consumption can be reduced.

Further, in order to flexibly cope with various transmission path environments, the sub-matched filters MF _{1 to} MF _m are operated at a predetermined cycle and the sub-matched filter selection operation is repeated to reduce power consumption. It is necessary to periodically update the optimum number of processing bits. For example, the sub-matched filter control unit 24 includes a control counter 60 and a sub-matched filter selection unit 61 as shown in FIG. Control counter 60
Generates a pulse signal every predetermined period, and the sub-matched filter selecting unit 61 receives the pulse signal every time.
The sub-matched filter selected and operated in the previous cycle and all the sub-matched filters in the stopped state are restarted, and the selection of the sub-matched filter used in the next cycle is performed by the sub-matched filter selection operation. .
That is, as shown in FIG. 5, _{one of the} sub-matched filters MF _{1 to} MF ₄ which becomes the minimum necessary processing bits under the reception conditions at the time of reception is selected according to the signals DET ₁ to DET ₄ . By repeating this process, it is possible to flexibly cope with the ever-changing transmission path environment.

A mode selection circuit 62 may be provided to externally switch the control mode / non-control mode for the number of processing bits. That is, in the processing bit number non-control mode, the sub-matched filter MF included in the matched filter bank 22 is
Sub-matched filter with the maximum number of processing bits from _{1 to} MF ₄
MF ₄ is used unconditionally, and in the processing bit number control mode,
Perform sub-matched filter selection operation. For example, when the influence of Rayleigh fading is large, the processing bit number non-control mode is set. Thereby, the number of processing bits using the maximum of the sub-matched filter MF _4, out synchronization due to insufficient number of processing bits, can be prevented communication cutoff. At this time, the threshold judging unit corresponding to the sub-matched filter MF ₄ except sub matched filter and they all stopped. On the other hand, when the influence of the Rayleigh fading is small and the transmission path environment during use is stable, the sub-matched filter selection operation is performed as the processing bit number control mode. As a result, the number of processing bits of the matched filter used during communication can be optimized, and power consumption can be reduced.

As described above, in the present embodiment, the spreading codes and the sub-matched filters MF _{1 to} MF _m corresponding to the input signals of _{1 to m} bits in which the received signal is level-shifted are respectively used. Is calculated, and the correlation value is output to the threshold value determination unit 23. In the threshold determination unit 23,
Sub matched filter MF ₁ ~MF threshold and sub matched that is set in advance according to the number of bits of _m filter MF ₁ ~MF _m
The output of the sub-matched filters MF _{1 to} MF _m whose output exceeds the threshold value and whose processing bit number is the smallest should be operated by the sub-matched filter control unit 24 in the reception state. Select as a submatched filter. This reduces power consumption by reducing the number of processing bits according to the reception state, that is, when the transmission path environment is good, and reduces the detection accuracy by increasing the number of processing bits when the transmission path environment is poor. prevent.

The number of sub-matched filters MF _{1 to} MF _m of the matched filter bank 22 is reduced by coarsening the shift step of the level shifter 21 to 2 bits, 3 bits, or the like due to the limitation of the receiving circuit scale or power consumption. You may. Further, the sub-matched filters MF _{1 to} MF _m−1 corresponding to the “second sub-matched filter” in the present invention, the sub-matched filter selection performed by the threshold determination unit 23 and the sub-matched filter control unit 24 The operation may be realized by signal processing software such as a DSP. In this case, DSP controls the number of processing bits of the matched filter MF _m.

[0055]

As described above, according to the present invention,
In harsh transmission channel environments such as when noise power is large and Rayleigh fading speed is high, the correlation peak detection accuracy is maintained by increasing the number of bits of the input signal, and conversely in a better transmission channel environment. In this case, since the power consumption is reduced by reducing the number of bits of the input signal, the power consumption can be reduced while maintaining the correlation peak detection accuracy.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a despreading circuit according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a matched filter correlation operation unit according to the embodiment of the present invention.

FIG. 3 is a configuration diagram illustrating a matched filter bank according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram illustrating an operation of a matched filter correlation operation unit according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram illustrating an operation of a sub-matched filter control unit according to the embodiment of the present invention.

FIG. 6 is a configuration block diagram of a sub-matched filter control unit according to the embodiment of the present invention.

FIG. 7 is an overall configuration block diagram of a communication system according to an embodiment of the present invention and a conventional example.

FIG. 8 is a configuration block diagram of a conventional despreading circuit.

FIG. 9 is a configuration diagram illustrating an example of a conventional digital matched filter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Despreading circuit 11 Digital matched filter 12 Cyclic integrator 13 Synchronization acquisition judgment part 14 Control part 21 Level shifter 22 Matched filter bank 23 Threshold judgment part 24 Submatched filter control part 30 Received signal accumulation register 31 Multiplication part 32 Adder 33 Spread code replica generator 34 Spread code register for input 35 Spread code register for operation 60 Control counter 61 Submatched filter selection circuit 62 Mode selection circuit

Claims (12)

[Claims] 1. A digital matched filter for calculating a correlation value between an m-bit input signal and a spreading code,
A digital matched filter for determining whether a transmission path environment is good or not, and calculating a correlation value between an input signal having a bit number smaller than m bits and a spreading code when the transmission path environment is good. 2. A first sub-matched filter for calculating a correlation value between an m-bit input signal and a spreading code, and a correlation value between an input signal having a bit number smaller than m bits and the spreading code And a control unit for determining whether the transmission path environment is good or not and selecting the use of the second sub-matched filter when the transmission path environment is good. Digital matched filter featured. 3. A method according to claim 1, wherein a plurality of said second sub-matched filters are provided, and each of said second sub-matched filters has a different number of bits of an input signal to be processed. The digital matched filter according to claim 2, wherein one of the first or the plurality of second sub-matched filters is selected according to a degree of quality of the environment. 4. A first threshold for comparing a correlation peak threshold preset according to the first sub-matched filter with an output of the first sub-matched filter. A value determination unit, a second threshold value determination unit that compares a correlation peak threshold value preset according to the second submatched filter with an output of the second submatched filter, Selecting the second sub-matched filter when the output of the first and second sub-matched filters exceeds the corresponding correlation peak threshold,
A sub-matched filter control unit that selects the first sub-matched filter when only the output of the first sub-matched filter exceeds a corresponding correlation peak threshold value. Item 3. A digital matched filter according to item 2. 5. A plurality of groups each comprising the second sub-matched filter and a second threshold value judging unit are provided, and each of the second sub-matched filters has a different number of bits of an input signal to be processed. Correlation peak thresholds respectively set in the second threshold value judgment sections are also different, and the sub-matched filter control section exceeds the correlation peak threshold value. 5. The digital matched filter according to claim 4, wherein a sub-matched filter having the smallest number of bits of the input signal is selected from the sub-matched filters. 6. A circuit for converting a received signal quantized to n bits into an input signal of m bits (m ≦ n) and an input signal of a bit number smaller than m bits. A digital matched filter according to claim 1. 7. A spread code replica generator, an input spread code register and an operation spread code register are shared between the first and second sub-matched filters. The digital matched filter according to claim 1. 8. The digital matched filter according to claim 2, wherein the control unit executes the selection operation at predetermined intervals. 9. The sub-matched filter control section executes a selection operation by operating a control counter that generates a pulse signal at predetermined intervals and operating all sub-matched filters each time the pulse signal is received. The digital matched filter according to claim 4, further comprising a sub-matched filter selection unit. 10. The digital matched filter according to claim 1, further comprising a mode selection circuit for switching whether or not to execute the selection operation. 11. A receiver comprising the digital matched filter according to claim 1. Description: 12. A communication system comprising the receiver according to claim 11.