JP2000349176A - Non-volatile semiconductor memory device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device where steps are less around a gate. SOLUTION: In this manufacturing method, a control gate 14 is formed on a P-type semiconductor substrate 10 using a nitride film 16 as a mask, and then side walls 22a and 22b are formed. An interlayer insulating film 26 is deposited on all the surface of the substrate 10, and a groove (recess) is provided to a part of the interlayer insulating film 26 where a floating gate is to be formed. A polycrystalline silicon film is deposited so as to fill up the groove and then etched by chemomechanical polishing(CMP) or the like, by which a floating gate 36 buried in the groove is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor memory devices are broadly classified into volatile semiconductor memory devices such as DRAM which require a memory holding operation, and nonvolatile semiconductor memory devices not requiring a memory holding operation. 2. Description of the Related Art In recent years, nonvolatile semiconductor memory devices have been adopted in various fields, and miniaturization and high integration are required.

FIGS. 15A and 15B show FAMOS (Float) which has been put to practical use as a nonvolatile semiconductor memory device.
FIG. 15C shows a cross-sectional structure of an ing-gate Avalanche-injection MOS), and FIG. 15C shows an equivalent circuit of these devices. FIG. 15A shows a structure that was put to practical use at an early stage. This device has a stack structure in which a floating gate 206 and a control gate 205 are stacked on a semiconductor substrate 200. A source region 204 is formed in an active region surrounded by element isolation 202 on the surface of the semiconductor substrate 200.
a and the drain region 204b are formed. Some of the electrons emitted from the source region 204a are
Before reaching the gate electrode 04b, the electrons are hot-electronized and injected into the floating gate 206. FIG. 15B shows a structure in which the floating gate 216 and the control gate 218 are formed in a self-aligned manner, which is more suitable for improving the degree of integration.

[0004]

According to the above-described nonvolatile semiconductor memory device, a large step is formed due to a laminated structure including a control gate and a floating gate with the miniaturization of element size. There is a problem that it is difficult to form an upper wiring. This leads to short-circuiting and disconnection of the wiring, which not only lowers the production yield of the device but also lowers the reliability.

[0005]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor region; a source and a drain formed in the semiconductor region; a floating gate insulated from the semiconductor region; And a control gate insulated from the floating gate, further comprising an interlayer insulating layer covering the semiconductor region and having an upper surface planarized, wherein the floating gate and the control gate At least one is embedded in a recess formed in the interlayer insulating layer.

Preferably, at least one of the upper surfaces of the floating gate and the control gate is polished together with the upper surface of the interlayer insulating layer.

It is preferable that the upper surface of the gate buried in the recess of the interlayer insulating layer is located at substantially the same level as the upper surface of the interlayer insulating layer.

[0008] In one embodiment, the floating gate is embedded in the concave portion of the interlayer insulating layer.

[0009] Another insulating film covering the floating gate and the interlayer insulating film, and an erase gate formed on the other insulating film and including a portion facing the floating gate via the other insulating film. Further, it may be provided.

In one embodiment, a capacitance insulating film formed on the floating gate and a drain electrode electrically connected to the drain and capacitively coupled to the floating gate via the capacitance insulating film. It has more.

It is preferable that the capacitance insulating film is formed not only on the side surface but also on the upper surface of the floating gate.

In one embodiment, the semiconductor device further includes another interlayer insulating film formed on the interlayer insulating film, wherein the drain electrode extends the interlayer insulating film and the other interlayer insulating film until the semiconductor layer reaches the semiconductor region. It is embedded in the opening that penetrates.

In one embodiment, the drain region includes a plurality of impurity diffusion layers, and at least a part of the drain region overlaps a part of the floating gate.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a semiconductor region, a source and a drain formed in the semiconductor region, a floating gate insulated from the semiconductor region, the semiconductor region and the floating A method of manufacturing a non-volatile semiconductor storage device having a control gate insulated from a gate, the method comprising: forming a control gate having an upper surface and side surfaces covered by an insulating layer on the semiconductor region; Forming a recess in the interlayer insulating film by selectively etching a part of the interlayer insulating film; and forming a recess in the interlayer insulating film by selectively etching a part of the interlayer insulating film. Filling the formed recess with a conductive material, thereby forming the floating gate made of the conductive material in the recess of the interlayer insulating film Including a floating gate forming process that.

In one embodiment, the floating gate forming step includes a step of forming a conductive film of the conductive material so as to cover the interlayer insulating film so as to fill the concave portion of the interlayer insulating film; And removing a portion located on the interlayer insulating film.

The step of removing a portion of the conductive film located on the interlayer insulating film is preferably performed using a chemical mechanical polishing method.

The step of removing a portion of the conductive film located on the interlayer insulating film may be performed using an etch-back method.

The floating gate forming step may include a step of selectively growing a conductive film of the conductive material in the concave portion of the interlayer insulating film.

Before the step of forming a recess in the interlayer insulating film by selectively etching a part of the interlayer insulating film, a step of planarizing the upper surface of the interlayer insulating film is included. Is also good.

The flattening step may be performed using a chemical mechanical polishing method, or may be performed using an etch back method.

In one embodiment, the step of forming the recess in the interlayer insulating film includes the step of forming a resist mask having an opening defining the recess at a position overlapping the control gate in a planar layout. When,
Etching a part of the interlayer insulating film through the opening of the resist mask to form the recess so as to reach a surface of the semiconductor region.

The method may further include, after forming the concave portion in the interlayer insulating film, forming a tunnel insulating film on the surface of the semiconductor region exposed at the bottom of the concave portion.

In one embodiment, after forming the concave portion in the interlayer insulating film, impurity ions are implanted into the surface of the semiconductor region located at the bottom of the concave portion,
This includes a doping step of forming an impurity-doped region functioning as a part of the drain region.

In one embodiment, after the doping step, a step of removing the insulating layer covering the side surface of the control gate is included.

In one embodiment, the method includes a step of forming a tunnel insulating film on the surface of the semiconductor region exposed at the bottom of the recess after removing the insulating layer covering the side surface of the control gate.

The tunnel insulating film may be formed on a side surface of the control gate.

In one embodiment, the step of forming the control gate having the upper surface and the side surface covered with an insulating layer on the semiconductor region includes the step of forming the control gate having the upper surface covered with an insulating layer. Covering the side surface of the control gate with an insulating layer.

In one embodiment, the step of covering the side surface of the control gate with an insulating layer includes the step of forming an insulating film covering the control gate, and the step of forming the insulating film covering the control gate by anisotropic etching. Removing other portions while leaving portions located on the side surfaces.

After the floating gate forming step, a step of forming a mask layer covering the floating gate; a step of forming another interlayer insulating film covering the mask layer and the insulating film; Forming a resist mask having an overlapping opening on the other interlayer insulating film, and via the opening of the resist mask,
Etching the interlayer insulating film and the other interlayer insulating film, thereby forming a drain contact opening in the interlayer insulating film and the other interlayer insulating film; Embedding with a material, thereby forming a train contact.

According to another method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a semiconductor region, a source and a drain formed in the semiconductor region, a floating gate insulated from the semiconductor region, A method of manufacturing a non-volatile semiconductor storage device having a control gate insulated from the floating gate, wherein the step of forming the floating gate having an upper surface and side surfaces covered by an insulating layer on the semiconductor region; Forming an interlayer insulating layer covering the floating gate on the semiconductor region; forming a recess in the interlayer insulating film by selectively etching a part of the interlayer insulating film; The recess formed in the layer is filled with a conductive material, whereby the control gate made of the conductive material is placed in the recess of the interlayer insulating film. It includes a step of forming.

In one embodiment, the control gate forming step includes: forming a conductive film of the conductive material so as to cover the interlayer insulating film so as to fill the concave portion of the interlayer insulating film; Removing a portion located on the interlayer insulating film.

The step of removing a portion of the conductive film located on the interlayer insulating film may be performed using a chemical mechanical polishing method or an etch back method.

[0033] The control gate forming step may include a step of selectively growing a conductive film of the conductive material in the concave portion of the interlayer insulating film.

[0034]

(Embodiment 1) A first embodiment of a nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS.

First, reference is made to FIG. This nonvolatile semiconductor memory device is a split gate type FAMOS,
P-type single crystal silicon substrate 10 functioning as a semiconductor region
Source region 25a and drain region 2 formed therein.
5b, a floating gate 36 insulated from the substrate 10, and a control gate 14 insulated from the substrate 10 and the floating gate 36. The substrate 10 is covered with a planarized interlayer insulating layer 26 on the upper surface, and the floating gate 36 is formed of a conductive layer embedded in a groove (recess) formed in the interlayer insulating layer 26. As will be described later, the floating gate 36 of the present embodiment is formed so as to fill a groove provided in the insulating film, and the upper surface thereof has been subjected to a flattening process such as polishing or etching. The upper surface of the floating gate 36 is covered with an insulating layer 38.

More specifically, the control gate 14 and the substrate 10
A first gate insulating film 12 is interposed between the gate insulating film 12 and the gate insulating film 12 and the control gate 14 and the substrate 10 are electrically separated. The upper surface of control gate 14 is capped by nitride film 16. On the side surface of the control gate 14 on the side of the source region, there is a sidewall spacer 22a via a thin oxide film. The capacitance insulating film 32a is provided on the side surface of the control gate 14 on the drain region side. The capacitance insulating film 32a is
And the floating gate 36 are capacitively coupled. A second gate insulating film 32b is interposed between the floating gate 36 and the substrate 10, and the second gate insulating film 32b is
6 and the substrate 10 are electrically separated. However, the second
Since the thickness of the gate insulating film 32b is relatively thin, 9 to 15 nm, electrons and holes (hot carriers) having high energy can be injected from the substrate 11 into the floating gate 36 over the potential barrier. Contact holes reaching the surfaces of the source region 25a and the drain region 25b are formed in the insulating layers 26 and 38, and the contact holes are filled with the source contact 46a and the drain contact 46b. The source contact 46a and the drain contact 46b are connected to a peripheral circuit via a wiring (not shown).

Control gate 14 and buried floating gate 36
And are arranged side by side. However, as shown in FIG. 1, the embedded floating gate 36 is formed thicker than the control gate 14, and a part of the embedded floating gate 36 partially overlaps with the control gate 14. As a result, the facing area of the floating gate 36 and the control gate 14 is smaller than the facing area of the stacked nonvolatile memory, but is still maintained at a sufficient level. The upper surface of the floating gate 36 does not need to be located at a higher level than the upper surface of the nitride film 16 on the control gate 14. As will be described later, the upper surface of the floating gate 36 is formed by chemical mechanical polishing (CMP).
Therefore, when the floating gate 36 is formed to be thin, a part or all of the nitride film 16 may be etched. If the nitride film 16 is shaved in the process of forming the floating gate 36, a part of the control gate 14 may be exposed. Even if the control gate 14 is exposed at a certain stage in the manufacturing process, the problem can be solved by forming an insulating layer on the surface of the control gate 14 thereafter. If the nitride film 16 is deposited sufficiently thick,
Exposure of the control gate 14 can be avoided. Therefore, the upper surface of the control gate 14 and the upper surface of the floating gate 36 can be positioned at the same level.

Next, reference is made to FIG. FIG. 2 shows a planar layout of the nonvolatile semiconductor memory device of FIG.
The control gate 14 of the present embodiment is interconnected with the control gate of another non-volatile memory cell (not shown),
4 itself also serves as a wiring. On the other hand, the buried floating gate 36 has an isolated pattern shape, and is electrically separated for each memory cell. Source region 25a and drain region 25b are formed in active region 9 of substrate 10. Active region 9 is surrounded by element isolation 11.

The device of the present embodiment has a so-called split gate structure in which the control gate 14 and the floating gate 36 are arranged in parallel via a capacitance insulating film. The floating gate 36 functions as an information storage node, and makes the charged state correspond to "0" and "1" of information. Data reading is performed by utilizing the fact that the threshold voltage seen from the control gate 14 changes according to the amount of charge stored in the floating gate 36.

The data writing utilizes a strong lateral high electric field generated at the boundary between the “drain potential extension region” immediately below the floating gate 36 and the “inversion channel region” immediately below the control gate 14. . The channel hot electrons in a high energy state due to the lateral high electric field are injected into the oxide film, and the floating gate 3
6, a relatively high efficiency of electron injection is achieved. Such electron injection is called “source side injection”.

The data is erased by utilizing the Fowler-Nordheim (FN) type tunnel phenomenon and extracting electrons in the floating gate 36 to the drain region 25b. In order to utilize the FN tunnel phenomenon, it is necessary to form a high electric field of about 10.5 MV / cm to 11 MV / cm in the oxide film 32b.

Next, an example of an operation for writing, reading and erasing data in the nonvolatile semiconductor memory device will be briefly described.

First, at the time of data writing, a voltage of about 2.5V is applied to the control gate 14, a voltage of about 0V to the source region 25a, and a voltage of about 5V to the drain region 25b. Then, hot electrons are generated in the channel region, and the hot electrons are injected into the floating gate 36. Thus, data writing is performed.

When data is read, the source region 25 is read.
a and 3.3 V to the control gate 14 and 3.3 V to the source region 25 a and the drain region 25 b, respectively.
Is applied with a voltage of about 0V.

To erase data, the control gate 36
And a voltage of about 7 V is applied to the drain region 25b. Thereby, the electrons accumulated in the floating gate 36 are extracted to the drain region 25b via the tunnel oxide film 32b. The electrons pass through the tunnel oxide film 32b using the FN type tunnel phenomenon.

Next, FIGS. 3 (a) to 3 (e) and FIGS.
An embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described with reference to (e) and FIGS. 5 (a) to 5 (d). First, an element isolation structure not shown,
After a well structure is formed in the substrate 10 as necessary, a first gate insulating film (thickness: 5 to 10 nm) 12 is deposited. Thereafter, as shown in FIG.
Control gate 1 capped with 200 nm nitride film 16
4 is formed on the p-type silicon substrate 10. Control gate (control gate length: 250 to 400 nm) 14 of the present embodiment
Is formed by depositing a nitride film 16 on a polycrystalline silicon film (thickness: 200 to 300 nm), and then patterning the nitride film 16 and the underlying polycrystalline silicon film sequentially using lithography and etching techniques. The polycrystalline silicon film is doped with an n-type impurity.

Next, an n-type impurity-doped region 20 functioning as at least a part of the source region is formed by using lithography and ion implantation techniques. After this, the substrate 1
Oxide film (thickness: 10 to 20 n) so as to cover the entire surface of
m) Deposit 18 and a nitride film (thickness: 50 to 100 nm) 12.

As shown in FIG. 3B, by performing anisotropic dry etching on the nitride film 22 in a blanket state, the nitride film 22 is removed from the sidewall 22a.
And 22b are formed. The thickness of the sidewalls 22a and 22b is controlled by adjusting the thickness of the nitride film 22.

As shown in FIG. 3C, after a resist pattern 23 is formed by photolithography, n-type impurity ions (for example, Arsenic ions). Thus, an n-type impurity doped region 24a functioning as a part of the source region and an n-type impurity doped region 24b functioning as at least a part of the b drain region are formed. Resist pattern 2
3 exposes the region to be doped with n-type impurities,
It is formed so as to cover a region other than the region. Also, n
The ion implantation for forming the impurity doped regions 24a and 24b is performed, for example, at a dose of 1 × 10 ¹³ to 1 × 1.
It is performed under the conditions of 0 ¹⁴ cm ^-2 and an acceleration energy of 15 to 30 keV. The surface impurity concentration of n-type impurity doped regions 24a and 24b is preferably 5 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

As shown in FIG. 3D, after removing the resist pattern 23, an insulating film (thickness: 500 to 1000 nm) 26 is deposited so as to cover the entire upper surface of the substrate 10. The interlayer insulating film 26 can be formed from, for example, a non-doped silicate glass (NSG) film substantially containing no impurities, another silicon oxide film, or an organic film. The interlayer insulating film 26 may have a structure in which a plurality of types of insulating layers are stacked.

As shown in FIG. 3E, after a resist pattern 28 is formed on the interlayer insulating film 26 by photolithography, a portion of the interlayer insulating film 26 not covered by the resist pattern 28 is dry-etched. To remove. The resist pattern 28 is formed to have an opening 28a that defines the shape and position of the floating gate 36. As a result of removing the portion of the interlayer insulating film 26 exposed through the opening 28a of the resist pattern 28, a groove (recess) 30 is formed in the interlayer insulating film 26. The groove 30 has a width of, for example, 400 to 1000 n.
m, having a size of 1500 to 3000 nm in length and reaching the surface of the substrate 10. After the dry etching, one (22b) of the pair of sidewalls 22a and 22b and a part of the nitride film 16 are exposed in the groove. In etching the interlayer insulating film 26, the control gate 14 is not etched at all because the nitride films (16 and 22b) functioning as etch stops cover the control gate 14. The kind of the etchant used for etching the interlayer insulating film 26 is selected so that the etching rate of the nitride film with respect to the etchant is sufficiently smaller than the etching rate of the oxide film.

Next, as shown in FIG. 4A, the side wall 22 exposed in the groove 30 is formed by chemical dry etching which is one of the isotropic etching techniques.
b is removed. Since the sidewall 22b of the present embodiment is formed of a nitride film, the nitride film is
Dry etching is performed under conditions of preferentially etching the substrate 10 and the substrate 10.

As shown in FIG. 4B, the oxide film 18 on the side wall of the control gate 14 is wet-etched.
Is removed. For this etching, for example, hydrofluoric acid is used as an etchant.

As shown in FIG. 4C, an insulating film (thickness: 10 to 15 nm) 32 made of SiO _{2 is} formed on the silicon surface exposed in the groove 30 by a thermal oxidation method. As a result, the insulating film 32 is formed on the side surface of the control gate 14 and on the surface of the substrate 10. The insulating film 32 insulates and separates the control gate 14 from the floating gate 36 and also insulates and separates the silicon substrate 10 from the floating gate 36. The control gate 14 and the floating gate 36 of the insulating film 32
The portion located between the floating gate 36 and the silicon substrate 10 functions as a capacitive insulating film 32a (see FIG. 1).
Is located between the tunnel insulating film 32b (FIG. 1).
Function). Note that the insulating film 32 may be formed by a method other than the thermal oxidation method (for example, a CVD method). In FIG. 4C, the control gate 14 and the floating gate 36
And between the silicon substrate 10 and the floating gate 36, one type of insulating film 32 is provided. An insulating film (capacitive insulating film) formed between the control gate 14 and the floating gate 36 is provided. It is not necessary to match the type of 32a) with the type of insulating film (tunnel insulating film 32b) formed between the silicon substrate 10 and the floating gate 36. When the control gate 14 is formed from a conductive thin film other than the polycrystalline silicon film, it is difficult to use a thermal oxide film as the capacitor insulating film. It will be used as an insulating film. Alternatively, in the process step shown in FIG. 4B, a portion of the oxide film 18 located on the side surface of the control gate 14 is left,
That part may be used as at least a part of the capacitive insulating film.

As shown in FIG. 4D, a polycrystalline silicon film (thickness: 300
After depositing (.about.500 nm) 34, the upper portion of the polycrystalline silicon film 34 is etched by a planarization method by CMP, and a portion of the polycrystalline silicon film 34 located on the upper surface of the interlayer insulating film 26 is removed. As a result, as shown in FIG. 4E, the inside of the groove is filled with the remaining portion of the polysilicon film 34, and the floating gate 36 is formed from that portion of the polysilicon film 34. Floating gate 36
Is defined by the shape and position of the groove (recess) formed in the interlayer insulating film 26. In addition,
The floating gate 36 may be formed of a conductive thin film other than the polycrystalline silicon film 34 (for example, a film made of tungsten (W), titanium (Ti), aluminum (Al), or the like).

As shown in FIG. 5A, after an insulating film (hereinafter referred to as "oxide film") 38 of silicon dioxide having a thickness of, for example, 250 to 500 nm is deposited on the interlayer insulating film 26, As shown in FIG. 5B, openings 26a and 26b for source / drain contacts are provided in oxide film 38 and interlayer insulating film 26 by photolithography and etching techniques. Thereafter, for example, arsenic ions of 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² are accelerated at an acceleration energy of 30 to 40 keV to form openings 2 in the interlayer insulating film 26.
N ⁺ -type impurity-doped regions 42a and 42b are formed in the substrate 10 by implanting into the substrate surface regions located on the bottom surfaces of 6a and 26b.

As shown in FIG. 5C, after a tungsten film (thickness: 500 to 700 nm) 44 is deposited so as to cover the entire surface of the substrate, the tungsten film 44 is planarized by the CMP method. I do. Thus, FIG.
As shown in (d), the openings 26a and 26b of the interlayer insulating film 26 are buried with the tungsten film 44, and the source contact part 46a and the drain contact part 46b are formed. After that, a wiring forming step and another interlayer insulating film forming step are performed.

The structure of the source / drain regions 25a and 25b of the device shown in FIG. 5D is different from the structure of the source / drain regions of the device shown in FIG. Reference signs “24a” and “42” in FIG.
The element indicated by "a" is simply described as "drain region 25b" in FIG. On the other hand, elements indicated by reference numerals “24b” and “42b” in FIG. 5D are simply described as “source region 25a” in FIG. The structure of the source / drain regions is shown in FIGS.
It is not limited to the one shown in (d). Using a known impurity doping technique, a suitable impurity diffusion structure for improving the efficiency of carrier injection into the floating gate 36 can be appropriately formed in the semiconductor substrate.

According to the manufacturing method of this embodiment, after the trench of the insulating film is filled with the conductive material, the floating gate is formed by using a planarization process such as CMP or etching. The upper surface of the insulating film to be covered is also flattened, thereby greatly facilitating the formation of wiring.

(Embodiment 2) Next, FIGS. 6 (a) to 6 (c)
A second embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG. Until the formation of the buried floating gate 36, the same steps as those described in the first embodiment are performed, and the description thereof will not be repeated here. The manufacturing process after forming the embedded floating gate 36 will be described below.

First, reference is made to FIG. An oxide film (thickness: 10 to 20 nm) so as to cover the entire surface of the substrate 10
After forming on the interlayer insulating film 26 and the buried floating gate 36, a polycrystalline silicon film 50 is deposited on the oxide film 48.

As shown in FIG. 6B, a resist pattern 52 is formed on the polycrystalline silicon film 50 by using a photolithography technique. Resist pattern 52
Is formed so as to cover the buried floating gate 36.
More precisely, the resist pattern 52
4 are formed in a wiring shape substantially in parallel with each other, and the resist pattern 52 includes a plurality of embedded floating gates 3 arranged in a line.
6 is formed.

As shown in FIG. 6C, dry etching is performed using the resist pattern 52 as an etching mask to remove the erase gate 5 from the polycrystalline silicon film 50.
4 is formed. Each erase gate 54 extends substantially parallel to the control gate 14 and covers a plurality of buried floating gates 36 arranged in a row.

In the step of forming the erase gate 54,
At the same time, other interconnection lines may be formed.

According to the present embodiment, the buried floating gate 36 in which the erase gate 54 for erasing data is flattened is provided.
Placed on top. Since the base of the erase gate 54 is flat, the erase gate 54 is formed stably with little risk of short-circuit and disconnection.

The material of oxide film 48 is not limited to a silicon dioxide film. A silicon nitride (Si ₃ N ₄ ) film or a tantalum pentoxide (Ta ₂ O ₅ ) film may be used as long as the insulating film waits for a structure suitable for the erasing operation. The erase gate 5
The material of No. 4 is not limited to polycrystalline silicon, and may be formed of another conductive material.

(Embodiment 3) Next, FIGS. 7 (a) to 7 (c)
A third embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. 8A to 8C. Until the formation of the buried floating gate 36, the same steps as those described in the first embodiment are performed, and the description thereof will not be repeated here. The manufacturing method after the formation of the buried floating gate 36 will be described below.

First, reference is made to FIG. After a nitride film (thickness: 50 to 200 nm) 56 is formed on the interlayer insulating film 26 and the buried floating gate 36 so as to cover the entire surface of the p-type single crystal silicon substrate 10, a resist pattern 58 is formed by using a lithography technique. It is formed on the nitride film 56.

By performing etching using the resist pattern 51 as an etching mask, a floating gate cover 60 is formed from the nitride film 56 as shown in FIG. 7B. This cover 60 functions as an etch stop during etching described later,
It serves to protect the buried floating gate 36 from etching. Therefore, the shape and position of the cover 60 are determined so that the cover 60 completely covers the embedded floating gate 36. The material and thickness of the cover 60 are selected so that the floating gate 36 can be sufficiently protected against etching described later.

As shown in FIG. 7C, the interlayer insulating film 62 is covered with the interlayer insulating film 26 so as to cover the entire surface of the substrate 10.
And a resist pattern 64 is deposited on the floating gate cover 53 by using a lithography technique.
2 is formed. The resist pattern 64 has openings 64a and 64 for forming source / drain contacts.
b. At this time, the drain contact opening 64b is formed so as to overlap the buried floating gate 36. By performing dry etching using the resist pattern 64 as an etching mask, as shown in FIG. 8A, openings 66a and 66b for source / drain contacts are formed in the interlayer insulating films 26 and 62 made of SiO _2.
Formed. Since this dry etching is performed under the condition that the etching rate of SiO ₂ is higher than the etching rate of the nitride film, as described above, the cover 60 on the embedded floating gate 36 functions as an etching stop, and FIG. Is obtained. Thereafter, for example, arsenic ions of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² are implanted with an acceleration energy of 10 to 25 keV to form interlayer insulating films 26 and 6
The n ⁺ -type impurity-doped regions 42a and 42b are formed in the substrate 10 by injecting them into the substrate surface regions located at the bottom surfaces of the two openings 66a and 66b.

As shown in FIG. 8B, after the tungsten film 68 is deposited on the interlayer insulating film 62 so as to cover the entire surface of the substrate 10, the tungsten film 68 is planarized by the CMP method. Thus, as shown in FIG. 8C, a source contact portion 70a and a drain contact portion 70b are formed.

According to the present embodiment, the drain electrode 70b
However, a structure that easily overlaps the buried floating gate 36 via a relatively thin insulating film (cover 60) can be easily obtained. Such a structure improves the capacitive coupling between the drain electrode 70b and the floating gate 36, so that the writing efficiency can be improved.

The material of the cover 60 is not limited to a nitride film. Any material can be used as long as it can function as a stopper for the etching of the interlayer insulating films 26 and 62.

(Embodiment 4) Next, FIGS. 9 (a) to 9 (d)
A fourth embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 10 (a) and 10 (b).

Since the same steps as those described in the first embodiment are performed until the step shown in FIG. 3E, the description will not be repeated here. The manufacturing process after the opening 30 of FIG. 3E is formed in the interlayer insulating film 26 will be described below.

First, reference is made to FIG. FIG. 9 (a)
Is subjected to a dry etching process. This dry etching is performed under conditions for selectively etching the nitride film. As a result, the surface of the sidewall 22b is partially etched, and as shown in FIG. 9B, a sidewall 72 whose width is relatively reduced as compared with the sidewall 22b is obtained. Thereafter, ions of an n-type impurity such as arsenic are implanted into the substrate 10 before removing the sidewall 72. For example, the dose is 1 ×
10 ^{12 -1} × 10 ¹³ cm ^-2 , acceleration energy 10-20
keV. By this ion implantation, the n ⁻ -type impurity-doped region 74 can be formed at a part of the groove bottom.

After removing the sidewalls 72 and the oxide film 18 as shown in FIG. 9C, an insulating film 76 is formed by thermal oxidation as shown in FIG. 9D.

As shown in FIG. 10A, the substrate 10
Polycrystalline silicon film (thickness: 50) so as to cover the entire surface of
After depositing (0 to 700 nm) 34, the upper portion of the polycrystalline silicon film 34 is etched by a planarization method by CMP, and a portion of the polycrystalline silicon film 34 located on the upper surface of the interlayer insulating film 26 is removed. As a result, FIG.
As shown in (2), the inside of the trench is filled with the remaining portion of the polycrystalline silicon film 31, and a buried floating gate 36 is formed from that portion of the polycrystalline silicon film 31. Subsequent steps may be performed in the same manner as the steps described in any of the above embodiments.

According to the present embodiment, there is an advantage that the impurity concentration of the drain region located below the floating gate 36 can be easily adjusted to a desired level. In addition, since the position of the drain region on the channel region side can be defined by etching the sidewall spacers 22b without using a special mask, it is possible to form a low impurity concentration drain structure with high reproducibility. . In addition, n ^-
Providing the low-concentration impurity region of the type impurity doped region 74 has an advantage of suppressing the short channel effect.

(Embodiment 5) The present invention has been described with reference to a nonvolatile semiconductor memory device having a buried floating gate. Hereinafter, a nonvolatile semiconductor memory device having a buried control gate will be described. FIG. 11 (a)
-(D), FIGS. 12 (a)-(c) and 13 (a)-
(C) An embodiment of such a nonvolatile semiconductor memory device will be described.

First, an element isolation structure (not shown)
After a well structure is formed in the p-type silicon substrate 80 as necessary, a gate insulating film (thickness: 9 to 15 nm) 82 is deposited on the substrate 80. Thereafter, as shown in FIG. 11A, a floating gate 84 made of a polycrystalline silicon film having a thickness of 200 to 300 nm is formed on the substrate 80. The polycrystalline silicon film is doped with an n-type impurity.

As shown in FIG. 11B, an oxide film (thickness: 10 to 20 nm) 86 covering the floating gate 84 is formed on the substrate 80. As shown in FIG.
An interlayer insulating film 88 made of borophosphosilicate glass (BPSG) is deposited on the oxide film 86 by the CVD method so as to cover the floating gate 84. Then, the opening 9
A resist 90 having 0 'is formed on the interlayer insulating film 88. Openings 90 'define the control gate pattern. By etching a portion of the interlayer insulating film 88 exposed through the opening 90 ′ of the resist 90, FIG.
As shown in (c), a groove 88 ′ is formed in the interlayer insulating film 88. The groove 88 'is formed so as to partially straddle the floating gate 86, and the oxide film 86 is exposed at the bottom of the groove 88'. At the time of etching for forming the groove 88 ′,
Oxide film 86 functions as an etch stop.

As shown in FIG. 12A, the substrate 80
Polycrystalline silicon film (thickness: 50) so as to cover the entire surface of
After depositing (0 to 700 nm) 92, the upper portion of the polycrystalline silicon film 92 is etched by a planarization method by CMP, and a portion of the polycrystalline silicon film 92 located on the upper surface of the interlayer insulating film 88 is removed. As a result, FIG.
As shown in (2), the inside of the groove is filled with the remaining portion of the polysilicon film 92, and the control gate 94 is formed from that portion of the polysilicon film 92. Control gate 9
The shape and position of 4 are defined by the shape and position of a groove (recess) 88 ′ formed in the interlayer insulating film 88.
As described above, the control gate 94 of the present embodiment is formed so as to fill the groove, and the upper surface thereof has been subjected to a flattening process such as polishing or etching. The control gate 94
Is a conductive thin film other than the polycrystalline silicon film 92 (for example,
(A film made of tungsten (W), titanium (Ti), aluminum (Al), or the like).

As shown in FIG. 12C, the oxide film 9
6 is deposited on the insulating film 88, and a resist 98 having openings 98a and 98b for source / drain contacts is formed on the insulating film 96 by photolithography.
Form on top. After that, as shown in FIG.
Openings 100a and 100b for source / drain contacts are provided in insulating films 88 and 96 by an etching technique. Thereafter, for example, 1 × 10 ^{15 to} 5 × 1
Arsenic ions of 0 ¹⁵ cm ^-2 are accelerated at an energy of 30 to 50 ke.
V, openings 100a and 100a in insulating films 88 and 96
Implanted into the substrate surface region located at the bottom surface of n ⁺ -type impurity doped regions 101a and 101b.
Is formed in the substrate 80.

As shown in FIG. 13B, a tungsten film (thickness: 500 to 700 nm) 102 is
Is deposited so as to cover the entire surface of the substrate, and then the tungsten film 34 is planarized by the CMP method. Thus, as shown in FIG.
02, the openings 100a and 100b of the insulating films 88 and 96 are buried, and the source contact 104
a and the drain contact portion 104b are formed.

FIG. 14 shows a plan layout of the nonvolatile semiconductor memory device of this embodiment. The embedded control gate 94 of this embodiment is interconnected with the control gate of another non-volatile memory cell (not shown), and the control gate 94 itself also serves as a wiring. On the other hand, the floating gate 84
Has an isolated pattern shape and is electrically isolated for each memory cell. The source region 104a and the drain region 104b are formed in the active region of the substrate 80.

According to the manufacturing method of this embodiment, a nonvolatile semiconductor memory device in which the control gate is embedded in the groove of the interlayer insulating film can be easily manufactured. The device manufactured in this way is
Like the nonvolatile semiconductor memory device having a buried floating gate, it has a structure in which the gate step is reduced, so that it is easy to form an upper layer wiring which is less likely to cause a short circuit or the like.
In each of the above embodiments, the trench formed in the interlayer insulating film is buried with a conductive material film, and then a planarization step by CMP is performed to form a buried gate. Etchback using an etching technique may be performed. Further, a conductive film may be selectively grown in the groove of the interlayer insulating film by using a selective CVD method or the like.

Further, the material of the sidewall spacer and the interlayer insulating film is not limited to the materials described in the above embodiment. For example, when the side wall spacer is BPSG
(Borophosphosilicate glass) film, and the interlayer insulating film may be formed from a low dielectric constant organic film.

[0089]

According to the nonvolatile semiconductor memory device of the present invention, one of the control gate and the floating gate is formed so as to be buried in the groove of the insulating layer. And it is extremely easy to form an upper wiring to cover them. for that reason,
According to the present invention, it is possible to provide a nonvolatile semiconductor memory device with a higher degree of integration with a high yield.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a plan layout view of the device of FIG. 1;

FIGS. 3A to 3E are process cross-sectional views illustrating a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 4A to 4E are process cross-sectional views illustrating a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 5A to 5D are process cross-sectional views illustrating a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 6A to 6C are process cross-sectional views illustrating a second embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 7A to 7C are process cross-sectional views illustrating a third embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 8A to 8C are process cross-sectional views illustrating a third embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 9A to 9D are process cross-sectional views illustrating a fourth embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 10A and 10B are cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIGS. 11A to 11D are process cross-sectional views illustrating a fifth embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 12A to 12C are process cross-sectional views illustrating a fifth embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIGS. 13A to 13C are process cross-sectional views for explaining a fifth embodiment of the method for manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 14 is a plan layout diagram of a nonvolatile semiconductor memory device having an embedded control gate according to the present invention.

15A is a sectional view showing a first conventional example of a nonvolatile semiconductor memory device, FIG. 15B is a sectional view showing a second conventional example of a nonvolatile semiconductor memory device, and FIG. ) Are their equivalent circuit diagrams.

[Explanation of symbols]

Reference Signs List 10 p-type silicon substrate 12 gate insulating film 14 control gate 16 nitride film 18 oxide film 20 22 a, 22 b sidewall 24 a, 24 b n-type impurity doped region 26 insulating film 28 resist pattern 30 groove (recess) 32 insulating film 34 polycrystalline silicon Film 36 floating gate 38 insulating film 40 resist pattern 42a, 42b n ⁺ type impurity doped region 44 tungsten film 46a source contact portion and 46b drain contact portion 48 insulating film 50 polycrystalline silicon film 52 resist pattern 54 erase gate

Continuing from the front page (72) Inventor Hiromasa Fujimoto 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Junichi Kato 1006 Okadoma Kadoma, Kadoma City Osaka Pref. Atsushi Hori 1006 Kadoma, Kazuma, Kadoma, Osaka Prefecture, Japan Matsushita Electric Industrial Co., Ltd. (72) Inventor Shinji Odanaka 1006, Kadoma, Kazuma, Kadoma, Osaka Pref. , Wappingers Falls, Old Hopewell Road 140, Halo LSI Design and Device Technology, Inc. F-Term (in reference) 5F001 AA21 AA32 AB03 AB07 AB08 AC02 AC61 AD12 AD41 AD51 AD52 AE02 AE03 AE08 AG02 AG12 AG21 5F083 EP14 EP14 EP30 ER02 ER06 ER09 ER11 ER14 ER15 ER30 GA09 GA27 JA06 JA19 PR36 PR40

Claims (23)

[Claims] A semiconductor region, a source and a drain formed in the semiconductor region, a floating gate insulated from the semiconductor region, and a control gate insulated from the semiconductor region and the floating gate. A non-volatile semiconductor memory device, further comprising an interlayer insulating layer covering the semiconductor region and having a flattened upper surface, wherein at least one of the floating gate and the control gate is formed in a recess formed in the interlayer insulating layer. Embedded non-volatile semiconductor storage device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein an upper surface of at least one of said floating gate and said control gate is polished together with an upper surface of said interlayer insulating layer. 3. The nonvolatile semiconductor memory device according to claim 1, wherein an upper surface of the gate buried in the recess of the interlayer insulating layer is located at substantially the same level as an upper surface of the interlayer insulating layer. . 4. The nonvolatile semiconductor memory device according to claim 1, wherein said floating gate is buried in said concave portion of said interlayer insulating layer. 5. An erase gate covering the floating gate and the interlayer insulating film, and an erase gate formed on the other insulating film and including a portion facing the floating gate via the other insulating film. The nonvolatile semiconductor memory device according to claim 4, further comprising: 6. A capacitor insulating film formed on the floating gate, and a drain electrode electrically connected to the drain and capacitively coupled to the floating gate via the capacitor insulating film. The nonvolatile semiconductor memory device according to claim 4, further comprising: 7. The nonvolatile semiconductor memory device according to claim 6, wherein said capacitance insulating film is formed not only on a side surface but also on an upper surface of said floating gate. 8. The semiconductor device further comprising another interlayer insulating film formed on the interlayer insulating film, wherein the drain electrode penetrates the interlayer insulating film and the other interlayer insulating film until the drain electrode reaches the semiconductor region. The nonvolatile semiconductor memory device according to claim 6, which is embedded in a unit. 9. The device according to claim 1, wherein the drain region includes a plurality of impurity diffusion layers, and at least a part of the drain region overlaps a part of the floating gate. Non-volatile semiconductor storage device. 10. A semiconductor device comprising: a semiconductor region; a source and a drain formed in the semiconductor region; a floating gate insulated from the semiconductor region; and a control gate insulated from the semiconductor region and the floating gate. A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming, on a semiconductor region, the control gate having a top surface and side surfaces covered with an insulating layer; and forming an interlayer insulating layer covering the control gate on the semiconductor region. Forming a recess in the interlayer insulating film by selectively etching a part of the interlayer insulating film; filling the recess formed in the interlayer insulating layer with a conductive material; Thereby forming the floating gate made of the conductive material in the recess of the interlayer insulating film. Method of manufacturing location. 11. The floating gate forming step includes: forming a conductive film of the conductive material on the interlayer insulating film so as to fill the concave portion of the interlayer insulating film; 11. The method of manufacturing a semiconductor device according to claim 10, further comprising: removing a portion located on an upper surface of the semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 10, wherein said floating gate forming step includes a step of selectively growing a conductive film of said conductive material in said concave portion of said interlayer insulating film. 13. A step of flattening an upper surface of the interlayer insulating film before the step of forming a recess in the interlayer insulating film by selectively etching a part of the interlayer insulating film. The method of manufacturing a semiconductor device according to claim 10. 14. The step of forming the recess in the interlayer insulating film, the step of forming a resist mask having an opening defining the recess at a position overlapping the control gate on a planar layout; The method of manufacturing a semiconductor device according to claim 10, further comprising: etching a part of the interlayer insulating film through the opening of the resist mask to form the recess so as to reach a surface of the semiconductor region. Method. 15. The semiconductor according to claim 14, further comprising, after forming the recess in the interlayer insulating film, forming a tunnel insulating film on the surface of the semiconductor region exposed at the bottom of the recess. Device manufacturing method. 16. After forming the concave portion in the interlayer insulating film, impurity ions are implanted into the surface of the semiconductor region located at the bottom of the concave portion, thereby functioning as a part of a drain region. The method for manufacturing a semiconductor device according to claim 14, further comprising a doping step of forming an impurity-doped region. 17. The method according to claim 16, further comprising, after the doping step, removing the insulating layer covering a side surface of the control gate. 18. The method according to claim 17, further comprising, after removing the insulating layer covering the side surface of the control gate, forming a tunnel insulating film on the surface of the semiconductor region exposed at the bottom of the recess. Of manufacturing a semiconductor device. 19. The method according to claim 19, wherein the step of forming the control gate having the top surface and the side surface covered with an insulating layer on the semiconductor region includes: forming the control gate having the top surface covered with an insulating layer; The method of manufacturing a semiconductor device according to claim 10, further comprising: covering the side surface of the control gate with an insulating layer. 20. A step of covering the side surface of the control gate with an insulating layer, a step of forming an insulating film covering the control gate, and anisotropic etching to cover the side surface of the control gate in the insulating film. 20. The method of manufacturing a semiconductor device according to claim 19, further comprising: removing a remaining portion while leaving the portion located. 21. After the floating gate forming step, a step of forming a mask layer covering the floating gate; a step of forming another interlayer insulating film covering the mask layer and the insulating film; Forming a resist mask having an opening that partially overlaps on the other interlayer insulating film, and etching the interlayer insulating film and the other interlayer insulating film through the opening of the resist mask. Forming a drain contact opening in the interlayer insulating film and the other interlayer insulating film, and filling the inside of the drain contact opening with a conductive material, thereby forming a train contact; The method of manufacturing a semiconductor device according to claim 10, further comprising: 22. A semiconductor device comprising: a semiconductor region; a source and a drain formed in the semiconductor region; a floating gate insulated from the semiconductor region; and a control gate insulated from the semiconductor region and the floating gate. A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a floating gate having an upper surface and side surfaces covered by an insulating layer on the semiconductor region; and forming an interlayer insulating layer covering the floating gate on the semiconductor region. Forming a recess in the interlayer insulating film by selectively etching a part of the interlayer insulating film; filling the recess formed in the interlayer insulating layer with a conductive material; Forming the control gate made of the conductive material in the concave portion of the interlayer insulating film thereby. 23. The control gate forming step, comprising: forming a film of the conductive material so as to cover the interlayer insulating film so as to fill the concave portion of the interlayer insulating film; 23. The method of manufacturing a semiconductor device according to claim 22, further comprising: removing a portion located on the interlayer insulating film.