JP2000348490A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device which generates the timing of a data transfer according to its own characteristic. SOLUTION: This memory device 1 performs an internal operation following an access request in synchronization with the oscillation output of a built-in self-excited oscillation circuit 102 with respect to requests (200, 201, 202) from a CPU 2, and it outputs to the CPU a response request 103 with respect to the access requests. The CPU performs the access requests with respect to the memory device, it receives the response request 103 from the memory device which performs the access requests, and it fetches data from the outside or outputs data to the outside according to the kind of an access request in synchronization with the response request. A data interface between the memory device and the CPU is realized by mutually equal access requests and by response requests with respect to the access requests. A data transfer is realized easily in the limit time of characteristics of the memory device and the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling the transfer of various information such as instruction information and data information between a memory or a peripheral circuit and a data processor, and a peripheral circuit, a data processor and a method utilizing the method. The present invention relates to a data processing system, and particularly relates to a technology particularly effective when applied to a data transfer control technology between a data processor and a memory.
In this specification, a data processor is a CPU (Central Processing Unit), a microprocessor, a microcomputer, a single-chip microcomputer, a digital signal processor,
It is a general term for a controller such as a direct memory access controller.

[0002]

2. Description of the Related Art A conventional CPU is described in, for example, "Hitachi 32-bit RISC Processor PA / 10HD69010 Hardware Manual -Provisional Edition": ADJ-602-06
As described in No. 5], there is a type in which one or a plurality of cache memories are built in a chip due to various conditions such as LSI performance, price, and manufacturing process technology level.
These CPUs are connected to many memories and input / output circuits (I / O) on a mounting board to form a system. The operating clock is the basis for system operation.
(System clock) is generally used. Normally, peripheral circuits such as memory and input / output circuits that make up the system have their own functions and characteristics.
The operation procedure, the response time, or the operation speed is also different. Needless to say, the CPU interface of the memory and the input / output circuit often differ in function, timing, etc., though they have similarities.

[0005] As described above, a memory controller is used for a memory, and an I / O controller is used for an input / output circuit for the difference in function, operation speed, interface specification and the like. The functions of such a controller are roughly divided into the following two points.

The first function is to notify the memory or the input / output circuit of the memory or the input / output circuit which the CPU has selected, and to start the data transfer. The function is grasped as so-called chip selection or chip enable control. can do. For example, a logic is taken between signals indicating the address and the type of access, and a pulse or level signal is formed using an operation clock or the like, and only signals connected to the selected memory or input / output circuit are set to true (Active). I do.

Second, the operation clock is counted by a counter or the like to generate a signal for requesting the CPU to extend the access period in units of the operation clock such as wait or ready, and this signal is checked by the CPU for each operation clock. This function absorbs the difference in timing or the difference in operation speed between the CPU and the memory or the peripheral circuit by the rule that the data transfer is performed, and reliably realizes data transfer. This function is a so-called wait state control function.

[0006]

However, it has been clarified by the present inventors that the above-mentioned wait state control by the controller has the following problems.

(1) Since the length of the data transfer time extended by the wait state is always determined in units of the operation clock of the system, the inherent performance of the memory and the peripheral circuits cannot be sufficiently obtained. Moreover,
It is practically impossible to design a system using the performance based on the design data submitted by the manufacturer / seller for the memory and input / output circuits in an extreme state. In such a case, a dead time always occurs in the data transfer, and the data transfer efficiency on the data bus is inevitably reduced. This problem occurs not only when the system is configured on the mounting board, that is, when the connection between the memory and the input / output circuit and the CPU is performed by a bus on the mounting board, but also when the CPU and the memory are formed on the same semiconductor chip. This is also true to some extent.
In other words, if the optimization design is performed in consideration of the electrical characteristics and the arrangement of the circuit elements, the controller and the memory can perform data transfer with respect to the operation clock of the controller without waste, but in actual circuit design, Considering the characteristics of each logic circuit block, delicate timing must be performed inside the chip, which is not always easy.

(2) When there are a plurality of memories and input / output circuits, the wait state control needs to be designed by a system designer for each memory or input / output circuit due to differences in functions (including protocols) and performance. It takes a lot of trouble.

(3) Circuit parts for wait state control are required for the number of memories and input / output circuits, so that the system is complicated, the number of parts is increased, the speed of the signal system is increased, and the speed and size are reduced. , Causing a negative effect on cost reduction and the like.

(4) As described in the above (1), the wait state control cannot sufficiently bring out the inherent performance of the memory and the peripheral circuit, and there is a limit to the high-speed operation. For this reason, it is also possible to connect all or a memory or an input / output circuit having a high effect on system efficiency without wait state control. However, at that time, if the operation clock of the controller is suppressed in accordance with the characteristics such as the operation speed of the memory and the input / output circuit, the operation clock of the controller such as the CPU tends to be faster, and the value of the system is reduced. Would. Conversely, if a high-speed memory or input / output circuit is used in accordance with the operation clock of the controller, the system price will rise extremely.

As described above, in the conventional method in which the data transfer timing between the CPU and the peripheral circuit is generated from the operation clock of the CPU or the system, the data transfer that fully utilizes the original performance of the peripheral circuit such as a memory is realized. I can't. That is, the wait signal is set to CP at an integer multiple of the operation clock based on the characteristics of the peripheral circuit.
The inventor of the present invention determined that it would be difficult to expect a fundamental increase in speed if the CPU and peripheral circuits were connected by a wait state control function emphasizing reliable operation.

An object of the present invention is to provide a technique capable of performing data transfer by sufficiently exhibiting the original characteristics of a peripheral circuit such as a memory. It is another object of the present invention to provide a peripheral circuit which generates data transfer timing according to its own characteristics. It is still another object of the present invention to provide a data processor capable of efficiently performing data transfer with such a peripheral circuit. Another object of the present invention is to provide a data processing system capable of sufficiently exhibiting the original characteristics of a peripheral circuit such as a memory and performing high-speed data transfer with a data processor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, as typically shown in FIG. 1, the peripheral circuit (1) includes a data processor (2)
In response to an access request (200, 201, 202) from the device, an internal operation according to the access request is performed in synchronization with the oscillation output of the self-excited oscillation circuit (102) incorporated therein, and in synchronization with the internal operation. A configuration is employed in which a response request (103) to the access request is output to the data processor. The data processor issues an access request to a required peripheral circuit, receives a response request from the peripheral circuit that made the access request, and fetches data from the outside in synchronization with the request in accordance with the type of the access request or A configuration for outputting data to the outside is adopted.

The data transfer between the data processor and the peripheral circuit is controlled by the data processor making an access request to the peripheral circuit and the oscillation of the self-excited oscillation circuit incorporated in the requested peripheral circuit. A process of performing an internal operation according to the access request in synchronization with the output, a process of outputting a response request to the data processor to the data processor in synchronization with the internal operation of the access-requested peripheral circuit, The data processor that has received the response request synchronously fetches data from the outside in accordance with the type of the access request or performs a process of outputting data to the outside.

In order to realize the above-mentioned means by minimizing the number of additional circuits to the existing data processor and peripheral circuit configuration, the access request indicates the peripheral circuit to be selected as an access target and the data transfer direction. The response request is made by one signal (1) changed in synchronization with the internal operation of the peripheral circuit.
03).

In order to relatively easily configure a peripheral circuit having the above-described functions, an access cycle signal (1013) for internal operation in response to an access request from a data processor, as typically shown in FIG. The self-excited oscillation circuit (1
And an external terminal (AC) for outputting the access cycle signal to the outside as the response request.
And an internal timing generation circuit (1011) for generating an internal operation timing signal in synchronization with the access cycle signal (103) to constitute a peripheral circuit.

When such a peripheral circuit is configured as a memory capable of burst reading (continuous data reading of a plurality of words), as shown in FIG. 6, the number of words of continuous data reading from the memory cell array is set to the above value. A counting circuit (105) for counting based on a change in the access cycle signal and stopping the oscillation operation of the self-excited oscillation circuit when the count result reaches a predetermined count value may be further added. At this time, in order to make the number of continuous data read words programmable, as shown in FIG. 12 as a representative, the counting circuit includes a parameter register ( 10
51) is provided. When the counting circuit has a storage stage corresponding to the number of counted bits, the parameter register can be preset and can be positioned as a substantial parameter register.

In the data processor having the above-described functions, in order to transfer data having different transfer speeds between the internal unit and the outside at a high speed or efficiently, it is necessary to use FIG.
Buffer memory having an asynchronous port (2064) capable of writing and reading based on the response request, and a synchronous port (2065) capable of writing and reading in synchronization with an internal operation clock, as shown in FIG. (20
6) is adopted. The synchronous port of the buffer memory is connected to an arithmetic circuit or a register as an internal unit, and the asynchronous port of the buffer memory is connected to an input / output buffer circuit (205) that interfaces with the outside. At this time, in order to allow the data transferred from the peripheral circuit to the buffer memory to be promptly provided to the processing of the internal unit (204), the buffer memory includes the number of consecutive read accesses requested by the access control circuit to the peripheral circuit. A counting circuit (2066) for detecting the read request from the number of changes in the response request, and using the count circuit as the information (AND gate representatively shown in FIG. 9) indicating the completion of the read data acquisition by the access request. 2063
(R5 output information) may be provided to the central processing unit. The buffer memory is not limited to a complete dual port, and the uniport buffer memory may be apparently used as a dual port in a time division manner.

When the data processor is interfaced with a plurality of different types of peripheral circuits, as shown in FIG. 14, the input terminal of a single response request in the data processor is connected to the response request in each peripheral circuit. Are connected, for example, via an OR gate or wired-OR, such that the output terminals of the two terminals share.

[0022] For example, 1 /
To interface the same peripheral circuit having a 2n-bit multi-bit input / output function with a data processor, the data processor can write and read based on a response request, as typically shown in FIG. It is sufficient to provide a plurality of buffer memories (206U, 206L) each having an asynchronous port and a synchronous port that can write and read in synchronization with an internal operation clock.

[0023]

According to the above means, the peripheral circuit is operated in synchronization with the oscillation output of its own built-in self-oscillation circuit, and is asynchronous with the operation clock signal of the data processor which issues an access request to the peripheral circuit. It is operated with. In this connection, the data interface between them is realized by mutually equal access requests and corresponding response requests. This means that the series of data transfer times, which was conventionally limited to an integral multiple of the basic operation clock of the data processor, depends on the intrinsic self-oscillation frequency generated according to the operating speed and other characteristics of peripheral circuits such as memory. It is determined according to the clock cycle of the response request. Therefore, data transfer in the time limit of the characteristic of each of the peripheral circuit and the data processor can be easily realized. In other words, the wasted time generated for synchronization with the operation clock of the data processor, which is a conventional problem, is reduced. Furthermore, a wait state control circuit or the like for interfacing the data processor with each peripheral circuit is not required, and the circuit connection means can be simplified.

A data processor having on-chip a buffer memory interfaced with a peripheral circuit absorbs a difference in data transfer speed between an internal unit of the data processor and the outside, and reads data or write data according to an access request. Does not require sequential waiting time.

[0025]

FIG. 1 shows a state in which a CPU as an embodiment of a data processor according to the present invention and a memory as an embodiment of a peripheral circuit according to the present invention are connected.

The memory 1 shown in FIG. 1 includes a memory cell array 100 and an access cycle control unit 101 shown on a single semiconductor substrate, and a data processor 2.
In response to an access request (200, 201, 202) from the device, a read operation or a write operation according to the access request is performed in synchronization with the oscillation output of the self-excited oscillation circuit 102 incorporated therein, and the internal operation is synchronized. Request to the data processor 2 in response to the access request (10
3) is output.

The CPU 2 shown in FIG. 1 includes an arithmetic circuit 204, a buffer memory 206 in which one port is coupled to the arithmetic circuit 204, and a buffer memory 20 as a representative.
6, an input / output buffer circuit 205 coupled to the external data bus 211, an access control circuit 207 for making an access request to the external memory 1 and other peripheral circuits (not shown), and an instruction execution sequence control circuit. A central control unit 208 for controlling the operation of the entire central processing unit such as an interrupt control circuit is provided on one semiconductor substrate.
Access requests (200,
201, 202) and receives a response request (103) from a peripheral circuit that has made the access request, for example, the memory 1, and in synchronization with this, fetches data from the outside into the buffer memory 206 according to the type of the access request or The data is output from the buffer memory 206 to the outside. The memory 1 is operated in synchronization with the oscillation output of its own built-in self-oscillation circuit 102. On the other hand, the CPU 2 operates in synchronization with the operation clock 209 of the system.

When the CPU 2 accesses the memory 1, the start of access is transmitted to the memory 1 by an access start signal 200. Access start signal 20
0 is regarded as a signal equivalent to the chip selection signal for the memory. Although not particularly limited, according to this embodiment, the access control circuit 207 has a function as a chip selection controller. This function can be replaced by a decoder that decodes the upper few bits of the address signal output from the CPU 2 to the outside and forms a chip select signal. In either case, the address refers to the address assigned to the peripheral circuit to be accessed and the address generated by the CPU 2. In this sense, an access request to a peripheral circuit such as a memory, especially an instruction to start access, is made. Is directly or indirectly performed by a circuit portion that generates an access address, and the access control circuit is understood as including such a circuit portion.

The data transfer direction is read / write signal 2
Indicated by 01. A read is a data transfer from a peripheral circuit such as the memory 1 to the CPU 2, and a write is a data transfer from the CPU 2 to a peripheral circuit such as the memory 1. According to the present embodiment, the position designation (pointer) of the data in the peripheral circuit requested to be accessed is designated by the address signal supplied to the address bus 210. The number of data transfer words is specified by a single mode / burst mode instruction signal (single / burst signal) 202. The single / burst signal 202 is not required for those which do not have the burst mode which is a continuous data transfer mode.

When detecting an access request by the access start signal 200, the access cycle control section 101 generates an access cycle signal for internal operation based on the oscillation output of the self-excited oscillation circuit 102 in response to the detection. In the memory 1, a read or write operation specified by the read / write control signal 201 is performed in synchronization with the access cycle signal. Further, to the outside of the memory 1, the access cycle signal is output to the CPU 2 as an access clock signal 103. The access clock signal 103 is a clock signal unique to the memory 1 and is given to the CPU 2 as a response request to the access request from the CPU 2.

FIG. 2 shows the relationship between the data output timing of the memory 1 in the read operation and the data output timing of the CPU 2 in the write operation and the access clock signal 103. According to FIG. 2, the memory 1 to which the read operation has been instructed receives a setup time (Trs) / hold time (T) with respect to a rising edge of an access clock signal 103 (an access cycle signal in the memory).
The desired data is output to the data bus 211 at a timing that guarantees rh). The CPU 2 loads the data into the buffer memory 206 at the rising timing of the access clock signal 103. In writing, the CPU 2 outputs the data from the buffer memory 206 to the data bus 211 so as to guarantee the setup time (Tws) / hold time (Twh) with respect to the fall of the access clock signal 103. The memory 1 captures the data at the falling timing of the access cycle signal. In the write operation, the rise of the access clock signal 103 can be used as a reference.

According to the embodiment of FIG. 1, the access cycle control section 101 outputs a cycle complete signal 104 for notifying the CPU 2 of the completion of the continuous data transfer in the burst mode. The access control unit 101 counts the number of words to be transferred by a burst counter 105 using an access cycle signal equivalent to the access clock signal 103, and outputs a count-up state as a cycle complete signal 104. Instead of the cycle complete signal 104, the same function may be realized on the CPU 2 side. That is, a burst counter for counting the access clock signal 103 may be provided on the CPU 2 side.

FIG. 3 is a block diagram of a system that enables data transfer via a wait state control unit as a comparative example of the above embodiment, and FIG. 4 shows the data transfer timing.

In FIG. 3, when the CPU 400 transfers data to the external memory 401, the start of data transfer is notified to the memory 401 and the wait state control unit 402 by the access start signal 403. The memory 401 that has received the access start signal 403 reads /
The write control circuit 404 starts a read or write operation according to the read / write signal 405. In synchronization with this, the wait state control unit 402 also interprets the access start signal 403 and the read / write signal 405 and generates a wait signal 407 for indicating the access completion based on the same operation clock 406 as the CPU 400. Therefore, the counting of the weight counter 408 is started. In a read operation, the memory 401 can output data to be read to the data bus 409 after a lapse of time guaranteed by the manufacturer / distributor. Further, in the write operation, the memory 401 stores the CPU 40 after the time guaranteed by the manufacturer / distributor elapses.
The data on the data bus 409 output by 0 can be taken in. The completion of the read operation or the write operation due to the lapse of the time guaranteed by the manufacturer / distributor is normally performed by the wait state control unit 402 causing the CPU 400 to change the wait signal 407 to false (False). (If the wait signal is an asynchronous signal, the CPU checks the wait signal in synchronization with the operation clock). For example, in FIG. 4, when the wait signal is set to false (low level) at time t1 in the read operation, the CPU reads data on the data bus. When the wait signal is false at time t2 in the write operation, the CPU confirms that the data to be written has been taken into the memory and stops outputting the write data.

As is apparent from the timing shown in FIG. 4, the position (timing) at which the wait signal is made false usually differs between the read cycle and the write cycle. Also, in the burst mode, the wait signal should be generated cyclically continuously for the number of transfer words, but the interval between the first word and the interval after the second word is different. Therefore, the change of the wait signal 407 is
When 00 is confirmed, the CPU 400 completes a series of read or write cycles and makes the access control circuit 410 wait until the next cycle starts. Further, when switching between a read cycle and a write cycle in the same operation mode, a switching time as indicated by Tdis in FIG. 4 is required. This is because the wait signal is confirmed in synchronization with the clock. As described above, in the case of data transfer using a wait signal, complicated control and extra time must be spent.

According to the above embodiment, the following operation and effect can be obtained. (1) In the present embodiment shown in FIGS. 1 and 2, in the read cycle and the write cycle, the occurrence start position of an access cycle generated by a peripheral circuit such as a memory and the update timing of the change are usually different. CPU
No. 2 need only concentrate on data input / output in accordance with the change of the access clock signal 103 without considering these complicated timings. That is, data transfer with complicated timing can be realized without the conventionally required wait state control unit. This applies, of course, to both single and burst transfers.

(2) Eliminate the wait state control unit,
Since data transfer is performed using the access clock signal 103 output from a peripheral circuit such as a memory, the access cycle time can be substantially reduced and the bus use efficiency can be substantially improved.
That is, a peripheral circuit such as a memory is operated in synchronization with the oscillation output of its own built-in self-excited oscillation circuit 102, and is operated asynchronously with an operation clock signal 209 of a CPU that issues an access request to the peripheral circuit. The mutual data interface is realized by mutually equal access requests and response requests thereto. Therefore, the conventional CPU
A series of data transfer times limited to an integral multiple of the basic operating clock of a data processor, such as a memory, requires a response request that depends on the natural self-oscillation frequency generated according to the operating speed and other characteristics of peripheral circuits such as memory. Can be determined according to the clock cycle. As a result, it is possible to easily realize data transfer within the time limit of the characteristics of the peripheral circuit and the CPU. In other words, it is possible to reduce the wasted time generated for synchronizing with the operation clock of the CPU, which has been conventionally regarded as a problem.

(3) Since the CPU 2 has on-chip the buffer memory 206 for interfacing with the peripheral circuit, the difference in data transfer speed between the CPU internal unit 204 and the outside is absorbed internally, and read by an access request is performed. It is possible to prevent the sequential waiting time from intervening in the processing of data and write data.

(4) The data transfer format according to the above-described embodiment can be extended and considered that a memory is also given a bus right when considered locally. That is, at the start of the data transfer, the system operates at the operation clock 209 of the CPU 2, but during the data transfer, it is considered that the system operates at the operation clock 103 of the memory. Appears to have moved. This concept is considered to be particularly effective when the integration degree of the LSI is improved in the future and the logic function is merged into the memory.

FIG. 5 is a block diagram showing an embodiment of the memory. Although not particularly limited, the memory 1 shown in FIG. 1 is formed as a static random access memory (SRAM) on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The memory 1 shown in FIG. 1 has row address signal input terminals AR0 to ARm, column address signal input terminals AC0 to ACn, and data input / output terminals I / O0 to I / O0.
An I / Op, a chip selection signal input terminal CS, an output enable signal input terminal OE, a write enable signal input terminal WE, an access cycle signal output terminal AC, a burst / single switching signal input terminal B / S, and a power supply terminal (not shown) Is provided. 1, an access start signal 200 is supplied to a chip selection signal input terminal CS, a read signal constituting a read / write signal 201 is supplied to an output enable signal input terminal OE, and a write A write signal constituting the read / write signal 201 is supplied to the enable signal input terminal WE, and the access cycle signal 103 is output from the access cycle signal output terminal AC.

In the memory cell array 100, static memory cells are arranged in a matrix, and a word line connected to a selection terminal of the memory cell is connected to an output of the row address decoder 110. Row address decoder 1
10 receives an output of a row address buffer 111 which converts a row address signal supplied from the outside into an internal complementary address signal and outputs it, and decodes the output to select one word line corresponding to the row address signal. Drive to the level. Bit lines coupled to data input / output terminals of the memory cells are commonly connected to a common data line 113 via a column switch circuit 112. The selection of the bit line to be conducted to the common data line 113 is performed by the column switch circuit 112 receiving the output of the column address decoder 114. The column address decoder 114 converts a column address signal supplied from the outside into an internal complementary address signal and outputs the converted signal.
5 is received and decoded to perform a bit line selection operation by the column switch circuit 112. Reference numeral 116 denotes a sense amplifier and an output buffer circuit for amplifying data read from the memory cell to the common data line 113 and outputting the amplified data to the outside. The input is to the common data line 113, and the output is to the data input / output terminal I / O0. ~ I /
It is bound to Op. 117 is a data input / output terminal I / O0
ＩI / Op is an input buffer for inputting write data given thereto, and its output is coupled to the common data line 113. Reference numeral 118 denotes a data control circuit for equalizing or precharging a data latch circuit or a common data line.

The access control unit 101 includes a cycle timing generation circuit 1010 and an internal timing generation circuit 10
11 is provided. The internal timing generation circuit 1011 is coupled to the input terminals CS, OE, WE, and B / S, and determines an internal operation mode by detecting an access start, determining a read / write operation, determining a burst mode / single mode, and the like. And a cycle timing generation circuit 1010
, An internal operation timing signal corresponding to the operation mode is generated in synchronization with the access cycle signal supplied from. The cycle timing generation circuit 1010 synchronizes with a signal supplied from the internal timing generation circuit 1011 based on an access start instruction supplied from the CS terminal, and generates a cycle timing signal 1013 and an access clock based on the oscillation output of the self-excited oscillation circuit 102. Signal 1
03 is generated. The delay circuit 1014 is used for adjusting the phase of the self-excited oscillation output, and the delay circuit 1015 is used for adjusting the phase of the access clock signal 103 and the cycle timing signal 1013 output to the outside.

FIG. 6 shows a detailed example circuit of the cycle timing generation circuit 1010. Self-excited oscillation circuit 1
02 is not particularly limited, but is a two-input AND gate 1
020 and a feedback loop composed of an inverter amplifier 1021 for feeding back the output of the AND gate 1020 to one of its inputs. A trigger circuit for controlling the oscillation and stop of the feedback loop is connected to the other input of the AND gate 1020. You. The trigger circuit includes an AND gate 1024 to which the output of the selector 1022 whose output is set to the high level in the initial state is input and the output of the OR gate 1023 is input as feedback. The OR gate 1023 receives the output of the AND gate 1024 and a trigger signal 1025 such as a one-shot pulse supplied from the internal timing generation circuit 1011 in synchronization with the start of the read or write operation, and ANDs the output. Gate 1020
To supply. The reference numerals 1026 to 1028 denote waveform shaping elements (or delay elements). This self-excited oscillation circuit 102 outputs a low level in an initial state. When the trigger signal 1025 is changed by a one-shot pulse in this state, oscillation occurs in a feedback loop constituted by the AND gate 1020 and the inverter amplifier 1021. This oscillation state is continued until the output of the selector 1022 is changed to a low level and the output of the OR gate 1023 is changed to a low level.

In the configuration shown in FIG. 6, the burst counter 105 and the select 10
22 are used. The selector 1022 is supplied with the B / S signal or an internal signal equivalent thereto, and selects the output of the waveform shaping element 1027 in the single mode. Therefore, in the single mode, the self-excited oscillation circuit 102 changes the access clock signal 103 and the cycle timing signal 1013 by one cycle to stop the oscillation operation. In the burst mode, the output of the burst counter 105 is selected. The burst counter 105 counts the number of words of continuous data read from the memory cell array by the waveform shaping element 1.
It counts based on the output pulse change of 027, and outputs a one-shot pulse that changes from high level to low level when the count result reaches a predetermined count value (target burst transfer word number). Therefore, when an access cycle corresponding to the number of consecutive read words in the burst mode is generated, the oscillation operation of self-excited oscillation circuit 102 is stopped.

FIG. 7 is an operation timing chart showing an example of the memory shown in FIG. As shown in the figure, the access cycle signal output terminal AC is changed in synchronization with the timing at which read data is output in the read cycle, and the access cycle signal output terminal AC is changed in synchronization with the timing in the write cycle. CPU
Supplies write data.

FIG. 8 is a block diagram showing a detailed embodiment of the CPU 2. Although not particularly limited, the CPU 2 shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The same circuit blocks as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, the buffer memory 20
6 will be described in detail.

The buffer memory 206 is a read buffer 2 of a FIFO (first-in first-out) type.
061, a write buffer 2062, and a buffer control circuit 2063. The read buffer 2061 is a CPU
, And the write buffer 2062 is dedicated to data transfer in the write direction by the CPU. Both buffers 2061 and 2062 are asynchronous ports 2064 controlled based on a response request from the memory 1 given by the access clock signal 103.
And a synchronization port 2065 controlled in synchronization with the internal operation clock 209. Buffer control circuit 206
Reference numeral 3 includes an asynchronous control unit 2063A for controlling the asynchronous port 2064 and a synchronous control unit 2063B for controlling the synchronous port 2065. Asynchronous port 2064
Is connected to the input / output buffer circuit 205, and the synchronization port 2065 can be interfaced with a group of registers and a cache memory included in the arithmetic circuit 204.

The asynchronous control unit 2063A synchronizes with the change of the access clock signal 103 to
062, an asynchronous read signal (ASyn
c Read Signal) and the asynchronous read address (A
Sync Read Pointer), and the read buffer 20 is synchronized with the change of the access clock signal 103.
Asynchronous write signal (ASync
Write Signal) and the asynchronous write address (AS
(ync Write Pointer). Whether the read buffer 2061 or the write buffer 2062 should be accessed in synchronization with the change of the access clock signal 103 depends on whether the access request of the CPU 2 corresponding to the access clock signal 103 is a read or a write. The determination is made by receiving the indicated information from the central control unit 208.

The synchronization control unit 2063B is provided by the central control unit 20.
8 is operated as part of the instruction execution control. For example, when a memory read operation is required along with execution of a data transfer instruction such as a load instruction, a store instruction, or a move instruction, a synchronous read instructing a read operation to the read buffer 2061 in synchronization with the operation clock 209 is performed. A signal (Sync Read Signal) and a synchronous read address (Sync Read Pointer) at that time are supplied. When a memory write operation is required in response to execution of a data transfer instruction or the like, the operation is synchronized with the operation clock 209. Write buffer 2
062, a synchronous write signal (Sync W)
rite Signal) and the synchronous write address (Sync
Write Pointer). Read buffer 2061
Is to be accessed or the write buffer 2062 is to be accessed is determined by receiving an instruction decoding signal output from the central control unit 208 in accordance with the instruction execution.

In the example of FIG. 8, the memory 1 does not have the function of outputting the cycle complete signal 104. An equivalent function is performed by a burst counter 2066 incorporated in the asynchronous control unit 2063A, and gives the end of a burst transfer cycle to the access control circuit 207. C of the present embodiment
In PU2, the count-up signal of the burst counter 2066 is also used to notify the central control unit 208 of the completion of writing to the read buffer 2061 and the completion of reading from the write buffer 2062. This will be described with reference to FIG.

FIG. 9 is a block diagram showing a detailed example of a circuit portion relating to the read buffer 2061 in the buffer control circuit 2063. The up counter 2063R1 generates the synchronous read address of the read buffer 2061, and the up counter 2063R2 generates the asynchronous write address of the read buffer 2061. The up-count operation of the up-counter 2063R2 is performed when the access clock signal 103 is changed to a high level and the central control unit 2
This is performed in synchronization with the timing at which the read buffer write signal from 08 is activated. Up counter 2063
The R1 up-count operation is performed in synchronization with the operation clock 209 when the read buffer read signal from the central control unit 208 is activated. Both up counters 20
63R1 and 2063R2 are cleared to 0 by the high level output of the AND gate 2063R3. When the output value of the up-counter 2063R1 is not 0, the two up-counters 2063R1, 263 are cleared.
The coincidence detection circuit 20 determines that the outputs of the 063R2 have coincided.
63R6. Up counter 20
The fact that the output value of 63R1 is 0 means that the 0 detection circuit 206
3R4 detects. When the output value of the up counter 2063R1 is 0, the 0 detection result by the 0 detection circuit 2063R4 means that the read buffer 2061 is empty, and this is given to the central control unit 208. The central control unit 208
When this state is detected, it can be confirmed that all the read data from the memory 1 has passed to the arithmetic circuit 204. The burst counter 2066 shown in FIG. 8 detects whether the number of continuous data transfer words has reached the number of words to be transferred. When the arrival has been detected by the burst counter 2066, the output of the burst counter 2066 is changed to a high level for a predetermined period. In the read operation for the memory 1, the change of the burst counter 2066 to the high level is supplied to the AND gate 2063R5 as a signal indicating the completion of the read. AND gate 2063
When R5 receives the signal indicating the completion of the read when the output of the up counter 2063R1 does not output 0 by the 0 detection circuit 203R6, the R5 detects the completion of the read to the read buffer 2061 and passes it to the central control unit 208. . When the central control unit 208 detects that the read to the read buffer 2061 is completed, it can confirm that all the read data from the memory 1 has been stored in the read buffer 2061, whereby the central control unit 208 stores the read data in the read buffer 2061. The internal arithmetic processing can be started immediately by reading out the data from the address 2061.

FIG. 10 is a detailed block diagram showing an example of a circuit portion related to the write buffer 2062 in the buffer control circuit 2063. The up counter 2063W2 generates the synchronous write address of the write buffer 2062, and the up counter 2063W1 generates the asynchronous read address of the write buffer 2062. The up-counting operation of the up-counter 2063W1 is performed in synchronization with the timing when the access clock signal 103 is changed to the high level and the write buffer read signal from the central control unit 208 is activated. Up counter 206
The 3W2 up-count operation is performed in synchronization with the operation clock 209 when the write buffer write signal from the central control unit 208 is activated. Up counter 2 of both
063W1 and 2063W2 are AND gates 2063W3
Is cleared to 0 by the high level output of. When the output value of the up-counter 2063W1 is not 0, the up-counter 2063W1 is cleared.
The match detection circuit 2 indicates that the output of the 2063W2 is matched.
063W6. Up counter 2
The fact that the output value of 063W1 is 0 means that the 0 detection circuit 20
63W4 detects. If the output value of the up counter 2063W1 is 0, the 0
The detection result indicates that the write buffer 2062 is empty, whereby the central control unit 208 recognizes the empty state of the write buffer 2062. In the write operation for the memory 1, the change of the burst counter 2066 to the high level is supplied to the AND gate 2063W5 as a signal indicating the completion of the write operation. AND gate 2063
When W5 receives the signal indicating the completion of the writing when the output of the up counter 2063W1 is not 0 by the 0 detection circuit 2063W4, the W5 detects the completion of the writing operation to the write buffer 2062 and sends it to the central control unit 208.
Pass to. The central control unit 208 includes a write buffer 2062
When the completion of writing to the memory 1 is detected, it can be confirmed that all the write data to the memory 1 in response to the response request from the memory to the memory write access has been output from the write buffer 2062.

FIG. 11 shows a buffer memory different from the buffer memory 206 shown in FIG. The buffer memory 206 shown in the figure has a read / write buffer 2067 shared by a read buffer 2061 and a write buffer 2062, and a buffer control circuit 2063 operates the read / write buffer 2067 as a read buffer or writes data. A read / write buffer enable flag 2068 for setting information on whether to operate as a buffer is provided, and the operation is controlled according to an instruction from the central control unit 208. Figure 8 for other points
The same reference numerals are given to the same circuit blocks, and detailed description thereof will be omitted. This contributes to a reduction in chip area.

FIG. 12 shows a main part of an embodiment having a control parameter register for the memory of FIG. That is, there is a parameter register 1051 that holds the number of target transfer words (the number of transfer words to be counted up) of the number of continuous data transfer words to be counted by the burst counter 105 in FIG. This parameter register 1
Reference numeral 051 transfers a desired parameter (information for specifying the number of burst transfer words) in a programmable manner under the control of the central control unit 208 of the CPU 2. Other configurations are the same as those of FIGS. 5 and 6, and the same circuit blocks are denoted by the same reference numerals and detailed description thereof will be omitted. This increases the degree of freedom of data transfer or the flexibility of control thereof.
When the burst counter 105 has a storage stage corresponding to the number of counted bits, the parameter register 1051 can be configured as a parameter register so that the storage stage can be preset.

FIG. 13 shows an embodiment in which mutually identical memories having a multi-bit input / output function of, for example, 1/2 n bits with respect to the number of bits of the data bus are interfaced with the CPU 2. In this embodiment, the CPU
2 is a buffer memory 206 and an input / output buffer circuit 2
05 are provided. For example, if the data bus 211 is 3
When the number of parallel input / output bits of the memory 1 is 2 bits and the number of parallel input / output bits is 16 bits, the 16-bit upper data bus 211U is connected to one memory 1U via the input / output buffer circuit 205U.
The 16-bit lower data bus 211U is coupled to the other memory 1L via the input / output buffer circuit 205L. An access start signal 200, a read / write signal 201, a single / burst signal 202, and an address bus 210 are commonly connected to the memories 1U and 1L. The access clock signal 103U is supplied to the buffer memory 206U.
The access clock signal 103L is supplied to the buffer memory 206
L are individually connected to each other. Cycle complete signals 104U, 10 output from respective memories 1U, 1L
4L is supplied to the cycle complete control circuit 2069, and the end of both memory accesses is determined by the access control circuit 2069.
7

The actual number of parallel input / output bits of the memory is ×
4, × 8, × 9, × 16, × 18 bits are mainstream,
The number of parallel data input / output bits of the CPU is × 16, × 3
As shown in FIG. 13, it is necessary to provide a buffer memory for each of a plurality of bits in order to interface the memory with the CPU correspondingly to 2, 36, 64, and 72 bits. And become important.

FIG. 14 shows an embodiment in which a system is constructed by mixing memories having different characteristics / functions. In this case, if the fine terminal functions and connection conditions are ignored, data transfer can be basically performed in accordance with the access clock. Therefore, the access clock signal 103-1 of the memory 1-1 and the data of the memory 1-2 are not transmitted. The access clock signal 103-2 is output from the OR gate 3 outside the CPU 2.
00 to the buffer control circuit 2063.
Similarly, the access complete signal 10 of the memory 1-1 is
4-1 and access completer signal 10 of memory 1-2
4-2 is also connected to the access control circuit 207 via the OR gate 301 outside the CPU 2. Other access start signal 200, read / write signal 201, single / burst signal 202, address bus 210, data bus 211 and the like are commonly connected to memories 1-1 and 1-2. As a result, a system can be configured by mixing peripheral circuits such as memories having different characteristics / functions.

FIG. 15 shows the CPU 2 described in the above embodiment.
One embodiment of a data processing system using a memory and a memory 1 is shown. In FIG. 15, as a peripheral circuit whose data can be transferred by the same protocol as the memory (RAM) 1 of the above embodiment, a file interfaced with the memory (ROM) 3, the hard disk device 41 and the floppy (registered trademark) disk device 42 A control device 4, a display control device 5 for performing drawing control on a frame buffer 51 and a display control for displaying drawn image data on a monitor 52, a parallel / serial port 6 interfaced with a printer 61 and a keyboard 62, and a communication device 10 Is provided. These peripheral circuits have their own self-excited oscillation circuits 102 according to their own operation characteristics, and realize data transfer by returning a response request to an access request from the CPU 2 similarly to the above memory.
In FIG. 15, reference numeral 9 denotes a system monitoring device, which monitors a system abnormality using a watchdog timer or monitors a power supply voltage state. The high-speed data transfer device 8 is a circuit such as a direct memory access controller. Bus right arbitration with the CPU 2 is performed by the bus right monitoring device 7. The high-speed data transfer device also performs the same data transfer control as the CPU 2. Reference numeral 21 denotes an external cache memory unique to the CPU 2, which is a secondary cache memory for the internal cache memory 22 of the CPU 2. The data processing system of FIG. 15 is configured on a mounting board on which an address and data bus 11 and a control bus 12 are formed.

In the data processing system of FIG. 15, since wait state control for the memory and the input / output circuit is not required, the memory controller and the input / output controller for this are not provided on the mounting board.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. No.

For example, in the above embodiment, R is used as a peripheral circuit.
The case where the present invention is applied to a memory such as an AM has been described. However, the peripheral circuits are not limited thereto, and can be applied to various peripheral circuits other than the peripheral circuit shown in FIG. Also, the one applied to such a peripheral circuit is CP
The present invention is not limited to the U and the direct memory access controller, and can be applied to various data processors such as a microprocessor, a microcomputer, a single-chip microcomputer, and a digital signal processor.

The buffer memory is not limited to the complete dual port buffer as in the above embodiment, but a uniport buffer memory can be used as a dual port in a time sharing manner. Also, the depth (storage capacity) of the buffer memory is important from the viewpoint of the chip area of the data processor. However, if the function is reduced too much, it will not contribute to the improvement of the bus speed. It is a design matter determined in consideration of off. It is considered that limiting the depth of the buffer memory to the number of words handled in one data transfer (such as the maximum number of words in burst transfer) is useful for simplifying the buffer control circuit.

[0064]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the peripheral circuit operates in synchronization with the oscillation output of its own built-in self-excited oscillation circuit, and operates asynchronously with the operation clock signal of the data processor which issues an access request to the peripheral circuit. In relation
The data interface between them is realized by mutually equal access requests and response requests thereto. Therefore, a series of data transfer times limited to an integral multiple of the basic operation clock of the data processor is reduced to a response request depending on the characteristic self-excited oscillation frequency generated according to characteristics such as the operating speed of peripheral circuits such as a memory. Can be determined according to the clock cycle. As described above, it is possible to easily realize the data transfer within the time limit of the characteristics of the peripheral circuit and the data processor. In other words, it is possible to reduce the wasted time that has been generated for synchronization with the operation clock of the data processor, which has been a problem in the related art. As described above, a wait state control circuit for interfacing the data processor with each peripheral circuit is not required, and the circuit connecting means can be simplified.

A data processor having on-chip a buffer memory interfaced with a peripheral circuit can absorb a difference in data transfer speed between an internal unit of the data processor and the outside, and can read or write data by an access request. Waiting time for the processing can be reduced.

The data processor can be interfaced with a plurality of different types of peripheral circuits, or the same peripheral circuit having a multi-bit input / output function of, for example, ｎn bits can be interfaced with the data processor. Thus, the data processing system can be freely configured.

[Brief description of the drawings]

FIG. 1 is a system block diagram showing a CPU as an embodiment of a data processor according to the present invention and a memory as an embodiment of a peripheral circuit according to the present invention.

FIG. 2 is a timing chart illustrating an example of a data transfer operation in the system of FIG. 1;

FIG. 3 is a block diagram of a system that enables data transfer via a wait state control unit as a comparative example with the above-described embodiment of FIG. 1;

FIG. 4 is a data transfer operation timing chart of FIG. 3;

FIG. 5 is a block diagram of an embodiment of the memory of FIG. 1;

FIG. 6 is a detailed example circuit diagram of the cycle timing generation circuit of FIG. 5;

FIG. 7 is an example operation timing chart of the memory of FIG. 6;

FIG. 8 is a detailed block diagram of an embodiment of the CPU of FIG. 1;

9 is a detailed example block diagram of a circuit portion related to a read buffer in the buffer control circuit of FIG. 8;

FIG. 10 is a detailed example block diagram of a circuit portion related to a write buffer in the buffer control circuit of FIG. 8;

FIG. 11 is a block diagram of an embodiment of a CPU having a buffer memory of a type sharing a read buffer and a write buffer.

FIG. 12 is a block diagram of an embodiment of a memory in which a parameter register is provided in a burst counter.

FIG. 13 shows, for example, 1/2 of the number of bits of the data bus.
FIG. 3 is a block diagram of an embodiment in which mutually identical memories having an n-bit multi-bit input / output function are interfaced with a CPU.

FIG. 14 is a block diagram of an embodiment in a case where a system is configured by mixing memories having different characteristics / functions.

FIG. 15 is a block diagram of an overall embodiment of a data processing system.

[Explanation of symbols]

 Reference Signs List 1 memory 1U, 1L memory 100 memory cell array 1-1, 1-2 memory 101 access cycle control unit 1010 cycle timing generation circuit 1011 internal timing generation circuit 1013 cycle timing signal 102 self-excited oscillation circuit 103 access clock signal 103U, 103L access clock Signals 103-1 and 103-2 Access clock signal 105 Burst counter 1051 Parameter register 2 CPU 200 Access start signal 204 Arithmetic circuit 205 Input / output buffer circuit 205U, 205L Input / output buffer circuit 206 Buffer memory 206U, 206L Buffer memory 2061 Read buffer 2062 Write buffer 2063 Buffer control circuit 2063A Asynchronous control unit 2063B Synchronous control unit 2 064 Asynchronous port 2065 Synchronous port 2066 Burst counter 207 Access control circuit 208 Central control unit 209 Operation clock signal 210 Address bus 211 Data bus 211U, 211L Data bus 300, 301 OR gate 3 Memory 4 File control device 5 Display control device 6 Parallel serial port 10 Communication equipment

Claims (20)

[Claims] 1. A memory device formed on a semiconductor substrate, comprising: a plurality of address input terminals to which a plurality of address signals are supplied; a data input / output terminal for inputting or outputting a data signal; A memory cell array having a plurality of memory cells arranged in an array and holding data; an address decoder for selecting the memory cells of the memory cell array by decoding the plurality of address signals; A first terminal coupled to the first terminal in response to the control signal.
An internal timing generation circuit for outputting a signal; a self-excited oscillation circuit for generating a clock signal in response to the first signal; and a clock signal when the data signal is input or output to the data input / output terminal. And an external terminal for outputting an internal signal, wherein the memory device performs an internal operation in synchronization with the clock signal. 2. The memory device detects a number of continuous data input or output to the data input / output terminal by counting a change in the clock signal in a burst mode, and determines the predetermined number of continuous data. A counter that stops the oscillation operation of the self-excited oscillation circuit when the count value reaches the count value. In the burst mode, a plurality of continuous data are synchronized with the clock signal in response to one access request. The memory device according to claim 1, wherein the access request includes the control signal and the plurality of address signals. 3. A plurality of memory cells; a plurality of first terminals to which a plurality of address signals for selecting the plurality of memory cells are input; and data read from a memory cell corresponding to the plurality of address signals. , A third terminal for outputting a timing signal synchronized with the read data, and a circuit for forming the timing signal. 4. The semiconductor device according to claim 3, wherein said read data is output at a timing having a predetermined setup time and a predetermined hold time with respect to a changing edge of said timing signal. . 5. In a predetermined read mode, when a plurality of continuous read data are output from the second terminal, and when the continuous read data is output, the level of the timing signal corresponds to the continuous read data. 4. The semiconductor device according to claim 3, wherein the semiconductor device changes. 6. The semiconductor device according to claim 5, wherein said predetermined read mode is a burst mode. 7. The semiconductor device according to claim 5, wherein when the continuous read data is output, the timing signal changes at a predetermined cycle. 8. The semiconductor device according to claim 3, wherein the semiconductor device is configured as a random access memory. 9. The semiconductor device according to claim 8, further comprising a fourth terminal to which a control signal for instructing a write operation or a read operation for said memory cell is inputted. 10. The semiconductor device according to claim 9, wherein said control signal is a write enable signal. 11. When the control signal indicates a write operation to the memory, the write data is transmitted to the second memory.
10. An input to a terminal.
13. The semiconductor device according to claim 1. 12. The semiconductor device according to claim 3, wherein the circuit for forming the timing signal includes an oscillation circuit. 13. A memory cell array including a plurality of memory cells, a plurality of first terminals to which a plurality of address signals are input, a second terminal to input or output data, and a third terminal to output a first signal. A fourth terminal to which a second signal instructing a write operation or a read operation to the memory cell array is inputted; an address decoder receiving the plurality of address signals and selecting a memory cell corresponding to the plurality of address signals; A circuit for forming the first signal, wherein when the second signal indicates a read operation, the data read from the memory cell is output to the second terminal and the first signal is output. Is output to the third terminal. 14. The data output from the second terminal is output at a timing having a predetermined setup time and a predetermined hold time with respect to a changing edge of the first signal. 14. The semiconductor memory according to claim 13, wherein: 15. In a predetermined read mode, continuous data is output from the second terminal, and when the continuous data is output, the level of the first signal changes in accordance with the continuous data. 14. The semiconductor memory according to claim 13, wherein: 16. The semiconductor memory according to claim 15, wherein said predetermined read mode is a burst mode. 17. The semiconductor memory according to claim 15, wherein when the continuous data is output, the first signal changes at a predetermined cycle. 18. The semiconductor memory according to claim 13, wherein said second signal is a write enable signal. 19. The circuit according to claim 1, wherein the circuit forming the first signal includes an oscillation circuit.
3. The semiconductor memory according to 3. 20. The semiconductor memory according to claim 13, wherein the first signal is a timing signal that changes in synchronization with the data output from the second terminal.