JP2000348086A - System and method for logic synthesis aid and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily design a circuit of high quality without any error in logic synthesis by generating a logic synthesis script by using the analysis result of the hierarchical structure in a function description. SOLUTION: A function description storage part 11 stores the function description of an object circuit to be designed by a description language VHDL and a structure analysis part 12 extracts the structure of a module, the correspondence between a file name and a module name, and the clock information of each module out of a basic structure information storage part 13. The basic structure information storage part 13 stores information as a key that the structure analysis part 12 takes. A script control part 14 makes settings regarding the kinds of commands included in the generated script and whether the individual commands have an operation. A script generation part 15 generates the script flies of a logic synthesis tool by the modules stored in the function description storage part 11 according to the analysis result of the structure analysis part 12 and the indication of the script control part 14 and stores them in a script storage part 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logic synthesis support system for supporting generation of a logic synthesis script used in a CAD system for supporting hardware design using a computer, a method thereof, and a program storage medium.

[0002]

2. Description of the Related Art In a function logic design process of an LSI, a function of a circuit to be designed is described in a language called a hardware description language (HDL), verified by a function simulation, and a HDL is used by a tool called a logic synthesis system. A general procedure is to automatically generate a logic circuit depending on a technology such as a gate array or a standard cell from a description.

As a logic synthesis tool, Synopsys, Inc.
Design Compiler is widely used. (Reference "Design Compiler Reference Manual: Fundamentals
(Japanese version) "1997 Synopsys, Japan) When a circuit is automatically generated by a logic synthesis system, the internal processing procedures and options of the logic synthesis are described in a script language of the logic synthesis system.
Must be input to the logic synthesis system.

Since the logic synthesis is basically performed for each module of the HDL description, when a circuit is large and the number of modules is several tens or several hundreds, it is troublesome to manually create each module individually. However, there is a problem that errors easily occur. In addition, as a result, an inappropriate circuit is generated, and there is a problem that a man-hour is required for correcting the circuit.

[0005] In addition, since logic synthesis is normally performed in order from the lower module of the circuit, commands on the operating system for controlling the execution order of the logic synthesis (for example, a makefile of a UNIX (registered trademark) operating system; UNIX Utility Library make "1990 Keigaku Publishing ISBN4-7665-1093-3)
It is also necessary to create In addition, various settings that need to be made in the logic synthesis script, such as the strength of optimization processing and the setting of delay to external pins of the module,
There is a know-how based on experience and achievements, and it is difficult for a beginner to make appropriate settings.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above circumstances. Accordingly, the present invention automates a task of creating a logic synthesis script of each module and an execution control command of the logic synthesis script. Accordingly, an object of the present invention is to provide a logic synthesis support system and method capable of providing an environment in which logic synthesis can be easily performed without error and a high quality circuit can be designed, and a program storage medium.

Another object of the present invention is to provide a logic synthesis support system and method for easily performing logic synthesis using know-how possessed by a logic synthesis expert, and a program storage medium.

A further object of the present invention is to provide a logic synthesis support system and method capable of easily performing logic synthesis of a reused part even in a design in which an HDL description is reused, and a program storage medium. .

[0009]

To achieve the above object, a logic synthesis support system according to claim 1 of the present invention comprises a function description storing means for storing a function description of a design, and a hierarchical structure in the function description. And a script generation means for generating a logic synthesis script which is an input of a CAD tool for logic-synthesizing the function description using the analysis result obtained by the structure analysis means. Features. According to this system, it is possible to automatically and easily create a logic synthesis script for each module in the function description.

According to a second aspect of the present invention, there is provided a logic synthesis supporting method, comprising the steps of: storing a function description of a design; analyzing a hierarchical structure of the function description; CAD for logic synthesis
Generating a logic synthesis script to be input to the tool. According to this method, a logic synthesis script for each module in the function description can be automatically and easily created.

According to a third aspect of the present invention, there is provided a computer-readable storage medium storing a function description storing a function description of a design, a structure analyzing means analyzing a hierarchical structure in the function description, and the structure analyzing means. Script generation means for generating a logic synthesis script which is an input of a CAD tool for logic-synthesizing the functional description using the analysis result obtained by the above-described method, and stored as a computer-readable program. According to the program stored in the storage medium, it is possible to automatically and easily create a logic synthesis script for each module in the function description.

A logic synthesis support system according to a fourth aspect of the present invention is characterized in that, in addition to the first aspect, the logic synthesis support system further comprises script control means for designating the contents of the logic synthesis script generated by the script generation means. According to this system, the contents of the generated script can be flexibly changed.

According to a fifth aspect of the present invention, there is provided a logic synthesis supporting method according to the second aspect, further comprising the step of designating the contents of the logic synthesis script generated by the step of generating the logic synthesis script. I do. According to this method, the contents of the generated script can be flexibly changed.

According to a sixth aspect of the present invention, in the computer-readable storage medium according to the third aspect, the program further includes script control means for designating the contents of a logic synthesis script generated by the script generation means. It is characterized by the following. According to the program stored in the storage medium, the contents of the generated script can be flexibly changed.

According to a seventh aspect of the present invention, there is provided a logic synthesis support system, comprising: a function description storage means for storing a function description of a design; a structure analysis means for analyzing a hierarchical structure in the function description; Execution control command generation means for generating a command for controlling the order of execution of logic synthesis between modules included in the function description using the analysis result of the function description. According to this system, it is possible to automatically and easily create an execution control command indicating that each module in the function description is logically synthesized.

The logic synthesis support method according to claim 8 of the present invention includes the steps of: storing a function description of a design; analyzing a hierarchical structure in the function description; Generating a command for controlling the order of execution of logic synthesis between modules included in the function description. According to this method, it is possible to automatically and easily create an execution control command indicating that each module in the function description is logically synthesized.

According to a ninth aspect of the present invention, there is provided a computer-readable storage medium, comprising: a function description storage unit for storing a function description of a design; a structure analysis unit for analyzing a hierarchical structure in the function description; Execution control command generation means for generating a command for controlling a logic synthesis execution order between modules included in the function description using the analysis result obtained by the means, and stored as a computer-readable program. is there. According to the program stored in the storage medium,
It is possible to automatically and easily create an execution control command indicating the order of logically synthesizing each module in the function description.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration diagram of a logic synthesis support system according to a first embodiment of the present invention.

In FIG. 1, the function description storage unit 11 stores
The function description of the circuit to be designed in the EEE standard hardware description language VHDL is stored. The structure analysis unit 12 extracts, from the function description storage unit 11 and the basic structure information storage unit 13, the hierarchical structure of the module, the correspondence between the file name of the VHDL description and the module name, and the clock information of each module. The basic structure information storage unit 13 stores the key information performed by the structure analysis unit 12, that is, the V including the top module.
The HDL file name, clock pin name, and information on its cycle are stored. The script control unit 14 sets the type of command included in the generated script and the presence / absence of an option of each command. The script generation unit 15 generates a module name.s for each module of the VHDL description stored in the function description storage unit 11 according to the analysis result of the structure analysis unit 12 and the instruction of the script control unit 14.
A script file of the logic synthesis tool Design Compiler is generated under the name cr and stored in the script storage unit 16. Hereinafter, a case where the function description storage unit 11 includes the VHDL description of FIGS. 3 to 6 will be described as an example.

The description of FIGS. 3 to 6 is based on a module (entity).
Ex.vhdl sub1.vhdl sub2.vhd
It is assumed that it is stored in l sub3.vhdl. FIG. 7 shows a block diagram of the VHDL of FIGS. The highest-order module is EX, and the input port ICLK is a clock having a period of 10 ns.

The basic structure information storage unit 13 stores these VHDL
The directory name where the description exists, the file name of the top module, and clock information are stored in a format as shown in FIG. The structure analysis unit 12 obtains the VH stored in the function description unit 11 from the information of FIG. 8 according to the flow of FIG.
By analyzing the DL description (FIGS. 3 to 6), a VHDL file name, a clock pin name, a submodule name and its instance name are generated for each module in the format of FIG.

First, a VHDL file (extension .vhdl) existing in the directory specified by dir on the first line in FIG.
Then, an entity declaration part is extracted from the list, and the correspondence between the file name and the module name is stored (step S61). Next, the file specified by top in the second line of FIG. 8 is read, and its module name and file name are output as in the first line of FIG. 10 (step S64). Further, FIG. 8, the third line cloc
The clock pin name ICLK specified by k is obtained, and FIG.
0 is output as in the second row (step S63). Further, the description in FIG. 3 is scanned to obtain the submodule instances C1 and C2 and their module names SUB1 and SUB2 (lines 33 and 39 in FIG. 3) and output them as shown in FIGS. .

Further, the reference position of the clock pin ICLK1 (lines 34 and 41 in FIG. 3) is obtained, and the lower module SU
It detects that the input ports ICLK1 and ICLK2 of B1 and SUB2 are clock pins and stores them (step S66). Then, the submodules SUB1 and SUB2
The same processing is performed recursively for (steps S68 to S68).
S615).

Here, in step S66 in FIG. 9, the clock pin name is output as shown in the sixth row in FIG. 10, since it is determined in advance when scanning the upper module as described above.

FIG. 1 shows the entire analysis result by the structural analysis unit 12.
0 is shown. The script generation unit 15 generates a logic synthesis script based on this information and the designation of the script control unit 14 shown in FIG.

In FIG. 11, the first line indicates that the top module is compiled with medium strength and the other layers are compiled with high strength. The second line indicates that the operating condition when optimizing for the maximum delay is WCCOM and the operating condition when optimizing for the minimum delay is BCCOM. The third and fourth lines indicate that a logic synthesis result report and a design rule check report are output when the top module is synthesized. In the fifth line, when synthesizing the top module, output the synthesis result of all modules to a file, and when synthesizing a module other than the top module, output only the synthesis result of the module to a file. (1, 0 in the figure is a flag indicating whether or not to output the synthesis result of all modules). The sixth line indicates that the synthesis result of all modules is output as a netlist when the top module is synthesized, and the netlist is not output when other modules are synthesized (1, 1 in the figure). 0 is a flag indicating whether or not to output a netlist). Lines 7 and 8 are verilog netlists.
Indicates that the file is output in the HDL format and that the extension of the netlist file is .net.

FIG. 12 shows a processing flow of the script generation unit 15. (A) is the whole flow, (b) is
This is a subroutine called in steps S91 and S95 of FIG. In the flow of (a), the data of the top module EX in FIG. 10 is referred to (step S92),
First, a logic synthesis script is generated for the top module EX and then for each of the submodules SUB1 and SUB2. Here, since SUB2 further has SUB3 as a submodule, after SUB2 script generation, S
A script for UB3 is generated (step S96).

As a result, the generated top module E
FIG. 13 shows the contents of the X. synthesis script file EX.scr. 13, lines 14, 15, 18, and 19 are outputs in step S98 of FIG. 12, lines 3 and 4 are outputs in step S99, and lines 5 to 11 are in step S98.
The output at 910, and the twelfth and thirteenth rows correspond to Step S91
1, the 14th to 19th lines are outputs in step S912, and the 20th to 25th lines are outputs in step S913.

The designation of the first and second lines in FIG.
The first and second lines in FIG. 11 are specified in lines 21 and 22 in FIG. 13, and the fifth to eighth lines in FIG.
Are reflected on lines 23 and 24, respectively. In addition, the third, seventh, ninth, and eleventh rows in FIG.
3. Instead of output based on the settings by the script control unit 14, the script is programmed in the script generation unit as general knowledge and know-how in the logic synthesis method, and is automatically output.

The default_top.scr in the third line
Is a script for reading the description of the top-level module, which is prepared in advance as a general-purpose script. Similarly, FIG. 14 shows the contents of the synthesis script file SUB1.scr of the lower module SUB1. Since SUB1 is not the top module, FIG.
Lines 3, 13, 17, and 19 are different from those in FIG. 13, but the others are the same. Here, by inputting dc_shell -f SUB1.scr from the UNIX command line, logic synthesis of the module SUB1 is executed, and the result is generated in a file called SUB1.db (dc_shell is the program name of Design Compiler.) . Further, by executing the scripts generated in this order from the lower module by the dc_shell command as described above, the entire circuit of FIG. 7 can be logically synthesized.

As described above, the structure analysis unit 12 automatically analyzes the hierarchical structure of the HDL description stored in the function description unit 11 so that the set_dont_touch command for the lower module as shown in lines 12 and 13 in FIG. , And the way commands are generated in the top-level module and other modules. In addition, as shown in the seventh and eighth lines in FIG. 13, a method common to all modules can be automatically generated by being incorporated in the system. The script control unit 14
Accordingly, it is possible to easily switch the presence / absence of a command and options as shown on the 21st and 23rd lines in FIG.

(Second Embodiment) FIG. 2 shows a configuration diagram of a logic synthesis support system according to a second embodiment of the present invention. This embodiment uses the logic synthesis script for each module generated in the first embodiment to generate a control command of an operating system that executes a logic synthesis tool, such as automatically performing logic synthesis in order from the lower module. Is what you do.

The function description storage unit 21 stores a function description of a circuit to be designed in the IEEE standard hardware description language VHDL. The structure analysis unit 22 includes a function description storage unit 21
Then, the module hierarchical structure and the correspondence between the file name of the VHDL description and the module name are extracted from the basic structure information storage unit 23. The basic structure information storage unit 23 includes the structure analysis unit 22
Is stored, that is, the VHDL file name including the top module. The logic synthesis execution procedure control command generation unit 24 generates the VHDL stored in the function description storage unit 21 according to the analysis result by the structure analysis unit 22.
UN that specifies the procedure for logically synthesizing each module of the description
The IX make file is generated, for example, with the name makefile_top-level module name, and the result is stored in the logic synthesis execution procedure control command storage unit 25.

Here, the logic synthesis script is VHDL
For example, it is assumed that each module is created with a name of module name.scr according to the first embodiment.
In the following, the VHDL of FIGS.
The case where the description is included will be described as an example.

In the basic structure information storage unit 23, 1 in FIG.
Specify the information on the second line. In the case of the present embodiment, the information on the third line in FIG. 8 is unnecessary. The structure analysis unit 22 performs the same flow as in FIG. 9 (however, steps S64, S66, S6
11, the processing related to the clock in S613 is not performed. )
As a result, information similar to that shown in FIG. 10 (information excluding the line having the keyword clock) is generated.

FIG. 15 shows a processing flow of the logic synthesis execution procedure control command generation unit 24. (A) is an overall flow, and (b) is a flow of output processing of a make command for one module called in steps S122 and S125. This processing flow refers to the information output from the structure analysis unit 22 in the same manner as in FIG. 12, and sequentially from the top, that is, the modules EX, SUB1, SUB2, and SUB3.
The command lines described in the makefile in this order are generated.

For example, in step S121,
The process (b) is called, and the target file name EX.db
The script file name (EX.scr) and the VHDL file name (EX.vhdl) of the module are output as dependent files, and the synthesis result file (module name.db) of the lower module is output, and EX.db is generated. Command to execute logic synthesis (dc_shell) is output as follows.

EX.db: EX.scr EX.vhdl SUB1.db SUB2.d
b dc_shell -f EX.scr Similarly, other modules SUB1, SUB2, SU
Makefil file resulting from the description of B3
FIG. 16 shows the contents of e_Ex. By using this makefile and inputting make -f makefile_EX EX.db on the UNIX command line, the logic synthesis of all modules below the module EX can be automatically performed.

As described above, the structure analysis unit 22 automatically analyzes the hierarchical structure of the HDL description recorded in the function description unit 21 so that the command file for controlling the execution of the logic synthesis tool as shown in FIG. Can be automatically generated.

The following is an example of a modification that can be made to the above embodiment.

(1) In the above embodiment, the case where the basic structure information storage units 13 and 23 are provided has been described, but this is not an essential component for the present invention. That is, in the above embodiment, the top-level module is specified in the basic structure information storage units 13 and 23, but a directory in which the structure analysis unit searches for the function description is determined in advance, and the structure analysis unit searches the directory. The top module may be automatically determined. Similarly, in the above embodiment, the clock name and its cycle are specified in the basic structure information storage unit 13, but these may be specified in the HDL description of the function description storage unit 11. Specifically, for example, V in FIG.
It is conceivable to use a comment in the declaration of the eighth line of the HDL description to describe as ICLK: IN std_logic;-clock10.

(2) In the above embodiment, the logic synthesis scripts of all the modules in the function description are generated. However, for example, only the script of a specific module is generated by designating the range for generating the script in the script control unit 14. Alternatively, a script below a certain module may be generated. This makes it possible to easily perform logic synthesis by changing conditions for each module, or to perform logic synthesis again by changing conditions for a certain module.

(3) The above two embodiments may be used in combination. 12 and 15 are different from each other in output contents, but are basically the same flow.
It is also conceivable that these are integrated to output a logic synthesis script and a logic synthesis execution control command at the same time.

(4) The present invention and Japanese Patent Application No. 10-278686.
May be used in combination. That is, by using the invention of Japanese Patent Application No. 10-278686, by incorporating restrictions on the timing of the circuit generated from the information embedded in the function description into the script generated by the present invention (for example, 12 in FIG. 13). Logic synthesis using information such as an include file name described in the line and a circuit exception path (false path, multi-cycle path) can be performed.

Similarly, it goes without saying that logic synthesis may be performed by adding a logic synthesis script generated by the present invention and a command manually created.

(5) In the above embodiment, VHDL
Has been described, but other HDLs, for example, Ver
It may be ilogHDL. In the above embodiment,
Usually, the case where logic synthesis is performed from a description called register transfer level to be subjected to logic synthesis is taken as an example, but it is also applicable to a case where a logic circuit is synthesized from a higher-level operation description (so-called high-level synthesis). It is.

(6) In the above-described embodiment, a case has been described in which a script for realizing a combining method called bottom-up is generated. That is, FIGS. 13 and 16 show scripts and makefiles on the assumption that logic synthesis is performed in order from the lower module to the upper module. However, other synthesis methods, for example, a top-down synthesis method (a Scripts and makefiles for implementing the method of reading and performing logic synthesis) can also be generated by the present invention.

The embodiment of the logic synthesis support system according to the present invention has been described above. The function of the logic synthesis support system is provided as a program stored in a computer-readable storage medium such as a floppy disk or an optical disk. May be performed.

[0050]

As described above, according to the present invention, the hierarchical structure of the functional description of the design is automatically analyzed, and the logic synthesis script of each module and the execution control commands of the logic synthesis script are automatically analyzed. Can be generated. Therefore, it is not necessary for the designer to manually create these logic synthesis scripts and execution control commands one by one, and these operations can be made much more efficient. In addition, errors in script creation can be significantly reduced as compared with the case where these are created manually. Further, know-how possessed by an expert in logic synthesis can be incorporated into the system, and a high-quality circuit can be easily designed. Further, even in a design in which the HDL description is reused, the logic synthesis of the reused portion can be easily performed by generating a logic synthesis script and an execution control command using the present invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic synthesis support system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a logic synthesis support system according to a second embodiment of the present invention;

FIG. 3 shows an example of a VHDL description stored in a function description storage unit 11 (file ex.vhdl)

FIG. 4 shows an example of a VHDL description stored in the function description storage unit 11 (file sub1.vhdl)

FIG. 5 shows an example of a VHDL description stored in the function description storage unit 11 (file sub2.vhdl).

FIG. 6 shows an example of a VHDL description stored in the function description storage unit 11 (file sub3.vhdl).

FIG. 7 is a block diagram showing a hierarchical structure of the VHDL description of FIGS. 3 to 6;

FIG. 8 is a diagram showing an example of information stored in a basic structure information storage unit 13;

FIG. 9 is a diagram showing a processing flow of the structure analysis unit 12;

FIG. 10 is a diagram showing an analysis result by the structural analysis unit 12.

FIG. 11 is a diagram showing a specification example of a script control unit 14;

FIG. 12 is a diagram showing a processing flow of a script generation unit 15;

FIG. 13 is a view showing the contents of a synthesized script file EX.scr of the top module EX generated in the script storage unit 16;

FIG. 14 is a view showing the contents of a composite script file SUB1.scr of a module SUB1 generated in the script storage unit 16;

FIG. 15 is a diagram showing a processing flow of a logic synthesis execution procedure control command generation unit 24;

FIG. 16 is a diagram showing contents of a makefile makefile_EX generated by a logic synthesis execution procedure control command generation unit 24;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Function description storage part 12 ... Structural analysis part 13 ... Basic structure information storage part 14 ... Script control part 15 ... Script generation part 16 ... Script storage part 21 ... Function description storage part 22 ... Structural analysis part 23 ... Basic structure information storage Unit 24: Logic synthesis execution procedure control command generation unit 25: Logic synthesis execution procedure control command storage unit

Continued on the front page (72) Inventor Yukihisa Fujimoto 2-9-9 Suehirocho, Ome-shi, Tokyo F-term in Toshiba Ome Plant (reference) 5B046 AA08 BA03 DA04 JA07

Claims (9)

[Claims] A function description storage unit for storing a function description of a design; a structure analysis unit for analyzing a hierarchical structure in the function description; and an analysis result obtained by the structure analysis unit. A logic synthesis support system comprising: script generation means for generating a logic synthesis script to be input to a CAD tool for logic synthesis. 2. A step of storing a function description of a design, a step of analyzing a hierarchical structure in the function description, and a CA for logically synthesizing the function description using a result of the analysis.
Generating a logic synthesis script to be input to the D tool. 3. A function description storage unit for storing a function description of a design, a structure analysis unit for analyzing a hierarchical structure in the function description, and the function description using an analysis result obtained by the structure analysis unit. A storage medium storing, as a computer-readable program, script generation means for generating a logic synthesis script to be input to a CAD tool for logic synthesis. 4. The logic synthesis support system according to claim 1, further comprising script control means for designating the contents of a logic synthesis script generated by said script generation means. 5. The logic synthesis support method according to claim 2, further comprising the step of designating the contents of the logic synthesis script generated by the step of generating the logic synthesis script. 6. The storage medium according to claim 3, wherein said program further includes script control means for designating the contents of a logic synthesis script generated by said script generation means. 7. A function description storage unit for storing a function description of a design, a structure analysis unit for analyzing a hierarchical structure in the function description, and the function description using an analysis result obtained by the structure analysis unit. And an execution control command generation means for generating a command for controlling the order of execution of logic synthesis between modules included in the logic synthesis support system. 8. A step of storing a function description of a design, a step of analyzing a hierarchical structure in the function description, and using the analysis result, controlling a logic synthesis execution order between modules included in the function description. Generating a command to perform the logic synthesis. 9. A function description storage unit for storing a function description of a design, a structure analysis unit for analyzing a hierarchical structure in the function description, and the function description using an analysis result obtained by the structure analysis unit. And an execution control command generation means for generating a command for controlling a logic synthesis execution order between modules included in the storage medium.