JP2000341138A - Decoding method and decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve accuracy of decoding by improving the decoding algorithm in a soft output Viterbi algorithm SOVA. SOLUTION: A Two-Step SOVA decoder 20 is provided with a post-stage branch metric calculation circuit 25 that re-calculates a branch metric from a delayed input signal S26, a post-stage ACS circuit 26 that conducts add- compare-select(ACS) processing for LVA decoding on the basis of a branch metric signal S27 and a state metric stored in the inside, a selection circuit 27 that selects a state signal corresponding to delayed state information S25 from among metric difference delay signals S30, a post-stage path memory circuit 28 that outputs decoded data S34 on the basis of delay state information S25 outputted from the pre-stage path memory circuit 23, and a likelihood update circuit 29 that outputs likelihood, information, before the cutting-off length U of the post-stage path memory circuit 28, as a logarithmic likelihood ratio S35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a decoding method and a decoding device suitable for maximum likelihood decoding of convolutional codes, and more particularly to a decoding method and a decoding device suitable for use in satellite broadcasting and the like.

[0002]

2. Description of the Related Art In recent years, studies have been made to reduce the symbol error probability by making the decoded output of an inner code of a concatenated code or the output of each repetition of the iterative decoding method a soft output. Attention has come to attention. As a decoding method for obtaining a soft output when decoding a convolutional code, for example, “Hagenauer and Hoeher, A Viterbi algo
rithmwith soft-decision outputs and its applicatio
ns, Proc.IEEE Global Telecomm.Conf.GLOBECOM, pp.4
7.1.1-47.1.7, Nov. 1989 ”is known. In the soft-decision Viterbi algorithm, the likelihood of each symbol is output instead of outputting each symbol as a decoding result. The output can be output as a soft output, which is referred to as a soft output.
Viterbi Algorithm; hereinafter abbreviated as SOVA. ) Will be described.

In the following description, as shown in FIG. 13, digital information is convolutionally encoded by a convolutional encoder 101, and its output is input to a decoder 103 via a memoryless communication path 102 having noise. Decoding and observation.

First, M states (transition states) representing the contents of the shift register of the convolutional encoder 101 are represented by m
(0,1, ···, M-1 ) expressed in, the state of the S _t of the time t, the input at time _t i t, the output at time t and X _t, the output system X _{^t t} ^' = _Xt , _{Xt + 1} , ..., _{Xt '} .

[0005] It is assumed that convolutional coding starts from state S ₀ = 0, outputs X ₁ ^T , and ends with S _T = 0. The memoryless communication path 102 with noise receives X ₁ ^T as input and outputs Y ₁ ^T. Where Y _t ^{t ′} = Y _t ,
_{Yt + 1} , ..., _{Yt '} . The transition probability of the no-memory channel 102 with noise is defined by R (· | ·) as expressed by the following equation (1) for all t (1 ≦ t ≦ T).

[0006]

(Equation 1)

Here, it is defined as in the following equation (2).

[0008]

(Equation 2)

[0009] This λ _t is the time t when Y ₁ ^T is received.
Represents the likelihood of the input information at, and is a soft output that should be originally obtained. In the practice, rather than the value of lambda _t themselves often seek Logramuda _t is its natural logarithm. In the following description, the Logramuda _t called log likelihood ratio.

In SOVA, the likelihood is not directly obtained, but the likelihood of the path not selected at each time in the selection process of obtaining the maximum likelihood path which is the sequence closest to the code sequence received by Viterbi decoding. The likelihood of each input information is approximately obtained by obtaining the likelihood of the decoded bit of the maximum likelihood path using the degree.

Here, the maximum likelihood path is defined as Pt _ML, and a path not selected by comparison with the maximum likelihood path at time j is defined as Pt _ML.
j, and the input bit at time t of the path Pt is I [P
t, t], the likelihood of the path Pt when receiving Y ₁ ^T is Pr {Pt | Y ₁ ^T }, and the set of Pt _j is ρ.
It is defined as in the following equation (3).

[0012]

(Equation 3)

At this time, in the SOVA, the log likelihood ratio of the decoded bit at time t is calculated by approximating the following equation (4). In SOVA, this makes it possible to obtain the log likelihood ratio of decoded bits as a difference between path metrics at the time of Viterbi decoding.

[0014]

(Equation 4)

Note that the log likelihood ratio in SOVA is calculated in the form of the following formulas (5) and (6), that is, the likelihood for the decoded bit of the maximum likelihood path.

[0016]

(Equation 5)

[0017]

(Equation 6)

Hereinafter, the algorithm of SOVA will be specifically described.

The description at the time j when the paths merge in the state k is determined as shown in FIG. In the figure,
The path on the selected side is represented by a path P ₁ (k, j), the path on the non-selected side is represented by a path P ₂ (k, j), and the path P ₁
The state where (k, j) passes at time j-1 is s
¹ (k), the state that the path P ₂ (k, j) passes at time j−1 is represented by s ² (k), and the path P ₁ (k, j),
The difference of the path metric between the paths P ₂ (k, j) is _represented by Δ _k (j)
It is represented by The path P ₁ (k, j) and the path P
The decoded bits at time t between ₂ (k, j) are represented by I [P ₁ (k, j), t] and I [P ₂ (k, j), t], respectively, and the path up to time j is selected. The log likelihood ratio of the decoded bit at time t of the surviving path in state k at this time is represented by L ^{^} _t (k, j).

Using the above notation, SOVA
Is as follows.

First, in SOVA, all t, k
, The log likelihood ratio is initialized to L ^{^} _t (k, 0).

Subsequently, in the SOVA, when a path is selected at each time j, all states k and all t
(T = 1 to j), the following equations (7) and (8)
Perform the operation shown in.

[0023]

(Equation 7)

[0024]

(Equation 8)

In the SOVA, when the last time is T and its maximum likelihood state is k ₀ , the log likelihood ratio that is the final soft output is obtained as L ^{^} _t (k ₀ , T). .

When such a SOVA is implemented in hardware, it is configured as a SOVA decoder 110 as shown in FIG.

The SOVA decoder 110 calculates a branch metric which is a Hamming distance between a received signal and a path, a branch metric calculation circuit 111, a branch metric calculated by the branch metric calculation circuit 111, and a branch metric up to that time. ACS (Ad
d Compare Select) circuit 112 and the ACS circuit 11
2 and a normalization circuit 113 for normalizing the new state metric signal s113 output from
State metric signal s114 output from
And a state metric storage circuit 114 for storing
It includes a path memory and likelihood updating circuit 115 that receives path selection information s116, metric difference information s117, and maximum likelihood state signal s118 from the S circuit 112, and outputs decoded data s119 and log likelihood ratio s120.

The SOVA decoder 110 receives the received value Y _t
A priori probability information _{logPr {i t = 0},} logPr
{I _t = 1} and the time you entered as s111, the decoded data s119 is decoded result, the log-likelihood ratio s120
And are output respectively.

When the received value and the prior probability information signal s111 are input, the branch metric calculation circuit 111
The branch metric of the received data is calculated, and the calculation result is output to the subsequent ACS circuit 112 as a branch metric signal s112.

Based on the branch metric signal s112 supplied from the branch metric calculation circuit 111 and the state metric signal s115 supplied from the state metric storage circuit 114, the ACS circuit 112 joins each of the two circuits which join a certain state. For the path, the branch metric and the state metric are added and compared, and a path having a high likelihood is selected based on the comparison result.
Let it be a new state metric. The ACS circuit 112 outputs the selected contents to the subsequent path memory and likelihood updating circuit 115 as path selection information s116. Also, ACS
The circuit 112 outputs the metric difference at the time of path selection for each state to the path memory and likelihood update circuit 115 as metric difference information s117. Further, the ACS circuit 112 outputs the number of the state having the minimum state metric to the path memory and the likelihood updating circuit 115 as the maximum likelihood state signal s118, and outputs the newly obtained state metric as a new state metric signal s113. Is output to the normalization circuit 113.

In order to explain a method of selecting a path in the ACS circuit 112, for example, a description will be given using a convolutional encoder 130 whose constraint length is "3" shown in FIG. This convolutional encoder 130 corresponds to the convolutional encoder 51 previously shown in FIG. Convolutional encoder 13
0 means three adders 131a, 131b, 131c,
It has two registers 132a and 132b. As shown in FIG. 17, a transition diagram (hereinafter, referred to as a trellis) of the convolutional encoder 130 has two paths merging for all states for each time slot. Therefore, the ACS circuit 112 adds and compares the state metric and the branch metric between the received signal and the path for each of the two paths that merge into a certain state, and performs a likelihood based on the comparison result. Choose the one with the highest

The normalization circuit 113 converts the new state metric signal s113 output from the ACS circuit 112
For example, the new state metric signal s113 is normalized by subtracting the minimum state metric, and a value within a preset range is output to the subsequent state metric storage circuit 114 as a normalized state metric signal s114.

The state metric storage circuit 114 stores the normalized state metric signal s114 supplied from the normalization circuit 113, and stores the state metric signal s1.
The value 15 is fed back to the ACS circuit 112.

The path memory and likelihood updating circuit 115
Based on the path selection information s116 output from the CS circuit 112, the decoded bits of the surviving path for each state are stored, and the likelihood of each decoded bit is determined using the metric difference information s117 output from the ACS circuit 112. To update. Further, a path memory and likelihood updating circuit 1
15 outputs, based on the maximum likelihood state signal s118 output from the ACS circuit 112, information before a certain length called a truncation length among decoded information corresponding to the maximum likelihood path as decoded data s119, The degree information is output as a log likelihood ratio s120.

The SOVA decoder 110 has the same configuration as that of the conventional Viterbi decoder 140 that realizes the Viterbi algorithm shown in FIG. 18 except for the path memory and the likelihood updating circuit 115. . That is, similar to the SOVA decoder 110, the conventional Viterbi decoder 140 includes a branch metric calculation circuit 141 for calculating a branch metric and an ACS circuit 1 for adding and comparing the branch metric and the state metric.
And a normalization circuit 14 for normalizing the new state metric signal s143 output from the ACS circuit 142.
And a state metric storage circuit 144 for storing the normalized state metric signal s144 output from the normalization circuit 143, and the ACS circuit 1
42, path selection information s146 and metric difference information s
147, and a path memory circuit 145 that outputs decoded data s148.

As described above, unlike the conventional Viterbi decoder 140, the SOVA decoder 110 can output likelihood information by including the path memory and the likelihood updating circuit 115.

Hereinafter, the path memory and likelihood updating circuit 1
15 will be described with reference to FIGS. In the path memory and likelihood update circuit 115, a memory cell including a selector and a register is arranged on a trellis,
Path selection information s116 output from ACS circuit 112
, The contents of the register storing the decoded bits and the contents of the register storing the likelihood information are changed.

Memory cell MS for storing decoded bits
_B is configured as shown in FIG. That is, the memory cell MS _B storing the decoded bit is stored in the ACS circuit 11
Selector 1 that inputs a select signal based on path selection information s116 output from 2 and selects one of two input bits based on the select signal.
51, and a register 152 for storing the input bits selected by the selector 151 as decoded bits. The memory cell MS _B structure for storing the decoded bits is the same as the structure of the conventional Viterbi decoder 140 shown in FIG. 18 above.

On the other hand, memory cell MS for storing likelihood information
_P is configured as shown in FIG. That is, the memory cell MS _P storing the likelihood information is stored in the ACS circuit 112.
A selector 153 that inputs a select signal based on the path selection information s116 output from, and selects one of the two pieces of likelihood information based on the select signal.
If, metric difference information s 2 two decoded bits b1, b2 inputted from the memory cell MS _B for storing the decoded bits output from b1 ≠ a b2 and ACS circuit 112
117, two metric differences Δ1, Δ2 are Δ1
A determination circuit 154 for determining whether or not <Δ2; and two decoded bits b1, b based on the determination of the determination circuit 154.
2 is b1 ≠ b2 and two metric differences Δ1,
When Δ2 is Δ1 <Δ2, the metric difference Δ1
And a selector 155 that selects the metric difference Δ2 in other cases, and a register 156 that stores the metric difference selected by the selector 155 as likelihood information.

Memory cell MS _B for storing such decoded bits and memory cell MS _P for storing likelihood information are arranged as shown in FIG. 21 when the constraint length is “3”. Note that the memory cells M for storing these decoded bits
Arrangement of the memory cell MS _P to store the S _B, and the likelihood information,
This corresponds to the trellis of the convolutional encoder 130 shown in FIG. In SOVA decoder 110, memory cell MS _B storing the decoded bit in this way
And by arranging the memory cells MS _P for storing likelihood information, it stores the information corresponding to the survival path of each state in the register. The memory cell MS _B storing the decoded bit and the memory cell MS _P storing the likelihood information are:
The number of stages corresponding to the truncation length is arranged. SOVA decoder 11
In 0, of the output of the final stage in the memory cell MS _P to store the memory cells MS _B and likelihood information storing these decoded bits, by selecting the output of the maximum likelihood state, corresponding to the maximum likelihood path And outputs the decoded data and the log likelihood ratio. Incidentally, in the arrangement of the memory cell MS _P to store the memory cells MS _B and likelihood information storing such decoded bit, when extracting only a portion of the memory cell MS _B for storing the decoded bits, in FIG. 18 previously It has the same configuration as the path memory circuit 145 in the conventional Viterbi decoder 140 shown.

The SOVA decoder 110 can implement the above-described SOVA algorithm with actual hardware.

Here, the SOVA decoder 110 has the configuration shown in FIG.
As shown in FIG. 1, a memory cell M for storing a decoded bit
A memory cell MS _P for storing S _B and likelihood information, respectively, is required by state number × terminating length. However, in SOVA decoder 110, the circuit size of memory cell MS _P storing the likelihood information previously shown in FIG. 20 is larger than the circuit size of memory cell MS _B storing the decoded bits shown in FIG. Therefore, when the number of states and the truncation length are increased, the circuit size of the SOVA decoder 110 is significantly increased as compared with the conventional Viterbi decoder 140 shown in FIG. was there. To solve this problem, Joeressen and Berrou have independently proposed the same approach. That is, Joeres
Sen et al., “Joreressen, Vaupel, Mey, High-speed VLS
I architectures for soft-outputViterbidecoding, in
Proc.Int.Conf.Applicat.Specific Array Processors.
Oakland, CA: IEEE Computer Society Press, Aug. 1992,
pp.373-384 ”and propose a method to solve the problem.
rou et al., “Berrou, Adde, Angui, Faudeil, A low com
plexity soft-output Viterbi decoder architecture,
in Proc.IEEE Int.Conf.Commun., Geneva, Switzerlan
d, May 1993, pp. 737-740 ", which proposes a method for solving the problem. Here, this method is called Two-Step SOVA according to Joeressen et al.

In Two-Step SOVA,
After once performing Viterbi decoding for the truncation length, the likelihood information is updated only for the selected path. By doing so, in the Two-Step SOVA, the memory cell that stores the decoded bit is stored in the above-described S-cell.
Although it requires twice as much as the OVA decoder 110, the memory cells that store the likelihood information need only have the truncation length. Therefore, in Two-Step SOVA, the number of memory cells storing likelihood information can be significantly reduced. As a result, in the Two-Step SOVA, the size of the path memory and the likelihood information updating circuit can be significantly reduced as a whole, considering the size of the circuit size of the memory cell that stores the likelihood information.

Two-Step SOVA decoder 160
Is a branch metric calculation circuit 161 that calculates a branch metric, and an AC that adds and compares the branch metric and the state metric, as shown in FIG.
S circuit 162, normalization circuit 163 for normalizing new state metric signal s 163 output from ACS circuit 162, and state metric storage circuit for storing normalized state metric signal s 164 output from normalization circuit 163 164, a preceding-stage path memory circuit 165 that stores decoded bits of a surviving path for each state and outputs delay state information s169, and a path selection information delay circuit 1 that delays path selection information s166.
66, a metric difference delay circuit 167 for delaying the metric difference information s167, a selection circuit 168 for selecting a signal of a state corresponding to the delay state information s169 from the metric difference delay signal s171, and a survivor for each state. A subsequent-stage path memory circuit 169 that stores the decoded bits of the path and outputs the maximum likelihood / merging path input information s173 and the decoded bits s174, and a likelihood update that updates the likelihood of the decoded bits and outputs a log likelihood ratio s175. And a circuit 170. This Two-Step SOVA
The decoder 160 receives value Y _t and a priori probability information logPr
{I _t = 0}, when you enter a logPr {i _t = 1} as s161, a decoding result decoded data s174
And the log likelihood ratio s175 are output. In addition,
Here, the cutoff length of the preceding-stage path memory circuit 165 is set to D
, And the cutoff length of the subsequent-stage path memory circuit 169 is represented by U.

When the received value and the prior probability information signal s 161 are input, the branch metric calculation circuit 161
The branch metric of the received data is calculated, and the calculation result is output to the subsequent-stage ACS circuit 162 as a branch metric signal s162.

Based on the branch metric signal s 162 supplied from the branch metric calculation circuit 161 and the state metric signal s 165 supplied from the state metric storage circuit 164, the ACS circuit 162 joins each of the two circuits which join a certain state. For the path, the branch metric and the state metric are added and compared, and a path having a high likelihood is selected based on the comparison result.
Let it be a new state metric. The ACS circuit 162 outputs the contents of the selection to the pre-stage path memory circuit 165 and the path selection information delay circuit 166 as path selection information s166. The ACS circuit 162 outputs the metric difference at the time of path selection for each state to the metric difference delay circuit 167 as metric difference information s167. Further, the ACS circuit 162 outputs the number of the state having the minimum state metric to the previous-stage path memory circuit 165 as the maximum likelihood state signal s168, and outputs the newly obtained state metric to the new state metric signal s163.
Is output to the normalization circuit 163.

The normalization circuit 163 converts the new state metric signal s163 output from the ACS circuit 162 into
For example, the new state metric signal s163 is normalized by subtracting the minimum state metric, and the new state metric signal s163 is set to a value within a preset range.
64.

The state metric storage circuit 164 stores the normalized state metric signal s164 supplied from the normalization circuit 163, and stores the state metric signal s1.
As 65, it is fed back to the ACS circuit 162.

The pre-stage path memory circuit 165 stores the decoded bits of the surviving path for each state based on the path selection information s166 output from the ACS circuit 162, and also stores the maximum likelihood state output from the ACS circuit 162. Based on the signal s168, the number of the state before the truncation length D retroactively from the maximum likelihood path is output to the selection circuit 168 and the subsequent path memory circuit 169 as delay state information s169.

The path selection information delay circuit 166 delays the path selection information s166 output from the ACS circuit 162 by the cutoff length D of the previous path memory circuit 165, and outputs the path selection information delay signal s170 to the subsequent path memory circuit 169. Output.

The metric difference delay circuit 167
Metric difference information s167 output from the circuit 162
Is delayed by the cutoff length D of the previous-stage path memory circuit 165, and is output to the selection circuit 168 as a metric difference delay signal s171.

The selection circuit 168 is connected to the pre-stage path memory circuit 1
A signal corresponding to the state corresponding to the delay state information s169 is selected from the metric difference delay signal s171 based on the delay state information s169 supplied from the metric difference delay circuit 167 and the metric difference delay signal s171 supplied from the metric difference delay circuit 167. Then, the metric difference delay selection signal s172 is output to the likelihood update circuit 170.

The subsequent-stage path memory circuit 169 stores the decoded bits of the surviving path for each state based on the path-selection information delay signal s170 supplied from the path-selection information delay circuit 166, and stores the decoded bits of the previous-stage path memory circuit 165. Based on the delay state information s169 output from, information on the maximum likelihood path further traced by the truncation length U is output as decoded bits s174. Further, based on the delay state information s169, the subsequent-stage path memory circuit 169 converts the input information corresponding to the maximum likelihood path and the input information corresponding to the path joining the maximum likelihood path into the maximum likelihood by the length U, respectively. Likelihood update circuit 1 as merging path input information s173
70.

The likelihood update circuit 170 includes a metric difference delay selection signal s172 supplied from the selection circuit 168,
Based on the maximum likelihood / merging path input information s173 supplied from the subsequent path memory circuit 169, the input information corresponding to the maximum likelihood path, that is, the likelihood of the decoded bit is updated, and the cutoff length of the subsequent path memory circuit 169 is updated. The likelihood information before U is output as log likelihood ratio s175.

As described above, Two-Step SOVA
The decoder 160 has exactly the same configuration as that of the conventional Viterbi decoder 140 shown in FIG. 18 with respect to the branch metric calculation circuit 161 to the previous-stage path memory circuit 165.

Hereinafter, the latter-stage path memory circuit 169 and the likelihood updating circuit 170 will be described with reference to FIGS. In subsequent path memory circuit 169, by arranging the memory cells MS _B for storing the decoded bits as shown in FIG. 19 previously Similarly to the trellis and normal Viterbi decoder 140, based on the path selection information delay signal s170 A memory cell MS that transitions information bits corresponding to a surviving path for each state and stores all decoded bits.
_The information bit from _B is input to a selection circuit (not shown), and based on the delay state information s169 output from the previous-stage path memory circuit 165, the input information corresponding to the maximum likelihood path and the path joining the maximum likelihood path And the input bit to be output to the likelihood updating circuit 170 as maximum likelihood / merging path input information s173. Memory cell MS _B and a selection circuit for storing the decoded bits in the subsequent path memory circuit 169,
When the constraint length is "3", the arrangement is performed as shown in FIG.

On the other hand, in likelihood updating circuit 170, memory cell MS _P storing likelihood information as shown in FIG.
Is provided. The memory cell MS _P that stores likelihood information inputs the maximum likelihood path input information b1 and the merge path input information b2 based on the maximum likelihood / merging path input information s173 supplied from the subsequent-stage path memory circuit 169, and selects Circuit 16
8 metric differential delay selection signal s172
A metric difference Δ1 based on inputs the likelihood information Δ2 supplied from the memory cell MS _P for storing the preceding likelihood information, survival path input information b1 and merging path input information b
2 is b1 ≠ b2, and the metric difference Δ1 and the likelihood information Δ2 determine whether Δ1 <Δ2, and the maximum likelihood path input information b1 and the merged path input are determined by the determination circuit 171. The information b2 is b1 ≠ b2, and the metric difference Δ1 and the likelihood information Δ2 are Δ1 <Δ
2, the selector 172 selects the metric difference Δ1; otherwise, the selector 172 selects the likelihood information Δ2.
And a register 173 for storing the metric difference or likelihood information selected by the selector 172.

[0058] In likelihood updating circuit 170 for the input bits of the memory cell MS _P for storing the likelihood information is arranged in a line as shown in FIG. 25, corresponding to the maximum likelihood path Motoma' by preceding path memory circuit 165 Update of only likelihood is performed for the cutoff length U of the subsequent-stage path memory circuit 169,
The updated likelihood information is output as a log likelihood ratio.

As shown in FIG. 26, such a Two-Step SOVA decoder 160 determines the maximum likelihood path to be decoded when it is sufficiently long from the maximum likelihood state at a certain time t, that is, by the truncation length D. Determine.
Here, if the metric difference and the path selection information are delayed, the two-step SOVA decoder 160
By comparing the maximum likelihood path with the path joining the maximum likelihood path at time t-D, the likelihood can be updated only for the maximum likelihood path.

Two-Step SOVA decoder 160
In “Berrou, Adde, Angui, Faudei
l, A low complexity soft-output Viterbi decoder ar
chitecture, in Proc.IEEE Int.Conf.Commun., Geneva,
Switzerland, May 1993, pp. 737-740 ”, it is generally known that it is sufficient if the cut-off length U of the subsequent-stage path memory circuit 169 is shorter than the cut-off length D of the preceding-stage path memory circuit 165. Therefore, even if a memory for delay is included, the same code can be realized with a circuit size about twice as large as that of the conventional Viterbi decoder 140 shown in FIG.

[0061]

By the way, in the SOVA, as described above, the log likelihood ratio of decoded bits at time t is calculated by approximation as shown in the following equation (9).

[0062]

(Equation 9)

However, as an approximation that gives a result with better accuracy than this approximation, “Robertson, Villebrun a
nd Hoeher, A comparison of optimal and sub-optimal
MAPdecoding algorithms operating in the log domai
n, IEEE Int.Conf.on Communications, pp.1009-1013,
The approximation used in the Max-Log-BCJR algorithm described in "June 1995" is known.

[0064] represents in the Max-Log-BCJR algorithm, a set of paths i _t = 0 ρ in _{[i t = 0], i} t
= 1 of the set of paths assuming represented by [rho [i _t = 1], the log-likelihood ratio Logramuda _t is approximated as shown in the following equation (10).

[0065]

(Equation 10)

Here, the right side of the above equation (9) and the above equation (10)
Comparing with the right side of the above, the numerator on the right side of the above equation (9) is different from the numerator on the right side of the above equation (10),
It can be seen that the high accuracy of approximation of the Max-Log-BCJR algorithm with respect to SOVA is caused by a difference in a set of paths used for calculating a log likelihood ratio.

[0067] That is, in the SOVA, among paths merging the maximum likelihood path in the course of Viterbi decoding selection, select the path that input at time t is i _t = 1, are you for comparison respect, in the Max-Log-BCJR algorithm, are all paths input at time t is i _t = 1 for comparison. This allows Max-Log-BCJR
The algorithm has a higher approximation accuracy than SOVA.
Furthermore, it can be said that the performance of SOVA is deteriorated with respect to the Max-Log-BCJR algorithm.

As a specific example, SOVA is Max-Log-BC
An example of calculating an output with poor accuracy for the JR algorithm will be described with reference to FIG. In the figure, represents the maximum likelihood path is an input-output are all "0" and pass 0 represents the path metric and PM _0. In the same drawing, among the paths whose input at time t is “1”, the path with the smallest metric is represented as path 1 and the path metric is represented as PM ₁ .

In this case, in the Max-Log-BCJR algorithm, the soft output is calculated in the form of “PM ₁ −PM ₀ ” by using the approximation shown in the above equation (10).

Here, among the paths whose input at time t is “1”, Ps whose values are smaller than the metric of path 1
Shall pass 2 and pass 1 has a metric that M ₂ merges with path 1 at time t _j before the time t _k which merges with path 0 is present. At this time, pass 1 is
The path will not be selected during the Viterbi decoding process at time t _j . Therefore, in SOVA, when the soft output is calculated using the approximation shown in the above equation (9),
A value larger than “PM ₁ −PM ₀ ” is calculated.

As described above, in the case of SOVA, the accuracy of the soft decision is sometimes deteriorated as compared with the case where the soft output is calculated by the Max-Log-BCJR algorithm.

The present invention has been made in view of such circumstances, and improves the decoding algorithm in the conventional SOVA, improves the accuracy of the decoding, and sets the Max-Log-BCJR
An object of the present invention is to provide a decoding method approaching an algorithm and a decoding device to which the decoding method is applied.

[0073]

According to the present invention, there is provided a decoding method for soft-output Viterbi decoding of an input convolutional code to output decoded data and likelihood information. Using a maximum likelihood path that is a sequence closest to the sequence of the convolutional code and a path other than the maximum likelihood path,
It is characterized by obtaining likelihood information.

In such a decoding method according to the present invention, when soft-output Viterbi decoding is performed on an input convolutional code, a maximum likelihood path and a path other than the maximum likelihood path are selected.

A decoding apparatus according to the present invention for achieving the above object is a decoding apparatus which performs soft-output Viterbi decoding of an input convolutional code and outputs decoded data and likelihood information. It is characterized by including a likelihood information output unit that obtains likelihood information using a maximum likelihood path that is a sequence closest to the sequence and a path other than the maximum likelihood path.

The decoding apparatus according to the present invention selects a maximum likelihood path and a path other than the maximum likelihood path to obtain likelihood information when performing soft-output Viterbi decoding of an input convolutional code.

[0077]

Embodiments of the present invention will be described below in detail with reference to the drawings.

This embodiment is based on the Two-Step Soft-Output Viterbi algorithm.
Algorithm; hereinafter, abbreviated as Two-Step SOVA. ) Implemented in hardware in Two-Step
It is a SOVA decoder. This Two-Step SOV
The A decoder is an LVA (List Viterbi decoding) described later.
Algorithm: List Viterbi decoding algorithm).

In the following description, as shown in FIG. 1, digital information is convolutionally coded by a convolutional coder 1 and its output is passed through a no-memory storage channel 2 with a Two-Step SOVA decoder. Consider the case where the data is input to 3, decoded, and observed.

First, the LVA will be described. LVA
“Seshadri, Sundberg, List Viterbi Algorithms
with Applications, IEEE Trans.Com., Vol.42, No.2 / 3
/ 4, pp. 313-323, Feb / Mar / Apr, 1994 ”, which is an extension of the normal Viterbi decoding algorithm. Although one maximum likelihood path is originally decoded, a path having the highest likelihood in the second and subsequent paths is also obtained.

In normal Viterbi decoding, FIG.
As shown in (1), for each state (transition state), one path is selected from the input two paths, whereas the LV
In A, two paths are selected for each state, as shown in FIG. Therefore, in LVA, unlike in the case of normal Viterbi decoding, a 2-to-1 path is selected for each state, but a 4-to-2 path is selected. In LVA, not only the path with the second highest likelihood is selected but also the path with the third and fourth highest likelihood can be selected.

An LVA decoder for realizing such an LVA is configured as shown in FIG. Here, an LVA decoder that decodes the maximum likelihood path and the path with the second highest likelihood will be described.

The LVA decoder 10 shown in FIG. 1 includes a branch metric calculation circuit 11 for calculating a branch metric of received data, and an ACS (Add Compare Selec) for adding and comparing the branch metric and the state metric.
t) A circuit 12 and a path memory circuit 13 are provided. The LVA decoder 10 receives the received value Y _t and the prior probability information log
Pr {i _t = 0}, when you enter a logPr {i _t = 1} as s11, from the code sequence may be generated from the transmission side of the encoder, a high likelihood to the maximum likelihood path and a second path And decrypted data s based on the selection.
16, s17 are generated and output. Note that the LVA decoder 10 uses the Two-Step SOVA shown in FIG.
It can be replaced by the decoder 3.

When the received value and the prior probability information signal s11 are input, the branch metric calculation circuit 11 calculates a branch metric of the received data, and outputs the calculation result as a branch metric signal s12.

The ACS circuit 12 outputs the branch metric signal s1 supplied from the branch metric calculation circuit 11.
2 and the state metrics stored therein, add and compare the branch metric and the state metric for each of the four paths joining a certain state. Is selected as the new state metric. The ACS circuit 12 outputs the selected content to the subsequent path memory circuit 13 as path selection information s13. In addition, the ACS circuit 12 sets the state number having the smallest state metric as the maximum likelihood state signal s14 and the state number having the second smallest state metric as the quasi-maximum likelihood state signal s15 to the path memory circuit 13 at the subsequent stage. Output.

The path memory circuit 13 changes the decoded bits based on the path selection information s13 output from the ACS circuit 12, and simultaneously converts the decoded bits into the maximum likelihood state signal s14 and the quasi maximum likelihood state signal s15 output from the ACS circuit 12. On the basis of the information corresponding to the maximum likelihood path and the path having the second highest likelihood, information before a certain length called a truncation length is output as decoded data s16 and s17.

The AC in such an LVA decoder 10
The S circuit 12 is configured by an ACS cell AC as shown in FIG. The ACS cell AC has four adders 14a and 14 for adding branch metrics to four paths.
b, 14c, 14d, a comparator 15 for comparing the added result, and based on a comparison result by the comparator 15,
The number of the state with the smallest state metric and 2
A selection circuit 16 for selecting a state number having the second smallest state metric; and a register 17 for storing the two results selected by the selection circuit 16, respectively.
a, 17b.

In the ACS cell AC, adders 14a, 14a are added to four paths joining a certain state.
b, 14c, and 14d, the branch metrics are added, and the selection circuit 1
6 to select the path with the highest likelihood up to the second and output the maximum likelihood path selection signal and the quasi-maximum likelihood path selection signal, and the selected maximum likelihood state metric and the quasi maximum likelihood state metric. I do.

Such an ACS cell AC is arranged in the ACS circuit 12 as shown in FIG. The LVA decoder 10 outputs a maximum likelihood path selection signal and a quasi-maximum likelihood path selection signal by arranging the ACS cells AC in this manner.

The path memory circuit 13 in the LVA decoder 10 is constituted by path memory cells MC as shown in FIG. In the LVA, since two paths are stored in one state, the path memory cell MC for each state includes two selectors 18a and 18b and two paths 18a and 18b.
And two registers 19a and 19b. The path memory cell MC inputs the maximum likelihood path selection information and the quasi-maximum likelihood path selection information based on the path selection information s13 output from the ACS circuit 12 to the selectors 18a and 18b, respectively. Make a transition.

Such path memory cells MC are arranged in the path memory circuit 13 by the cutoff length as shown in FIG. By arranging the path memory cells MC in this manner, the LVA decoder 10 selects a path of 4 to 2 and outputs decoded data.

As shown in FIG. 8, the Two-Step SOVA decoder 20 to which the LVA decoder 10 is applied is a pre-stage branch metric calculation circuit which is a branch metric calculation means for calculating a branch metric of received data. 21, a preceding-stage ACS circuit 22 serving as an addition / comparison / selection means for adding and comparing the branch metric and the state metric, and storing decoded bits based on path selection information s23 output from the preceding-stage ACS circuit 22; Delay state information s based on the maximum likelihood state signal s24 output from the previous-stage ACS circuit 22
25, an input delay circuit 24 for delaying the input received value and the prior probability information signal s21 by the cutoff length D of the previous path memory circuit 23, Delay circuit 2
4, a post-stage branch metric calculation circuit 25, which is a delay branch metric calculation means for calculating a branch metric again from the delay input signal s26 output from the fourth stage, and a branch metric signal s27 supplied from the post-stage branch metric calculation circuit 25. A post-stage ACS circuit 26, which is processing means for performing an ACS process for LVA decoding based on the stored state metrics,
Metric difference delay signal s3 output from S circuit 26
A selection circuit 27 for selecting a signal of a state corresponding to the delay state information s25 from among 0, and a subsequent stage which is a path memory means for outputting decoded data s34 based on the delay state information s25 output from the previous stage path memory circuit 23. A path memory circuit 28 and a likelihood updating circuit 29 which is likelihood information output means for outputting likelihood information before the cutoff length U of the subsequent path memory circuit 28 as the second cutoff length as a log likelihood ratio s35. Prepare.

This Two-Step SOVA decoder 2
0, the received value Y _t and a priori probability information logPr {i _t =
0}, when you enter a logPr {i _t = 1} as s21, the decoded data s34 is decoded result, and outputs the logarithmic likelihood ratio s35. Two-Step
The SOVA decoder 20 uses the conventional Tw shown in FIG.
The above-described LVA decoder 10 is applied to the subsequent-stage path memory circuit 169 in the o-Step SOVA decoder 160.

The preceding-stage branch metric calculation circuit 21
When the received value and the prior probability information signal s21 are input,
The branch metric of the received data is calculated, and the calculation result is output as a branch metric signal s22.

Based on the branch metric signal s22 supplied from the previous-stage branch metric calculation circuit 21 and the state metric stored therein, the preceding-stage ACS circuit 22 applies two paths that join a certain state to each other. The branch metric and the state metric are added and compared. Based on the result of the comparison, a branch metric having a high likelihood is selected and stored as a new state metric. Former stage A
The CS circuit 22 outputs the selected contents as path selection information s23 to the preceding path memory circuit 23 at the subsequent stage. Also,
The pre-stage ACS circuit 22 outputs the number of the state having the minimum state metric to the post-stage pre-stage path memory circuit 23 as the maximum likelihood state signal s24.

The previous-stage path memory circuit 23 stores the decoded bits of the surviving path for each state based on the path selection information s23 output from the previous-stage ACS circuit 22. Further, based on the maximum likelihood state signal s24 output from the previous-stage ACS circuit 22, the previous-stage path memory circuit 23 selects the number of the state before the truncation length D retroactively from the maximum-likelihood path as delay state information s25 as a selection circuit. 27
And output to the subsequent-stage path memory circuit 28.

The input delay circuit 24 delays the input received value and the prior probability information signal s21 by the cut-off length D of the pre-stage path memory circuit 23, and outputs it as a delayed input signal s26 to the post-stage post-stage branch metric calculation circuit 25. .

The subsequent-stage branch metric calculation circuit 25
A branch metric is calculated again from the delayed input signal s26, and this calculation result is used as the delayed branch metric signal s27.
Is output to the subsequent-stage ACS circuit 26.

The post-stage ACS circuit 26 performs an ACS process for LVA decoding based on the delayed branch metric signal s27 supplied from the post-stage branch metric calculation circuit 25 and the state metric stored therein. That is, the subsequent-stage ACS circuit 26 is connected to a certain state.
The branch metric and the state metric are added and compared for each of the paths, and based on the comparison result, 2
The one with the highest likelihood is selected as the new state metric. The subsequent-stage ACS circuit 26 outputs the path selection information of the maximum likelihood path for each state to the subsequent-stage path memory circuit 28 as a maximum-likelihood selection signal s28. Also, the latter-stage ACS
The circuit 26 outputs the path selection information of the path with the second highest likelihood for each state to the subsequent path memory circuit 28 as a path quasi-maximum likelihood selection signal s29. Further, the subsequent-stage ACS circuit 26 outputs the metric difference in the path selection process for each state to the selection circuit 27 as a metric difference delay signal s30.

The selection circuit 27 includes the pre-stage path memory circuit 23
State information s25 supplied from the
Metric difference delay signal s30 supplied from the circuit 26
, A signal of a state corresponding to the delay state information s25 is selected from the metric difference delay signals s30, and the difference signals of the two paths joining the maximum likelihood path are respectively set as metric difference delay selection signals s31 and s32. To the likelihood update circuit 29.

The subsequent-stage path memory circuit 28 transitions the decoded bits of the surviving path for each state based on the maximum-likelihood selection signal s28 and the quasi-most-likelihood selection signal s29 supplied from the subsequent-stage ACS circuit 26, Based on the delay state information s25 output from the previous-stage path memory circuit 23, information that further extends the maximum likelihood path by the truncation length U is output as decoded data s34. At the same time, the subsequent-stage path memory circuit 28 separates the input information corresponding to the maximum likelihood path and the input information corresponding to the two paths merging with the maximum likelihood path by the censoring length U based on the delay state information s25. The likelihood / merging path input information s33 is output to the subsequent likelihood update circuit 29.

The likelihood updating circuit 29 includes metric difference delay selection signals s31 and s32 supplied from the selection circuit 27.
And input information corresponding to the maximum likelihood path, that is, the likelihood of the decoded bit, is updated based on the maximum likelihood / merging path input information s33 supplied from the subsequent-stage path memory circuit, The likelihood information before the length U is output as a log likelihood ratio s35.

The latter-stage path memory circuit 28 in such a Two-Step SOVA decoder 20 has been described with reference to FIG.
The memory cell MC _B for storing the decoded bits made of the same configuration as the path memory cell MC shown in, similar to the arrangement shown in FIG. 7 above, placed on the trellis, the information bits corresponding to the survival path It causes a transition to enter all of the decoded information bits from the memory cells MC _B to store bits to a selection circuit not shown here, on the basis of the delay state information s25 outputted from the pre-stage path memory circuit 23, the maximum likelihood path The corresponding input information and the input bits corresponding to the two paths merging with the maximum likelihood path are output to the likelihood updating circuit 29 as maximum likelihood / merging path input information s33. Memory cells MC _B and selection circuit for storing decoded bits in subsequent path memory circuit 28, when the constraint length is "3", are arranged as shown in FIG.

On the other hand, in the likelihood updating circuit 29, FIG.
A memory cell MC _P for storing likelihood information as shown in 0. Memory cells MC _P for storing the likelihood information, the selection circuit and the determination circuit 30 for determining for determining the information to be selected by a subsequent stage of the selection circuit 31 to select the information to be output by the determination of the determination circuit 30 31, and a register 32 for storing information selected by the selection circuit 31 as likelihood information.

[0105] In the memory cell MC _P for storing likelihood information, the determination circuit 30, maximum likelihood path input information (b1) based on the maximum likelihood-merging path input information s33 supplied from subsequent path memory circuit 28 and the merging Path input information 1, 2 (b
2, b3) and a metric difference 1 (Δ) based on the metric difference delay selection signal s31 supplied from the selection circuit 27.
1) and a metric difference 2 (Δ2) based on the metric difference delay selection signal s32 supplied from the selection circuit 27
And likelihood information Δ3. Then, the judgment circuit 30
Determines whether the input information satisfies the conditions shown in the following equations (11) and (12).

[0106]

[Equation 11]

[0107]

(Equation 12)

Here, when it is determined that the input information satisfies the above equation (11), the determination circuit 30 notifies the selection circuit 31 to that effect. Based on the notification, the selection circuit 31 determines the metric difference 1 (Δ) based on the metric difference delay selection signal s31 supplied from the selection circuit 27.
Select 1).

When it is determined that the input information satisfies the above expression (12) instead of the above expression (11), the determination circuit 30 notifies the selection circuit 31 of that. The selection circuit 31 selects a metric difference 2 (Δ2) based on the metric difference delay selection signal s32 supplied from the selection circuit 27 based on the notification.

Further, when it is determined that the input information does not satisfy both the above equations (11) and (12), the determination circuit 30 notifies the selection circuit 31 of that. The selection circuit 31 determines the likelihood information Δ
Select 3.

As described above, the selection circuit 31 selects information to be output based on the judgment of the judgment circuit 30, and supplies the selected information to the register 32. Register 32
Stores and outputs the input information as likelihood information.

[0112] In likelihood update circuit 29, memory cells arranged MC _P to store such likelihood information to terminating length U min only one row as shown in FIG. 11 was obtained by the preceding stage path memory circuit 23 top Only the likelihood of the input bit corresponding to the likelihood path is updated for the cutoff length U, and the updated result is output as a log likelihood ratio s35.

Such a Two-Step SOVA decoder 20 is different from the conventional SOVA, for example, in FIG.
In the case shown in (1), the accuracy is improved. In the figure, represents the maximum likelihood path is an input-output are all "0" and pass 0 represents the path metric and PM _0. In the same drawing, among the paths whose input at time t is “1”, the path with the smallest metric is represented as path 1 and the path metric is represented as PM ₁ .

Now, among the paths whose input at time t is “1”, PMs having a value smaller than the metric of path 1
Shall pass 2 and pass 1 has a metric of ₂ merges with path 1 at time t _j before the time t _k which merges with path 0 is present. In such a case, in the conventional SOVA, it is obvious that the path 1 is a path that is not selected in the Viterbi decoding process at the time t _j and is reflected in the soft output calculation at the time t. Was not done. On the other hand, the Two-Step SOVA decoder 20
In the case, among the paths that merge with the path 0 at the time t, if the path 1 is the path having the second highest likelihood following the path 2, the path 1 is the soft output of the path 0 at the time t. The value of “PM ₁ −PM ₀ ” can be calculated from the calculation target.

As described above, Two-Step SOVA
The decoder 20 applies LVA to obtain soft output in SOVA, and reflects the likelihood of a path not selected in the normal Viterbi decoding process as a target of soft output calculation, thereby reflecting the soft output in conventional SOVA. The effect of the path not performed can be reflected in the result, and the accuracy of decoding can be improved. Therefore, Two-Step SO
The VA decoder 20 can make the decoding accuracy close to, for example, the Max-Log-BCJR algorithm.

Note that the present invention is not limited to the above-described embodiment, and can be applied, for example, even if the constraint length and the truncation length are arbitrary values. In addition, the present invention can select not only the path with the second highest likelihood but also the second and subsequent paths, for example, the third and fourth paths with the highest likelihood. It is. As described above, it goes without saying that the present invention can be appropriately changed without departing from the spirit of the present invention.

[0117]

As described in detail above, the decoding method according to the present invention is a decoding method for soft-output Viterbi decoding of an input convolutional code to output decoded data and likelihood information. Likelihood information is obtained using the maximum likelihood path that is the closest to the code sequence and paths other than the maximum likelihood path.

Therefore, the decoding method according to the present invention
When performing soft-output Viterbi decoding of an input convolutional code,
By selecting the maximum likelihood path and a path other than the maximum likelihood path, it is possible to reflect the influence of the path that has not been reflected in the related art on the result, thereby improving the decoding accuracy.

Further, the decoding apparatus according to the present invention is a decoding apparatus for outputting decoded data and likelihood information by soft-output Viterbi decoding of an input convolutional code. There is provided a likelihood information output unit for obtaining likelihood information using a certain maximum likelihood path and a path other than the maximum likelihood path.

Therefore, the decoding device according to the present invention
When performing soft-output Viterbi decoding of an input convolutional code,
By selecting the maximum likelihood path and a path other than the maximum likelihood path to obtain likelihood information, it is possible to obtain likelihood information reflecting the influence of a path that was not reflected conventionally, thereby improving decoding accuracy. Can be done.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating Two-Stele as an embodiment of the present invention.
It is a block diagram explaining the structure of the communication model to which a p SOVA decoder is applied.

FIGS. 2A and 2B are diagrams illustrating a path selection method in each state. FIG. 2A is a diagram illustrating a path selection method in a case of normal Viterbi decoding, and FIG.
FIG. 6 is a diagram illustrating a path selection method in the case of VA.

FIG. 3 is a block diagram illustrating a configuration of an LVA decoder.

FIG. 4 is a block diagram illustrating a configuration of an ACS cell included in an ACS circuit included in the LVA decoder illustrated in FIG. 3;

FIG. 5 is a diagram illustrating an example of an arrangement of ACS cells in an ACS circuit provided in the LVA decoder illustrated in FIG. 3;

6 is a block diagram illustrating a configuration of a path memory cell included in a path memory circuit included in the LVA decoder illustrated in FIG.

7 is a diagram illustrating an example of an arrangement of path memory cells in a path memory circuit included in the LVA decoder illustrated in FIG.

FIG. 8 shows Two-Steal shown as an embodiment of the present invention.
It is a block diagram explaining the structure of a p SOVA decoder.

FIG. 9 is a diagram illustrating an example of an arrangement of memory cells for storing decoded bits and a selection circuit when a constraint length is “3” in a subsequent-stage path memory circuit included in the Two-Step SOVA decoder.

FIG. 10 is a block diagram illustrating a configuration of a memory cell that stores likelihood information included in a likelihood update circuit provided in the Two-Step SOVA decoder.

FIG. 11 is a block diagram illustrating a configuration of a likelihood update circuit included in the Two-Step SOVA decoder.

FIG. 12 is a diagram for explaining the operation of the Two-Step SOVA decoder.

FIG. 13 is a block diagram illustrating a configuration of a communication model.

FIG. 14 is an explanatory diagram for specifically describing an algorithm of SOVA, and is a diagram for explaining a description method in a case where paths merge at a state k at a time j.

FIG. 15 is a block diagram illustrating a configuration of a conventional SOVA decoder.

FIG. 16 is a block diagram illustrating a configuration of a convolutional encoder with a constraint length of “3”.

17 is a diagram illustrating a trellis of the convolutional encoder illustrated in FIG.

FIG. 18 is a block diagram illustrating a configuration of a conventional Viterbi decoder.

FIG. 19 is a block diagram illustrating a configuration of a memory cell that stores decoded bits.

FIG. 20 is a block diagram illustrating a configuration of a memory cell that stores likelihood information.

21 is a diagram illustrating an example of the memory cell arrangement shown in FIGS. 19 and 20 when the constraint length is “3”.

FIG. 22 is a block diagram illustrating a configuration of a conventional Two-Step SOVA decoder.

FIG. 23 shows the conventional Two-Step S shown in FIG.
FIG. 11 is a diagram illustrating an example of an arrangement of a memory cell for storing decoded bits and a selection circuit when a constraint length is “3” in an OVA decoder.

FIG. 24 shows the conventional Two-Step S shown in FIG.
It is a block diagram explaining the structure of the memory cell which stores the likelihood information with which an OVA decoder is provided.

FIG. 25 shows the conventional Two-Step S shown in FIG.
It is a block diagram explaining the structure of the likelihood update circuit with which an OVA decoder is provided.

FIG. 26 shows the conventional Two-Step S shown in FIG.
It is a figure explaining the contents of operation of an OVA decoder.

FIG. 27 is a diagram illustrating an example in which a conventional SOVA calculates an output with lower accuracy than the Max-Log-BCJR algorithm.

[Explanation of symbols]

Reference Signs List 20 Two-Step SOVA decoder, 21 pre-stage branch metric calculation circuit, 22 pre-stage ACS circuit, 23 pre-stage path memory circuit, 24 input delay circuit, 25 post-stage branch metric calculation circuit, 26
Post-stage ACS circuit, 27, 31 selection circuit, 28
Post-pass memory circuit, 29 Likelihood update circuit, 30
Judgment circuit, 32 registers

Claims (12)

[Claims] 1. A decoding method for soft-output Viterbi decoding of an input convolutional code to output decoded data and likelihood information, comprising: a maximum likelihood path that is a sequence closest to the convolutional code sequence; A decoding method characterized in that the likelihood information is obtained using a path other than the maximum likelihood path. 2. The decoding method according to claim 1, wherein a path other than the maximum likelihood path is a path having the highest likelihood after the second path among the paths joining the maximum likelihood path. 3. A delay branch metric is calculated based on a delay input signal obtained by delaying the convolutional code by a truncation length, and each transition of the convolutional code is calculated based on the delay branch metric and a stored state metric. The delay branch metric and the state metric are added and compared for each of the four paths joining the state, and the maximum likelihood path is selected in each transition state of the convolutional code based on the comparison result. 2. The decoding method according to claim 1, further comprising outputting a path maximum likelihood selection signal indicating the content and a path quasi maximum likelihood selection signal indicating the content of selecting a path having a second or higher likelihood. 4. A transition of decoded data of a surviving path, which is a path selected for each transition state, based on the path maximum likelihood selection signal and the path quasi maximum likelihood selection signal, and further demultiplexes the maximum likelihood path. In addition to outputting the information retroactive for the censoring length of 2 as decoded data, the input information corresponding to the maximum likelihood path and the input information corresponding to the two paths merging with the maximum likelihood path are combined with the maximum likelihood / merging path. The input information is output for the second censoring length, and the likelihood of the decoded data corresponding to the maximum likelihood path is updated based on the maximum likelihood / merging path input information. 4. The decoding method according to claim 3, wherein likelihood information is output. 5. A branch metric is calculated based on the convolutional code. Based on the branch metric and a stored state metric, each of two paths joining each transition state of the convolutional code is calculated. To add and compare the branch metric and the state metric,
Based on the comparison result, path selection information indicating the content of selecting a path with a high likelihood in each transition state of the convolutional code and a maximum likelihood transition state signal indicating the number of the transition state having the minimum state metric are output. And storing the decoded data of the surviving path for each transition state based on the path selection information, and retrospectively from the maximum likelihood path based on the maximum likelihood transition state signal and the number of the transition state before the censoring length. 4. The decoding method according to claim 3, wherein delay transition state information indicating the following is output. 6. The decoding method according to claim 1, wherein a list Viterbi decoding algorithm is applied. 7. A decoding apparatus for soft-output Viterbi decoding of an input convolutional code to output decoded data and likelihood information, comprising: a maximum likelihood path that is a sequence closest to the convolutional code sequence; A decoding apparatus comprising: a likelihood information output unit that obtains the likelihood information using a path other than the maximum likelihood path. 8. The decoding apparatus according to claim 7, wherein a path other than the maximum likelihood path is a path having the highest likelihood after the path joining the maximum likelihood path. 9. A delay branch metric calculation means for calculating a delay branch metric based on a delay input signal obtained by delaying the convolutional code by a truncation length, and based on the delay branch metric and a stored state metric. The delay branch metric and the state metric are added and compared for each of the four paths merging with each transition state of the convolutional code. Processing means for outputting a path maximum likelihood selection signal indicating the content of selecting the maximum likelihood path, and a path quasi-maximum likelihood selection signal indicating the content of selecting the second or higher likelihood path. The decoding device according to claim 7, wherein 10. A transition of decoded data of a surviving path, which is a path selected for each transition state, based on the path maximum likelihood selection signal and the path quasi-maximum likelihood selection signal, and further demultiplexes the maximum likelihood path. In addition to outputting the information retroactive for the censoring length of 2 as decoded data, the input information corresponding to the maximum likelihood path and the input information corresponding to the two paths merging with the maximum likelihood path are combined with the maximum likelihood / merging path. Path memory means for outputting as input information only the length of the second truncation length, wherein the likelihood information output means outputs the likelihood of decoded data corresponding to the maximum likelihood path based on the maximum likelihood / merging path input information. 10. The decoding apparatus according to claim 9, wherein the degree is updated, and likelihood information before the second cutoff length is output. 11. A branch metric calculation means for calculating a branch metric based on the convolutional code, and two branch metric units which join each transition state of the convolutional code based on the branch metric and the stored state metric. Add and compare the branch metric and the state metric for each of the paths,
Based on the comparison result, path selection information indicating the content of selecting a path with a high likelihood in each transition state of the convolutional code and a maximum likelihood transition state signal indicating the number of the transition state having the minimum state metric are output. Adding and selecting means for storing decoded data of a surviving path for each transition state based on the path selection information, and retroactively from the maximum likelihood path based on the maximum likelihood transition state signal before the censoring length. 10. The decoding apparatus according to claim 9, further comprising: a delay transition state information output unit that outputs delay transition state information indicating a number of the transition state. 12. The decoding device according to claim 7, wherein a list Viterbi decoding algorithm is applied.