JP2000341090A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital filter with a small hardware scale. SOLUTION: This digital filter is configured with a data memory 201 that stores sampling data or a filter arithmetic result, a coefficient memory 203 that stores a multiplication coefficient, a selector 204 that has a function of receiving a control signal 206 outputted from a control circuit 205, discriminates contents received from the data memory and the coefficient memory and distributingly stores them to a 12-bit register 207 or a 16-bit register 208, and a product sum arithmetic unit 203 that has two input ports with 12-bit width and 16-bit width to receive the storage contents of the 12-bit register 207 or the 16-bit register 208.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IIR used for phase compensation in digital servo processing.
Digital filter device.

[0002]

2. Description of the Related Art Conventionally, as a digital filter device, a method of performing a filter operation using a combination of a multiplier and an adder of a DSP or a product-sum operation unit is known. For example, a DSP in which the bit width of the internal memory is 16
In the case of, the multiplication process multiplies data and coefficients stored in a 16-bit width memory or register to obtain a 32-bit width product, and the addition is performed in a 32-bit width. When the result of the addition is input to the multiplier, a 16-bit rounding process is performed.

[0003]

In the above-mentioned conventional digital filter device, since the DSP is used, the input bit width of the multiplier or the product-sum operation unit is the same. However, the effective word length required for each of the two inputs of the operator, the input for the multiplication factor and the input for the data to be multiplied, is
It depends on the system using the arithmetic unit. In other words, in a product-sum operation unit such as a DSP used in the prior art, the two input bit widths are fixed and the same.
The optimum word length required for each of the input for the multiplication coefficient and the input of the data to be multiplied cannot be combined, and the DSP or the like must be selected according to the longer one of the required word lengths. Such a selection causes the system to increase in scale and cost.

[0004] The present invention has been made to solve the above-mentioned problems in the conventional digital filter device.
An object of the present invention is to provide a digital filter device having a small hardware scale.

[0005]

In order to solve the above-mentioned problems, the invention according to claim 1 comprises a storage means such as a memory for storing a multiplication coefficient and data, and a product-sum operation for the multiplication coefficient and data. In an IIR digital filter device having an operation unit for performing processing and a control unit for controlling operations of the storage unit and the operation unit, the operation unit performs a product-sum operation on multiplication coefficients and data having different word lengths. It has two types of input ports that can be executed.

By configuring the arithmetic means as described above, for example, when the arithmetic means is used for phase compensation in digital servo processing, it is only necessary to design an arithmetic means having an input having a minimum bit width required for the phase compensation. This makes it possible to reduce the scale of the multiplier or the product-sum operation unit that occupies the maximum ratio of the operation means, thereby realizing a digital filter device with a small hardware scale.

According to a second aspect of the present invention, in the digital filter device according to the first aspect, the control means includes a multiplication coefficient and a multiplication coefficient of the storage means according to a word length of the multiplication coefficient in the product-sum operation processing. Switch data,
A switching means for inputting to two types of input ports of the arithmetic means is provided.

As described above, the switching means is provided inside the control means, and two types of bits constituting the arithmetic means are provided in accordance with the word length of the multiplication coefficient in the product-sum operation processing for realizing the required filter characteristics. By switching the input to the multiplier or the product-sum operation unit having a width, it is possible to suppress the deterioration of the filter characteristic due to the reduction of the bit width of the multiplier or the product-sum operation unit.

[0009]

Next, an embodiment will be described. FIG. 1 is a conceptual diagram of a second-order IIR filter applied to the digital filter device according to the present invention. In FIG. 1, reference numerals 101 to 103 denote sampling data x (n), x of times n, n-1, and n-2 output from an 8-bit A / D converter.
(n-1), x (n-2), and 104 to 106 represent time n, n-1,
The results y (n), y (n-1) and y (n-2) of the result of executing the filter operation on the n-2 sampling data are shown. 107-111 are data x (n) 101, x (n-1) 102, x (n-
2) A multiplying element for multiplying by 103 and coefficients corresponding to the results y (n-1) 105 and y (n-2) 106, and 112 is an adding element for adding the multiplication result. The result y (n) 104 of the second-order IIR filter is:
Data x (n) 101, x (n-1) 102, x (n-2) 103, result y (n-
1) The multiplication elements 107 to 111 multiply 105 and y (n-2) 106 by the corresponding coefficients, and add all the obtained multiplication results by the addition element 112.

FIG. 2 shows a configuration example of a digital filter device for realizing this processing. In FIG. 2, 201 is a data memory for storing sampling data or a filter operation result, 202 is a coefficient memory for storing multiplication coefficients, and 203 is 12
This is a multiply-accumulate unit with bit width and 16-bit width input ports. The DSP multiplies a 16-bit coefficient by 16-bit data or an operation result, and then performs 32-bit cumulative addition.
It is common to get the result rounded to 16 bits. In the present embodiment, a product-sum operation unit 203 having two input ports of 12-bit width and 16-bit width is used as an example. In FIG. 2, reference numeral 204 denotes a 12-bit register 207 or a 16-bit register 207 which receives a control signal 206 output from the control circuit 205.
Data memory 201 and coefficient memory 202 to register 208
This is a selector that has the function of sorting the contents input from the.

Next, the operation of the digital filter device configured as described above will be described. Data memory
The data or operation result read from 201 and the coefficient read from coefficient memory 202 are input to selector 204. The selector 204 receives the control signal 206 output from the control circuit 205, determines which of the contents input to the selector 204 is 12 bits, and stores it in the 12-bit register 207. Thereafter, the remaining one is stored in the 16-bit register 208. The 12-bit register 207 is connected to the 12-bit port of the multiply-accumulate
Numeral 8 is connected to the 16-bit port of the product-sum operation unit 203, and the contents of the registers 207 and 208 are input to the connected ports, respectively, thereby performing a multiplication of 12 bits × 16 bits.

As shown in FIG. 1, the multiplication of the IIR filter operation is divided into multiplication on input data or its delay and multiplication on the delay of the operation result. In the present embodiment, input data or data corresponding to the delay thereof 101 to 10
Since 3 is the output of the 8-bit A / D converter, it is only necessary to have 8-bit precision. Therefore, when the content read from the data memory 201 is the input data or its delay, the selector 204 always inputs the content of the data memory 201 to the 12-bit side and inputs the content of the coefficient memory 202 to the 16-bit side.
On the other hand, if the content read from the data memory 201 is a delay of the calculation result, the content of the data memory 201 is directly
The contents of the coefficient memory 202 may be input to the 16-bit side, and the contents of the data memory 201 may be input to the 16-bit side, and the contents of the coefficient memory 202 may be input to the 12-bit side. It is possible. This switching may be instructed to the control circuit 205 in consideration of the characteristics of the filter as to which bit width of the delay of the operation result or the coefficient should be increased.

FIGS. 3A and 3B are timing charts showing the switching state of the selector 204. FIG. FIG.
(A) shows that the contents x (n-2), x (n-1), x (n), y (n-2) and y (n-1) of the data memory 201 are always input to the 12-bit side. The contents a2 and a of the coefficient memory 202 are always stored in the 16-bit side.
An example of inputting 1, a0, b2, and b1 is shown. FIG.
(B) shows input data and its delay data 101-103.
At the time of the first to third calculations, the contents x (n−2), x (n−1) and x (n) of the data memory 201 are input to the 12-bit side, and the coefficient memory is stored to the 16-bit side. 202 contents a2, a1,
Enter a0. In the fourth and fifth operations, which are the operations 105 to 106, the coefficient memory 20 is shifted to the 12-bit side.
2 and the contents y (n-2) and y (n-1) of the data memory 201 are input to the 16-bit side. These switching can be performed by a control signal 206 generated according to the switching instruction content of the control circuit 205.

In this embodiment, the DSP uses 16 bits 2
Instead of using an input product-sum operation unit, it is only necessary to use a product-sum operation unit having 16-bit and 12-bit input ports.
This makes it possible to reduce the scale of the product-sum operation unit that occupies the maximum ratio, and to reduce the hardware scale. Also, depending on the characteristics of the required filter, each of the multiply-accumulate units may be used, such as when the multiplication coefficients are all input to the 16-bit side or when the multiplication coefficients are input to the 12-bit side when multiplying the delay of the operation result. By switching the target to be input to the port, it is possible to suppress the deterioration of the filter characteristics due to the reduction of the bit width of the product-sum operation unit.

Note that the product-sum operation unit in the present embodiment may be replaced with a combination of a multiplier and an adder.

[0016]

As described above with reference to the embodiment, according to the first aspect of the present invention, the calculating means for performing the product-sum operation processing performs the product-sum operation on the multiplication coefficients and data having different word lengths. Since two types of input ports capable of executing arithmetic processing are provided, the scale of the multiplier or the product-sum arithmetic unit constituting the arithmetic means can be reduced, and a digital filter device with a small hardware scale can be realized. According to the second aspect of the present invention, the multiplication coefficient and the data in the storage means are switched according to the word length of the multiplication coefficient in the product-sum operation processing for realizing the required filter characteristics, and Since the switching means for inputting to the different types of input ports is provided inside the control means, it is possible to suppress the deterioration of the filter characteristic due to the reduction of the bit width of the multiplier or the product-sum operation unit constituting the calculating means. Become.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an IIR filter applied to a digital filter device according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a digital filter device according to the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG. 2;

[Explanation of symbols]

 101, 102, 103 Sampling data 104, 105, 106 Result of executing filter operation 107-111 Multiplier element 112 Adder element 201 Data memory 202 Coefficient memory 203 Product-sum operator 204 Selector 205 Control circuit 206 Control signal 207 12-bit register 208 16-bit register

Claims (2)

[Claims] 1. A storage means such as a memory for storing a multiplication coefficient and data, an operation means for performing a product-sum operation on the multiplication coefficient and data, and a control for controlling operations of the storage means and the operation means. IIR digital filter device having means, wherein said calculating means has two types of input ports capable of executing a product-sum operation on multiplication coefficients and data having different word lengths. . 2. The switching unit according to claim 1, wherein said control unit switches a multiplication coefficient and data of said storage unit in accordance with a word length of the multiplication coefficient in said product-sum operation processing, and inputs the data to two types of input ports of said calculation unit. 2. The digital filter device according to claim 1, further comprising means.