JP2000341088A - Cr-correcting constant-current circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the element area by outputting a constant current from a constant-current source circuit in a feedback loop composed of the constant- current source circuit which inputs the output voltage of a negative feedback amplifier, a saw-tooth wave generating circuit, and a peak holding circuit. SOLUTION: The output voltage of the negative feedback amplifier 36 is supplied to the constant-current circuit 37 to generate the constant current, which is supplied to the saw-tooth wave generating circuit 38. The saw-tooth wave generating circuit 38 receives a clock signal 3 and supplies charging currents IP4D and IP5D from the constant current circuits 37 to 2nd and 3rd internal capacitors 20 and 22 to generate and send two saw-tooth waves A and B to the peak holding circuit 40. The peak holding circuit 40 puts the two saw-tooth waves A and B together to feed the peak-held signal back to the inverted input terminal of the negative feedback amplifier 36, which is made to compare it with a reference voltage 2. The feedback loop controls the charging currents IP4D and IP5D so that the output voltage of the peak holding circuit 40 is as high as the reference voltage 2, thereby regarding corresponding constant currents as 1st and 2nd outputs 34 and 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CR correction constant current circuit, and more particularly to a CR correction constant current circuit for correcting variations in capacitance and resistance components gm used in a built-in filter with a current for setting gm.

[0002]

2. Description of the Related Art FIG. 7A shows a block diagram of a conventional semiconductor integrated circuit. FIG. 7B shows a reference clock (Clock IN) waveform shown in FIG. The peak hold by the peak hold (peak hold) circuit is shown.

This semiconductor integrated circuit is provided with a reference voltage Vref. 2 is input to one input terminal, a negative feedback amplifier 56, a triangular wave generator 57, and a Peak H
An old circuit 58 and a constant current source 59 are provided.

A triangular wave is formed by the built-in capacitance and the reference clock shown in FIG. 1B, and its Peak value is held.
The held Peak value is fed back to the negative feedback amplifier 56 and compared with the reference voltage Vref.

Then, the Peak Hold voltage = Vre
The constant current source 59 is a voltage stable at a voltage where the relationship of f is established.
To generate the output current, and the current is taken out of the constant current source 59 as a first output 51 and a second output 52. As a technique similar to FIG. 7, for example, Japanese Patent Laid-Open Publication No.
A CR correction circuit that takes out two outputs is disclosed.

However, in the semiconductor integrated circuit shown in FIG. 7, the constant current source is disposed outside the feedback loop, and the reference voltage Vref is constant. The second output cannot be used for CR correction as it is.

As another prior art, a CR correction constant current circuit generally used at present is shown in FIG.

As shown in FIG. 1, this circuit has two sets of CRs.
Built-in filters 63 and 67 are mounted, and one filter is a dummy filter (Dummy Fil) for CR correction.
ter) 63 and the input end (Filter I)
N) 66 and another filter 67 having an output terminal (Filter OUT) 68 are used as a filter (Filter) 67 for original signal processing.

In operation, a sine wave reference signal 62 is input to a dummy filter 63 and a phase comparator 64. The output of the phase comparator 64 is supplied to the constant current source 65, and the constant current source 65 supplies the current generated from the output of the phase comparator 64 to the dummy filter 63 and the signal processing filter 67.

At this time, the phase comparator 64 → constant current source 65 →
A feedback loop is formed by the route from the dummy filter 63 to the phase comparator 64, and the result of the phase comparison between the sine wave reference signal 62 directly input to the phase comparator 64 and the signal passed through the dummy filter 63 is 90. The current value of the constant current source 65 is controlled so as to be constant at a point where the phase shifts.

At this time, if a second-order low-pass filter is taken as an example, the cutoff frequency f _C is given by the first equation, and the phase ph is given by the second equation.
It becomes an expression.

[0012]

(Equation 1)

[0013]

(Equation 2)

In the first and second equations, C10, C
20 is the capacitance value of the capacitance of the primary filter, gm1
0 and gm20 are transconductances of the primary filters, respectively, and ω is an angular velocity.

From the first and second equations, it can be seen that both the cutoff frequency f _C and the phase ph are determined by the ratio of gm to C.

Now, in order to keep the point where the phase becomes 90 degrees constant, current control may be performed so as to obtain a value of gm such that the ratio of gm to C becomes constant. In this case, since the C and R of the dummy filter 63 and the signal processing filter 67 formed on the same semiconductor substrate vary similarly, the signal determined by the ratio of gm and C similarly to the phase ph. The processing filter 67 cutoff frequency f _C can be kept constant irrespective of variations in C and R.

[0017]

As described above, in the prior art shown in FIG. 7, since the constant current source is arranged outside the feedback loop, its output cannot be used for CR correction.

On the other hand, the prior art shown in FIG. 8 has a problem in that although the CR correction accuracy is high, the element area increases because the dummy filter 63 is required.

If there is a waveform distortion in the group delay component at the time of phase comparison, there is a possibility that correction cannot be made. Further, a sine wave composed of a single frequency component must be used as the reference signal. Has a problem with sine in the application range.

[0020]

The present invention is characterized in that a negative feedback amplifier, a constant current source circuit for inputting an output voltage of the negative feedback amplifier, and a constant current generated by the constant current source circuit are input. A sawtooth generator circuit, and a peak hold circuit (Peak) for inputting the sawtooth wave generated by the sawtooth generator circuit.
Hold circuit) and means for feeding back from the peak hold circuit to the negative feedback amplifier to form a feedback loop, and means for outputting a constant current from the constant current source circuit located in the feedback loop. It is in the CR correction constant current circuit.

Here, it is preferable that a clock signal is input to the sawtooth wave generator circuit, and the sawtooth wave is generated by the constant current and the clock signal.

Further, first and second sawtooth generators are formed in the sawtooth generator circuit, and the first and second sawtooth generators are formed.
It is preferable that the sawtooth waves generated by the sawtooth wave generators are combined by a combiner and then input to the peak hold circuit. In this case, a clock signal can be input to the first sawtooth generator, and the clock signal can be input to the second sawtooth generator via an inverter.

Further, the output can be generated by a charging current of a built-in capacitance in the constant current source circuit.

Further, the output can be supplied as a constant current of a secondary filter formed on the same semiconductor chip.

[0025]

FIG. 1 shows a CR according to an embodiment of the present invention.
2 is a circuit diagram showing a correction constant current circuit, FIG. 2 is a waveform diagram (B) showing the voltage waveform of FIG. 1, and FIG. 3 is a block diagram showing a CR correction constant current circuit according to the embodiment of the present invention.

The negative feedback amplifier 36 includes first and second P-channel field effect transistors (hereinafter, referred to as PMOS) (P1, P2) whose sources are connected to the VCC line 1.
4, 5 and the first and second PMOS (P1, P2) 4,
5, the first and second NPN bipolar transistors (hereinafter, referred to as NPN transistors) (Q1, Q2) 6, 7 each having a collector connected to the drain thereof, and the first and second NPN transistors (Q1, Q2). Resistance (R1) 8 connected to the emitters of the first and second NPs
First and second constant current sources (I1, I2) 9, 10 connected to the emitters of N transistors (Q1, Q2), respectively.
And the reference voltage Vref. Is applied to the base of the first NPN transistor (Q1) 6. 2 and a second N
The first connected to the collector of the PN transistor (Q2) 7
And a capacitance (C1) 11.

The constant current source circuit 37 includes third to seventh PMOSs (P3, P4,
P5, P6, P7) 14, 15, 16, 17, 18;
The gate is connected to the collector of the second NPN transistor (Q2) 7, and the drain is connected to the third through seventh (P3, P4, P
5, P6, P7) PMOS14,15,16,17,
A first N-channel field-effect transistor (hereinafter referred to as NMOS) (N1) 12 commonly connected to the gate 18
And a second resistor (R2) 13 provided between the source of the first NMOS (N1) 12 and the ground, and the sixth PMO pad is formed by ordinary PR technology. However, if the diameter is designed to be the same, the pad diameter D _{P with} respect to the outer diameter D _{S of the} spacer is taken into consideration even when the dispersion of both is considered.
Is within ± 0.1 mm, and this range is the most preferable range. A first constant current output 34 is taken out from the drain of S (P6) 17 and a seventh PMOS (P7)
The second constant current output 35 is extracted from the drain of the drain 18.

The sawtooth wave generator 38 includes second and third NMOs.
S (N2, N3) 19, 21 and second and third NMO
Second and third internal capacitances (C2, C3) provided between the drain of S (N2, N3) 19.21 and ground, respectively.
20 and 22, and a first inverter (INV1) 23.

Then, the drain of the second NMOS (N2) 19 is connected to the drain of the fourth PMOS (P4) 15, so that the charging current IP4D flows, and the third NMOS (N3)
The drain of the fifth PMOS (P5) 16 is connected to the drain of the fifth PMOS (P5) 16 to supply the charging current IP5D, and the reference clock signal (Clock IN) 3 from the clock end is supplied to the second N
The signal is input to the gate of the MOS (N2) 19, and the reference clock signal (Clock IN) 3 is supplied to the third NMOS (N3) 21 through the first inverter (INV1) 23.
Of the two sawtooth generators 38A, 3
8B.

The synthesizer 39 includes a second NMOS (N2) 1
The third NPN transistor (Q3) 26 has a base connected to the drain of the third NMOS (N3) 21 and a fourth NPN transistor (Q4) 27 connected to the base of the third NMOS (N3) 21. And the sawtooth waves from the two sawtooth generators are synthesized.

A Peak Hold circuit (peak hold circuit) 40 is an eighth circuit in which the source is connected to the VCC line 1.
And a ninth PMOS (P8, P9) 24, 25 and a ninth PMOS (P8, P9).
A fifth NPN transistor (Q5) 28 having a collector connected to the drain of the PMOS (P9) 25, and a fourth N
The emitter of the PN transistor (Q4) 27 and the fifth NP
A third resistor (R3) 29 connected to the emitter of the N transistor (Q5) 28; a fourth NPN transistor (Q4) 27 and a fifth NPN transistor (Q5) 2
And fourth constant current sources (I3, I4) 30, 31 respectively provided between the emitter of E.8 and ground, and a fifth NP
A drain is connected to the fourth capacitor (C4) 32 provided between the base of the N transistor (Q5) 28 and the ground, the VCC line 1, and a gate is connected to the drain of the ninth PMOS (P9) 25. Fourth N having a source connected to the base of the second NPN transistor (Q2) 7 of the negative feedback amplifier
A MOS (N4) 33 is provided.

Next, the operation will be described.

The output voltage of the negative feedback amplifier 36 is supplied to a constant current source circuit 37 to generate a constant current. This constant current is supplied to two sawtooth generators 38A and 38B of the sawtooth generator circuit 38 to generate a sawtooth wave. The two sawtooth waves are synthesized by the synthesizer 39, and the Peak Hold circuit 40 generates Peak Hol
d, and feeds back to the inverting input terminal of the negative feedback amplifier 36, so that the reference voltage Vref. Compare with 2.

In this feedback loop, Peak Hold
Voltage = Vref. The charging currents (IP4D, IP4 in FIG. 1) of the built-in capacitors (the second capacitor (C2) 20 and the third capacitor (C3) 22 in FIG. 1) are stabilized so as to stabilize at a voltage where
5D).

The first and second constant current outputs 34 and 35 output the current generated by the charging currents IP4D and IP5D.

Next, control of the charging currents IP4D and IP5D will be described.

The basic current of IP4D and IP5D is generated from the output of the negative feedback amplifier 36 and the second resistor (R2) 13.

The potential VrefA at point A and the potential VrefB at point B in FIG. 1 which are the outputs of the sawtooth wave generator 38 shown in FIG.
Are respectively the following equations (3) and (4), and Vref
The relationship between A and VrefB and the Peak Hold voltage and the reference voltage Vref of the reference power supply is expressed by the following equation (5).

[0039]

(Equation 3)

[0040]

(Equation 4)

[0041]

(Equation 5)

Here, t = １ ／ cycle of the reference clock, and C2 and C3 are the second and third capacitors (C
2, C3) are capacitance values of 20, 22.

If the value of t in this equation is given such accuracy that it can be regarded as a constant, VrefA and Vr
Since efB is equal to the reference voltage Vref of the reference voltage source 2 and is always constant, the charging currents IP4D and IP5D are equal to the second.
, And is always proportional to the capacitance values C2 and C3 of the second and third capacitances (C2 and C3) 20, 22 which are built-in capacitances.

FIG. 2 shows a reference clock signal (Cl
ock IN) waveform, VrefA waveform, VrefB
, The waveform synthesized by the synthesizer, Peak Ho
The voltage peak-held by the ld circuit is shown.

Next, an example in which the embodiment of the present invention is applied to a secondary low-pass filter will be described. FIG. 4 is a block diagram of a secondary low-pass filter formed on the same semiconductor chip as the CR correction constant current circuit shown in FIGS. 1 to 3, and FIG. 5 is a diagram showing two ports thereof. FIG. 6 is a circuit diagram showing a first-order filter of the second-order low-pass filter.

When a filter is built in an IC, A
Using the mutual conductance gm of the mp (amplifier) as an impedance component, a filter operation is performed with the built-in capacitance.

As shown in FIGS. 4 and 5, the input end (Filter IN) 46 of the filter and the output end (Filter)
er OUT) 47, a second-order low-pass filter is formed from two Amps (gm10 and gm20) and two built-in capacitors (C10 and C20), and one of these Am
p and one built-in capacitance form a first-order filter.

FIG. 6A shows a first-order filter using gm10 and C10. The same applies to the first-order filter using gm20 and C20. FIG. 6B is a circuit diagram showing a portion B in FIG. 6A in detail.

The transconductance gm10 is determined by the following sixth
It is shown by the formula.

[0050]

(Equation 6) In the sixth equation, R10 is the resistance value of the resistor R10, k
Is the Boltzmann constant, T is the absolute temperature, and q is the amount of charge of one electron. Here, IINT is a current generated from the same type of resistor as R10, and R10 × IINT is constant. The above circuit is general, and supplies a current corresponding to IEXT of each primary filter from the first output 34 of FIG. 1 and a current corresponding to IEXT of another primary filter. From the second output 35 of FIG. Specifically, as shown in FIG. 4 or FIG. 6B, NPN transistors Q30, Q40, Q50, resistors R20, R30
The first output 34 and the second output 35 of FIG. 1 are input to the input terminals of the current mirror circuit, respectively. As described above, the cutoff frequency f _C of the secondary low-pass filter is given by the first equation, and the phase ph of the filter is given by the second equation.

(Equation 1)

[0051]

(Equation 2)

Here, C10 and C20 are the capacitance values of the capacitances C10 and C20 of the primary filters, gm10 and gm, respectively.
m20 is the mutual conductance of the first order filter, and ω is the angular velocity.

As described above, both the cut-off frequency f _{C of the} filter and the phase ph of the filter are determined by the ratio of gm and C.

Built-in capacitance C1 of secondary low-pass filter
The second and third built-in capacitances (C2, C2) of FIG. 1 formed in the same semiconductor chip as the capacitance values C10, C20 of 0, C20.
C3) Since C2 and C3 of 20, 22 vary similarly,
The constant currents 34 and 35 generated by the charging currents of the second and third built-in capacitors (C2 and C3) 20 and 22 are supplied to
In the case of EXT, variations in capacitance values of the built-in capacitors C10 and C20 act so as to be offset by gm10 and gm20, and variations in the cutoff frequency f _C and phase ph due to the variations in the built-in capacitors C10 and C20 are suppressed. Thus, the same correction effect can be obtained without using a dummy filter as in the related art.

Further, since a clock signal is used as a reference signal, even if a sine wave is not generated for correction,
The set of system clocks where C is used can be substituted,
A wide range of applications can be realized.

Next, in the embodiment, the sawtooth wave generator circuit 3
8 explains why two sets of sawtooth generators 38A and 38B are provided.

Referring to the timing chart of FIG. 1B, where the sawtooth wave is generated, if the clock signal as the reference signal has one phase, the output sawtooth wave uses only a half cycle of the clock signal. Not.

In this case, the Peak Hold circuit 40
In this case, sampling is performed only once in one cycle of the reference clock, and a smoothing ability enough to withstand the sampling is required, and the value of the fourth capacitor (C4) 32 for smoothing needs to be an appropriate value.

However, as in the embodiment of the present invention, the clock signal has two phases and the first inverter (INV1) 23
, The two sawtooth outputs are also output with the phases shifted by 180 degrees.

When these two outputs are combined by the combiner 39, the Peak Hold circuit 40 outputs the reference clock 1
Two sampling opportunities are given during the period, and the same value of the fourth capacitor (C4) 32 for smoothing is obtained with half the value of the case where only one phase of the reference clock is used to obtain the same smoothing capability. be able to.

Normally, the smoothing capacity is 10 times the capacity for generating the sawtooth wave.
Since the capacitance value is required twice or more, even if two sets of sawtooth generators are provided, if the smoothing capacitance can be reduced by half, the element area can be reduced.

Although the case where the CR correction constant current circuit of the present invention is applied to a filter, particularly a secondary low-pass filter, has been described, the CR correction constant current circuit of the present invention is applied to a CR delay circuit (mono circuit) requiring a constant current. It is also possible to apply to the correction of the transmission frequency of the multi-system) or the CR transmitter and the setting of the transmission frequency.

[0063]

As described above, according to the present invention, a feedback loop of a negative feedback amplifier → constant current source circuit → sawtooth generator circuit → peak hold circuit → negative feedback amplifier is formed and located in this feedback loop. Since the correction output is output from the constant current source circuit, highly accurate correction can be performed without using a dummy filter that involves an increase in element area.

Further, since a clock signal can be used as a reference signal, in this case, a set of system clocks in which an IC is used can be substituted, and a wide range of applications can be realized.

Further, since two sets of sawtooth generators can be provided, the smoothing capacity of the Peak Hold circuit can be reduced by half in this case, and from this point of view, high integration of the IC can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a CR correction constant current circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a voltage waveform in FIG.

FIG. 3 is a block diagram showing a CR correction constant current circuit according to the embodiment of the present invention.

FIG. 4 is a block diagram of a second-order low-pass filter shown as an example to which the embodiment of the present invention is applied;

FIG. 5 is a diagram showing the second-order low-pass filter of FIG. 4 with two ports.

FIG. 6A is a circuit diagram showing a first-order filter of a secondary low-pass filter, and FIG. 6B is a detailed diagram of a portion B in FIG.

FIG. 7 is a block diagram (A) and a waveform diagram (B) showing a CR correction constant current circuit according to the related art.

FIG. 8 is a block diagram showing another conventional CR correction constant current circuit.

[Explanation of symbols]

 Reference Signs List 1 VCC 2 reference voltage 3 clock signal 4 first PMOS (P1) 5 second PMOS (P2) 6 first NPN transistor (Q1) 7 second NPN transistor (Q2) 8 first resistor (R1) Reference Signs List 9 first constant current source (I1) 10 second constant current source (I2) 11 first capacitor (C1) 12 first NMOS (N1) 13 second resistor (R2) 14 third PMOS ( P3) 15 Fourth PMOS (P4) 16 Fifth PMOS (P5) 17 Sixth PMOS (P6) 18 Seventh PMOS (P7) 19 Second NMOS (N2) 20 Second capacitance (C2) 21 third NMOS (N3) 22 third capacitor (C3) 23 first inverter (INV1) 24 eighth PMOS (P8) 25 ninth PMOS (P9) 26 third NPN transistor (Q3 27 Fourth NPN transistor (Q4) 28 Fifth NPN transistor (Q5) 29 Third resistor (R3) 30 Third constant current source (I3) 31 Fourth constant current source (I4) 32 Fourth Capacitance (C4) 33 Fourth NMOS (N4) 34 First output 35 Second output 36 Negative feedback amplifier 37 Constant current source circuit 38 Saw wave generator circuit 38A First saw wave generator 38B Second saw Wave generator 39 Synthesizer 40 Peak Hold circuit 46 Input terminal of filter 47 Output terminal of filter 51 First output 52 Second output 56 Negative feedback amplifier 57 Triangular wave generator 58 Peak Hold circuit 59 Constant current source 62 Sinusoidal wave Reference signal 63 Dummy filter 64 Phase comparator 65 Constant current source 66 Input terminal of filter 67 Filter for signal processing 68 Output of filter End

Claims (6)

[Claims] 1. A negative feedback amplifier, a constant current source circuit for inputting an output voltage of the negative feedback amplifier, a sawtooth generator circuit for inputting a constant current generated by the constant current source circuit, and the sawtooth wave A peak hold circuit for inputting the sawtooth wave generated by the generator circuit, and a feedback loop having means for feeding back from the peak hold circuit to the negative feedback amplifier,
A CR correction constant current circuit, comprising: means for outputting a constant current from the constant current source circuit located in the feedback loop. 2. The CR correction constant current circuit according to claim 1, wherein a clock signal is inputted to said sawtooth wave generator circuit, and said sawtooth wave is generated by said constant current and said clock signal. 3. A sawtooth wave generator circuit includes first and second sawtooth wave generators. The sawtooth waves generated by the first and second sawtooth generators are combined by a synthesizer. 2. The CR correction constant current circuit according to claim 1, wherein the signal is input to the peak hold circuit after being combined. 4. A CR according to claim 3, wherein a clock signal is input to said first sawtooth generator, and said clock signal is input to said second sawtooth generator via an inverter. Correction constant current circuit. 5. The CR correction constant current circuit according to claim 1, wherein said output is generated by a charging current of a built-in capacitance in said constant current source circuit. 6. The CR correction constant current circuit according to claim 1, wherein said output is supplied as a constant current of a secondary filter formed on the same semiconductor chip.