JP2000340657A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cut a fuse with high accuracy and lessen the area of a pattern for positioning in trimming that it occupies in a scribe line region, in an IC where the fuse is trimmed with a laser. SOLUTION: Occupancy area is reduced by making patterns for positioning for laser trimming in the existing pad regions 202 within a semiconductor integrated circuit chip 201 and arranging them at the intersecting points between scribe lines, and putting them in such a continuous structure that they combines the function of the so-called sheeter marks for performing the relatively rough positioning with respect to the rotational direction of a semiconductor wafer, and the function of trimming marks for performing accurate positioning to the several semiconductor integrated circuits which are arranged repeatedly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device provided with a positioning pattern for cutting a fuse element formed on a semiconductor chip surface with high accuracy by laser beam irradiation.

[0002]

2. Description of the Related Art In an apparatus for an analog semiconductor integrated circuit, a laser trimming method for adjusting analog characteristics is known. For example, it is described in JP-A-5-13670. After two-dimensionally patterning an integrated circuit on a semiconductor wafer, electrical characteristics of each integrated circuit are measured in a wafer state. Next, for adjustment of analog characteristics, a fuse element provided on a part of the wiring is selected and cut by laser beam irradiation. With such a laser trimming method, the analog characteristics of the integrated circuit can be adjusted to desired characteristics by selecting the fuse element to be cut. In order to irradiate a predetermined fuse element with a laser beam, a positioning pattern is provided on the surface of the semiconductor wafer.

FIG. 3A is a plan view of a conventional positioning pattern, FIG. 3B is a cross-sectional view of the conventional positioning pattern, and FIG. It is a figure which shows the light reflection amount change at the time of scanning along the -C 'line direction. The conventional positioning pattern is shown in FIG.
As shown in FIG. 3A, a so-called theta mark 301 provided on the scribe line area 203 for performing a relatively rough alignment with respect to the rotation direction of the semiconductor wafer.
And an X-direction trimming mark 302 and a Y-direction trimming mark 3 for accurately aligning each of the semiconductor integrated circuit chips 201 arranged repeatedly.
03. It is desired that the shape of the theta mark 301 has a characteristic shape different from the pad region 202 or the like in the semiconductor integrated circuit chip 201 so that image recognition can be performed automatically.

In the example of FIG. 3A, a key-shaped shape is shown. However, any other shape may be used as long as it is a unique shape and easy to recognize. Next, as shown in FIG. 3B, the conventional positioning pattern is such that a rectangular aluminum film 105 is disposed on a first insulating film 102 made of a silicon oxide film provided on a silicon substrate 101. . C in FIG.
When the light beam is scanned along the −C ′ line direction, a light reflection pattern as shown in FIG. 3C is obtained because the reflectance of the aluminum film 105 is high. A high light reflection amount is shown on the aluminum film 105, and a low light reflection amount is obtained in a portion where the aluminum film 105 is not provided. By using a portion where the light reflection amount between the high light reflection amount and the low light reflection amount changes, a reference position used for trimming is grasped. The positional relationship between the positioning pattern and the fuse element made of the polycrystalline silicon film of the integrated circuit is determined at the time of design.
Therefore, by irradiating the positioning pattern with a light beam and detecting the position where the amount of light reflection changes, the coordinates of the desired fuse element are calculated, and by irradiating the laser with that position, the fuse element is selectively exposed. Can be trimmed.

[0005]

However, in conventional laser trimming, accurate positioning could not be performed because the fuse element and the positioning pattern were formed of different thin films. When a reference position is detected by a positioning pattern that is an aluminum pattern and a polycrystalline silicon thin film that is a fuse element is laser-trimmed, an aluminum pattern generated during a semiconductor process and an element formed of a polycrystalline silicon thin film are used. 14, the laser irradiation region 32 is displaced from the fuse element 31 as shown in FIG. Since the energy distribution of the laser irradiation region 32 is a Gaussian distribution, the energy intensity at the laser irradiation end is low. Therefore, in the wafer process, if there is a large misalignment between the patterning of the polycrystalline silicon film and the patterning of the aluminum film, there is a problem that the fuse element cannot be stably cut. In addition, 3
Numeral 3 denotes a base kogation, and numeral 34 denotes a portion where the fuse cut remains.

Conventionally, a laser trimming positioning pattern is often arranged in a scribe line area between semiconductor integrated circuit chips. However, the scribe line area is provided with a margin used for scribing (cutting) a semiconductor wafer. If a large number of films are present in this area, the blade of the dicing cutter will be damaged during the dicing process, and the throughput of the dicing process will be reduced. In extreme cases, dicing cannot be performed well. There is a problem that the semiconductor integrated circuit chip is damaged.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of accurately positioning and trimming a fuse element of a semiconductor chip.
In particular, an IC fabricated on an SOI substrate, which has recently attracted attention
The present invention provides a semiconductor device that can be applied to a semiconductor device. further,
An object of the present invention is to reduce the size and cost of a fuse element region by increasing the positioning accuracy of trimming.

A semiconductor device which does not hinder the dicing process by reducing the area of the laser trimming positioning pattern occupying the scribe line area or incorporating the laser trimming positioning pattern into a semiconductor integrated circuit chip. It is to provide.

[0009]

In order to solve the above problems, the present invention takes the following measures. (1) A semiconductor integrated circuit repeatedly arranged in a two-dimensional matrix on a surface of a semiconductor wafer via scribe lines, a fuse element for laser trimming provided on the semiconductor integrated circuit, and a semiconductor integrated circuit provided on the surface of the semiconductor wafer. And a laser trimming positioning pattern, wherein the laser trimming positioning pattern is formed of the same thin film as the laser trimming fuse element. (2) The semiconductor device according to (1), wherein the laser trimming positioning pattern includes a high light reflectance region and a low light reflectance region surrounded by a high light refraction region. Alternatively, on the contrary, the semiconductor device described in (1) includes a low light reflectance region and a high light reflectance region surrounded by the low light reflectance region. (3) The semiconductor device according to (2), wherein the low light reflectance region is a dot, lattice, or stripe pattern for diffusely reflecting light. (4) The semiconductor device according to (2), wherein the laser trimming fuse element is formed of a polycrystalline silicon thin film. (5) A semiconductor integrated circuit repeatedly arranged in a two-dimensional matrix on a surface of a semiconductor wafer via scribe lines, a fuse element for laser trimming provided on the semiconductor integrated circuit, and a semiconductor integrated circuit provided on the surface of the semiconductor wafer. A laser trimming positioning pattern, the laser trimming positioning pattern is composed of a high light reflectance region and a low light reflectance region, and the high light reflectance region is formed of a high light reflectance formed on a flat base. The low light reflectivity region is formed by a high light reflectivity film formed on a lattice or stripe or dot pattern for irregularly reflecting light, which is formed of the same thin film as the fuse element for laser trimming. Semiconductor device. (6) The semiconductor device described in (5), wherein the laser trimming positioning pattern includes a high light reflectance region and a low light reflectance region surrounded by the high light reflectance region. (7) The semiconductor device described in (5), wherein the laser trimming positioning pattern includes a low light reflectivity region and a high light reflectivity region surrounded by the low light reflectivity region. (8) The semiconductor device according to (5), wherein the fuse element for laser trimming is made of a polycrystalline silicon thin film. (9) The semiconductor device according to (5), wherein the high light reflectance film is made of aluminum. (10) The semiconductor device according to (5), wherein the laser trimming positioning pattern is arranged in a pad area for making an electrical connection with the outside in the semiconductor integrated circuit chip. (11) The laser trimming positioning pattern includes a high light reflectance region and a low light reflectance region, and the high light reflectance region is formed by a high light reflectance film formed on a flat base, and the low light reflectance region. The semiconductor device according to (10), which is formed by a high light reflectivity film formed on a lattice or stripe or dot-like pattern for irregularly reflecting light which is constituted by the same thin film as the fuse element for laser trimming. did. (12) The semiconductor device according to (11), wherein the laser trimming positioning pattern includes a high light reflectance region and a low light reflectance region surrounded by the high light reflectance region. (13) The semiconductor device according to (11), wherein the laser trimming positioning pattern includes a low light reflectance region and a high light reflectance region surrounded by the low light reflectance region. (14) The semiconductor device according to (11), wherein the laser trimming fuse element is made of a polycrystalline silicon thin film. (15) The semiconductor device according to (11), wherein the high light reflectance film is made of aluminum. (16) The semiconductor device according to (5), wherein the laser trimming positioning pattern is arranged at the intersection of the scribe lines. (17) The laser trimming positioning pattern performs a so-called theta mark for relatively coarse positioning in the rotational direction of the semiconductor wafer, and performs accurate positioning for each of the repeatedly arranged semiconductor integrated circuits. The semiconductor device according to (5), which has a continuous structure that can also serve as a trimming mark. (18) In order to increase the difference (contrast) in the amount of light reflection between the high light reflectance region and the low light reflectance region, a semiconductor device in which the size inside the laser trimming positioning pattern is defined using the laser beam diameter as an index is used. . (19) In particular, in the case of an IC manufactured on an SOI substrate, the semiconductor device according to (2), wherein the fuse element for laser trimming is formed of a single crystal silicon device forming layer. (20) In particular, in the case of an IC manufactured on an SOI substrate, the semiconductor device according to (5), wherein the fuse element for laser trimming is formed of a single crystal silicon device forming layer.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A laser trimming positioning pattern comprises a high light reflectance region and a low light reflectance region, and the boundary between the high light reflectance region and the low light reflectance region, that is, the light reflectance changes sharply. The location is defined by a pattern formed by the same thin film as the fuse element for laser trimming. Thus, laser trimming can be performed accurately without being affected by misalignment in the wafer process.

The laser trimming positioning pattern may be moved from the scribe line area to a pad area for making an electrical connection with the outside of the semiconductor integrated circuit chip, or may be formed in the scribe line area. , A so-called theta mark for relatively coarse alignment with respect to the rotation direction of the semiconductor wafer, and a trimming mark for accurate alignment for each of the repeatedly arranged semiconductor integrated circuits. By arranging it as a possible continuous structure at the intersection of the scribe lines, the area of the laser trimming positioning pattern occupying the scribe line area can be reduced.

Further, the dimension of the laser trimming positioning pattern is defined using the laser beam diameter as an index so that the reflectance between the high light reflectance region and the low light reflectance region has a large difference (increases contrast). Thus, it is possible to obtain a structure capable of sufficiently exhibiting the ability of the laser trimming positioning pattern.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. Although the following description is omitted for simplicity, the fuse element for laser trimming is assumed to be formed of a polycrystalline silicon thin film unless otherwise specified.

FIG. 1A is a plan view of a positioning pattern according to the present invention, and FIG. 1B is a diagram showing a change in the amount of light reflection when a light beam is scanned. The light reflection amount is a value when scanning is performed along the AA ′ direction in FIG. As shown in FIG. 1A, the positioning pattern of the present invention includes a high light reflectance area 106 and a low light reflectance area 107 inside the high light reflectance area 106. In the example of FIG. 1A, the low light reflectance region 107 is formed by utilizing the irregular reflection of light. In order to cause irregular reflection, a polycrystalline silicon thin film 103 which is the same thin film as the fuse element was formed in a dot shape. In order to cause irregular reflection, a pattern such as a lattice shape or a stripe shape may be used instead of the dot shape.
Is obtained. As the fuse element, a film that easily absorbs light and is easily cut is preferable. Also,
In order to form an integrated circuit, it is necessary to use a conductive film. A preferred film is a polycrystalline silicon film. The polycrystalline silicon film absorbs light easily and can be easily cut by laser irradiation. By forming the polycrystalline silicon thin film 103 as a dot-shaped pattern as shown in FIG. 1A and making the inside of the positioning pattern a low light reflectance area 107, it is possible to obtain a large contrast of the light reflection amount. . The high light reflectivity region 106 can be formed of a field region made of an oxide film or the like provided on a semiconductor substrate, as in the related art.

FIG. 2A is a plan view of a positioning pattern according to a second embodiment of the present invention, and FIG. 2B is a diagram showing a change in the amount of light reflection when a light beam is scanned. . The light reflection amount is a value when scanning is performed along the CC ′ direction in FIG. The positioning pattern of the present invention is shown in FIG.
As shown in FIG. 1, the low-reflectance region 107 and the high-reflectance region 106 inside the low-reflection region 107 have the reverse configuration of the example shown in FIG. As the laser trimming positioning pattern, either the low light reflectivity region 107 or the high light reflectivity region 106 may have a shape sandwiching the partner in a plane, so that the configuration shown in FIG. Become. The description of the other points is omitted by attaching the same reference numerals as those in FIG.

Although not particularly shown, in the embodiment of the present invention shown in FIGS. 1 and 2, the silicon nitride film and the NSG
A silicon oxide film such as a film, a PSG film, or a BPSG film, or a light-transmitting insulating film such as a polyimide film is disposed on the uppermost layer to increase the irregular reflection of light in the low light reflectance region 107. The contrast of the light reflection amount between the high light reflectance region 106 and the low light reflectance region 107 may be increased so that a low light reflectance is obtained.

In particular, when an IC is manufactured on an SOI substrate, a polycrystalline silicon thin film 103 described in FIGS. 1 and 2 is formed on a buried oxide film of the SOI substrate to form a single crystal silicon device. What is necessary is just to replace it with a layer. In this case, the fuse element is also formed of a single crystal silicon device forming layer, and the laser trimming positioning pattern is formed of the same thin film as the laser trimming fuse element.

FIG. 4A shows a third example of the semiconductor device according to the present invention.
FIG. 4 is a plan view of a positioning pattern according to the embodiment of FIG.
FIG. 4B is a sectional view of a positioning pattern according to a third embodiment of the semiconductor device of the present invention. FIG. 4C is a diagram showing a light beam applied to the positioning pattern according to the third embodiment of the semiconductor device of the present invention. FIG. 6 is a diagram illustrating a change in the amount of light reflection when scanning is performed.
The light reflection amount is a value when scanning is performed along the line AA ′ in FIG. As shown in FIG. 4B, the positioning pattern according to the third embodiment of the present invention includes a high light reflectivity area 106 and a low light reflectivity area 107 inside the high light reflectivity area.

Referring to FIGS. 4A and 4B, the structure of the positioning pattern of the present invention will be described. Silicon substrate 1
01, a first insulating film 102 made of a silicon oxide film or the like
Is formed, and a polycrystalline silicon thin film 103 in a partially dot shape is formed on the first insulating film 102. In a region where the polycrystalline silicon thin film 103 is not formed, the flat first insulating film 102 is exposed. On top of this, PSG
A second insulating film 104 made of a film or the like is formed, and an aluminum film 105 is formed on the second insulating film 104. Aluminum film 105 located above the region where dot-shaped polycrystalline silicon thin film 103 is formed
Is uneven due to the effect of the pattern of the polycrystalline silicon thin film 103, and the light applied to this portion is irregularly reflected. Therefore, this region can be used as the low light reflectance region 107. On the other hand, the aluminum film 10 on the region where the polycrystalline silicon thin film 103 is not formed
The surface of No. 5 is flat and can be a high light reflectance area 106.

When the light beam is scanned along the line AA 'in FIG. 4A, the amount of light reflection is, as shown in FIG. 4C, formed by the aluminum film 105 having a flat surface. It is large in the high light reflectivity region 106 to be formed, and small in the low light reflectivity region 107 formed by the aluminum film 105 having the uneven surface. FIG. 4 (a), (b)
In the examples of (c) and (c), the low light reflectance region 107 is formed by utilizing the irregular reflection of light. In order to cause irregular reflection of light, a dot-shaped pattern was formed by the polycrystalline silicon thin film 103 which is the same thin film as the fuse element. Diffuse reflection of light can be caused even in a pattern other than a dot, such as a lattice or a stripe, and a light reflection pattern as shown in FIG. 4C is obtained.

Since the first insulating film 102 and the second insulating film 104 in FIG. 4B are not always necessary, they may be omitted in some cases. The aluminum film 10
Instead of 5, a metal material such as tungsten, chromium, or gold may be used as the high light reflectance film. Although not shown, a silicon oxide film such as a silicon nitride film, an NSG film, a PSG film, or a BPSG film, or a light-transmitting insulating film such as a polyimide film is disposed on the aluminum film 105 in FIG. 4B. Then, by increasing the irregular reflection of light in the low light reflectance region 107, a lower light reflectance can be obtained, and the amount of light reflection between the high light reflectance region 106 and the low light reflectance region 107 is reduced. It is also good to increase the contrast.

As described above, the high light reflectance region 106
Is determined by the pattern of the polycrystalline silicon thin film 103, which is the same thin film material as the fuse element, so that the polycrystalline silicon forming the fuse element has been a problem of the conventional positioning pattern. With silicon,
The problem caused by misalignment with the aluminum film forming the positioning pattern can be relieved.

FIG. 5A shows a fourth example of the semiconductor device according to the present invention.
FIG. 5 is a plan view of a positioning pattern according to the embodiment of FIG.
FIG. 5B is a cross-sectional view of a positioning pattern according to a fourth embodiment of the semiconductor device of the present invention. FIG. 5C is a diagram showing a light beam applied to the positioning pattern according to the fourth embodiment of the semiconductor device of the present invention. FIG. 6 is a diagram illustrating a change in the amount of light reflection when scanning is performed.
The light reflection amount is a value when scanning is performed in the direction of the line CC ′ in FIG. As in the third embodiment shown in FIGS. 3A to 3C, the positioning pattern of the fourth embodiment of the present invention includes a high light reflectance area 106 and a low light reflectance area 107 inside the high light reflectance area 106. It is composed of

The difference from the third embodiment shown in FIG.
Polycrystalline silicon thin film 10 with high light reflectance region 106 flat
3 is formed by the aluminum film 105 located above the metal film 3. If the high light reflectivity region 106 is formed of a high light reflectivity film on a flat base, it can fulfill its role, and such a configuration is also possible.
The other description will be replaced by the same reference numerals as in FIGS. 4A to 4C.

FIG. 6A shows a fifth example of the semiconductor device of the present invention.
FIG. 6 is a plan view of a positioning pattern according to the embodiment of FIG.
FIG. 6B is a cross-sectional view of a positioning pattern according to a fifth embodiment of the semiconductor device of the present invention. FIG. 6C is a diagram showing a light beam applied to the positioning pattern according to the fifth embodiment of the semiconductor device of the present invention. FIG. 6 is a diagram illustrating a change in the amount of light reflection when scanning is performed.
The light reflection amount is a value when scanning is performed along the line DD ′ in FIG. 6A. The positioning pattern according to the fifth embodiment of the present invention has a configuration in which a low light reflectance area 107 is arranged outside and a high light reflectance area 106 is arranged inside.
As the positioning pattern, it is sufficient that one of the high light reflectance region 106 and the low light reflectance region 107 is sandwiched between the other regions, as shown in FIGS. 6 (a) to 6 (c). The fifth embodiment shows a case where the arrangement is opposite to that of the third embodiment shown in FIGS. 4A to 4C, and shows that such a configuration may be adopted. is there. The other description will be replaced by the same reference numerals as in FIGS. 4A to 4C.

FIG. 7A shows a sixth example of the semiconductor device of the present invention.
FIG. 7 is a plan view of a positioning pattern according to the embodiment of FIG.
FIG. 7B is a sectional view of a positioning pattern according to a sixth embodiment of the semiconductor device of the present invention, and FIG. 7C is a diagram showing a light beam applied to the positioning pattern according to the sixth embodiment of the semiconductor device of the present invention. FIG. 6 is a diagram illustrating a change in the amount of light reflection when scanning is performed.
The light reflection amount is a value when scanning is performed along the EE ′ line direction in FIG. The positioning pattern according to the sixth embodiment of the present invention has a configuration in which a low light reflectance area 107 is arranged on the outside and a high light reflectance area 106 is arranged on the inside.

As in the description of the fifth embodiment, the positioning pattern may be such that one of the high light reflectance region 106 and the low light reflectance region 107 is sandwiched between the other regions. The sixth embodiment shown in FIGS. 7A to 7C shows a case where the arrangement is opposite to that of the fourth embodiment shown in FIGS. 5A to 5C. is there. The other description will be replaced by the same reference numerals as in FIGS. 4A to 4C.

First insulating film 102 in FIGS. 4 to 7
And the second insulating film 104 is not always necessary,
It may be deleted in some cases. Further, instead of the aluminum film 105, a metal material such as tungsten, chromium, or gold may be used as the high light reflectance film. Although not particularly shown, a light-transmitting insulating film such as a silicon oxide film such as a silicon nitride film, an NSG film, a PSG film, or a BPSG film, or a polyimide film is disposed on the aluminum film 105 so as to have low light reflection. By increasing the irregular reflection of light in the high-reflectance region 107, a lower light reflectance can be obtained, and the contrast of the light reflection amount between the high-light reflectance region 106 and the low-light reflectance region 107 can be increased. good.

In particular, when an IC is manufactured on an SOI substrate, a polycrystalline silicon thin film 103 described with reference to FIGS. 4 to 7 is formed on a single crystal silicon device formed on a buried oxide film of the SOI substrate. The first insulating film 102 may be replaced with a buried oxide film of an SOI substrate. In this case, the fuse element is also formed of a single crystal silicon device forming layer, and the laser trimming positioning pattern is formed of the same thin film as the laser trimming fuse element.

FIG. 8A is a schematic plan view of a semiconductor integrated circuit chip having a positioning pattern according to the seventh to tenth embodiments of the semiconductor device of the present invention. FIG. 8B is an enlarged schematic plan view of a pad region where the laser trimming positioning pattern of FIG. 8A is arranged. FIG.
As shown in FIG. 1A, a pad region 202 made of a conductive thin film of aluminum or the like for making an electrical connection to the outside is arranged in a semiconductor integrated circuit chip 201. The adjacent semiconductor integrated circuit chip 20
A scribe line area 203 is arranged between the two.

Here, the laser trimming positioning pattern according to the present invention is formed inside the pad area 202. FIG. 8B shows a pad area 202 containing a laser trimming positioning pattern 204 according to the present invention.
FIG. In FIG. 8B, the pad region 2
A part of 02 is a laser trimming positioning pattern area 204.

Originally, the pad area 202 is an area necessary for electrical connection with the outside. Since the pattern area 204 for laser trimming positioning is formed inside the pad area 202, the area of the semiconductor integrated circuit chip 201 is reduced. The laser trimming positioning pattern 204 can be taken into the semiconductor integrated circuit chip without increasing.

FIGS. 8A and 8B show a laser trimming positioning pattern 204 in one pad area 202.
Is shown, but a plurality of laser trimming positioning patterns 204 may be formed in one pad area 202 as needed, or a laser trimming positioning pattern 204 may be formed in a plurality of pad areas 202. The patterns 204 may be formed one by one or a plurality of them.

Next, the laser trimming positioning pattern according to the present invention will be described in more detail with reference to FIGS. FIG. 9A is a plan view of a laser trimming positioning pattern according to a seventh embodiment of the semiconductor device of the present invention, and FIG. 9B is a laser trimming positioning according to a seventh embodiment of the semiconductor device of the present invention. FIG. 9C is a diagram showing a change in the amount of light reflection when a light beam is scanned on the laser trimming positioning pattern according to the seventh embodiment of the semiconductor device of the present invention. The light reflection amount is a value when scanning is performed along the line AA ′ in FIG. 9A. As shown in FIG. 9B, the laser trimming positioning pattern according to the seventh embodiment of the present invention includes a high light reflectance area 106 and a low light reflectance area 107 inside the high light reflectance area 106.

The structure of the laser trimming positioning pattern according to the present invention will be described with reference to FIGS. 9A and 9B. A first insulating film 102 made of a silicon oxide film or the like is formed on a silicon substrate 101, and a partially dot-shaped polycrystalline silicon thin film 1 is formed on the first insulating film 102.
03 is formed. In a region where the polycrystalline silicon thin film 103 is not formed, the flat first insulating film 102 is exposed. On top of this, a second insulating film 104 made of a PSG film or the like
Is formed, and an aluminum film 105 is formed on the second insulating film 104. The surface of the aluminum film 105 located above the region where the dot-shaped polycrystalline silicon thin film 103 is formed is the polycrystalline silicon thin film 1
Due to the effect of the pattern No. 03, the surface is uneven, and the light applied to this portion is irregularly reflected. Therefore, this region can be used as the low light reflectance region 107. On the other hand, the surface of the aluminum film 105 on the region where the polycrystalline silicon thin film 103 is not formed is flat and can be a high light reflectance region 106.

When the light beam is scanned in the direction of the line AA 'in FIG. 9A, the amount of light reflection is, as shown in FIG. 9C, formed by the aluminum film 105 having a flat surface. It is large in the high light reflectivity region 106 to be formed, and small in the low light reflectivity region 107 formed by the aluminum film 105 having the uneven surface. FIG. 9 (a), (b)
In the examples of (c) and (c), the low light reflectance region 107 is formed by utilizing the irregular reflection of light. In order to cause irregular reflection of light, a dot-shaped pattern was formed by the polycrystalline silicon thin film 103 which is the same thin film as the fuse element. Diffuse reflection of light can be caused even in a pattern other than a dot, such as a grid or a stripe, and a light reflection pattern as shown in FIG. 3C is obtained.

Since either one of the first insulating film 102 and the second insulating film 104 in FIG. 9B is not always necessary, it may be omitted in some cases. In the case where the laser trimming positioning pattern 204 is arranged in the pad region 202 which may have the same potential as the silicon substrate 101, both the first insulating film 102 and the second insulating film 104 are omitted, and the aluminum film 105 and silicon substrate 1
01 may be electrically connected. Also,
Instead of the aluminum film 105, a metal material such as tungsten, chromium, or gold may be used as the high light reflectance film as long as it meets the purpose of electrical connection with the outside.

As described above, the high light reflectance region 106
Is determined by the pattern of the polycrystalline silicon thin film 103, which is the same thin film material as the fuse element, so that the formation of the fuse element, which has been a problem of the conventional laser trimming positioning pattern, is performed. From the misalignment between the polycrystalline silicon to be formed and the aluminum film forming the laser trimming positioning pattern.

FIG. 10 (a) is a plan view of a laser trimming positioning pattern according to an eighth embodiment of the semiconductor device of the present invention, and FIG. 10 (b) is a plan view of the eighth embodiment of the semiconductor device of the present invention. FIG. 10C is a sectional view of a pattern for laser trimming positioning, and FIG.
FIG. 8 is a diagram showing a change in the amount of light reflection when a light beam is scanned on the laser trimming positioning pattern according to the example of FIG. The light reflection amount is a value when scanning is performed in the direction of the line CC ′ in FIG. The laser trimming positioning pattern according to the eighth embodiment of the present invention is shown in FIG.
As in the case of the seventh embodiment shown in FIG.
06, and a low light reflectance area 107 inside thereof.

The difference from the seventh embodiment is that the high light reflectance region 106 is formed by the aluminum film 105 located above the flat polycrystalline silicon thin film 103. If the high light reflectivity region 106 is formed of a high light reflectivity film on a flat base, it can fulfill its role, and such a configuration is also possible. The other description is replaced by the same reference numerals as in FIGS. 9A to 9C.

FIG. 11A is a plan view of a laser trimming positioning pattern according to a ninth embodiment of the semiconductor device of the present invention, and FIG. 11B is a plan view of the ninth embodiment of the semiconductor device of the present invention. FIG. 11C is a sectional view of a laser trimming positioning pattern, and FIG.
FIG. 8 is a diagram showing a change in the amount of light reflection when a light beam is scanned on the laser trimming positioning pattern according to the example of FIG. The light reflection amount is a value when scanning is performed along the line DD ′ in FIG. 11A. The positioning pattern according to the ninth embodiment of the present invention has a configuration in which a low light reflectance region 107 is disposed outside and a high light reflectance region 106 is disposed inside. As a laser trimming positioning pattern, it is sufficient that one of the high light reflectance region 106 and the low light reflectance region 107 is sandwiched between the other regions, as shown in FIGS. 11 (a) to 11 (c). The ninth embodiment shown in FIG. 9 shows a case where the arrangement is opposite to that of the seventh embodiment shown in FIGS. 9A to 9C, and shows that such a configuration may be adopted. Things. The other description is replaced by the same reference numerals as in FIGS. 3A to 3C.

FIG. 12A is a plan view of a laser trimming positioning pattern according to a tenth embodiment of the semiconductor device of the present invention, and FIG. 12B is a plan view of the semiconductor device of the tenth embodiment of the present invention. FIG. 12C is a cross-sectional view of a laser trimming positioning pattern, and FIG. 12C is a diagram showing a change in the amount of light reflection when a light beam is scanned on the laser trimming positioning pattern according to the tenth embodiment of the semiconductor device of the present invention. is there. The light reflection amount is a value when scanning is performed along the EE ′ line direction in FIG. The laser trimming positioning pattern according to the tenth embodiment of the present invention has a configuration in which a low light reflectance area 107 is arranged outside and a high light reflectance area 106 is arranged inside.

As in the description of the eighth embodiment, the laser trimming positioning pattern has a shape in which one of the high light reflectance area 106 and the low light reflectance area 107 is sandwiched between the other areas. Figure 12
The tenth embodiment shown in FIGS. 10A to 10C shows a case where the arrangement is opposite to that of the eighth embodiment shown in FIGS. 10A to 10C. The other description is replaced by the same reference numerals as in FIGS. 9A to 9C.

In particular, when an IC is manufactured on an SOI substrate, a polycrystalline silicon thin film 103 described with reference to FIGS. 9 to 12 is formed on a single crystal silicon device formed on a buried oxide film of the SOI substrate. The first insulating film 102 may be replaced with a buried oxide film of an SOI substrate. In this case, the fuse element is also formed of a single crystal silicon device forming layer, and the laser trimming positioning pattern is formed of the same thin film as the laser trimming fuse element.

FIG. 13A is a plan view of a positioning pattern according to an eleventh embodiment of the semiconductor device of the present invention.
FIG. 3B is a sectional view of a positioning pattern according to an eleventh embodiment of the semiconductor device of the present invention, and FIG. 13C is a light beam on the positioning pattern according to the eleventh embodiment of the semiconductor device of the present invention. FIG. 7 is a diagram showing a change in the amount of light reflection when scanning is performed. The light reflection amount is a value when scanning is performed along the line AA ′ in FIG. Laser trimming positioning pattern 401 according to Embodiment 11 of the present invention
As shown in FIG. 1 (a), the so-called theta mark function is provided at the intersection of the vertical and horizontal scribe line areas 203 to perform relatively rough alignment in the rotation direction of the semiconductor wafer. And an X-direction trimming mark and Y for performing accurate alignment for each of the semiconductor integrated circuit chips 201 repeatedly arranged.
It has a continuous structure that also has the function of a direction trimming mark. Laser trimming positioning pattern 4
01 has a pad area 202 in the semiconductor integrated circuit chip 201 so that image recognition can be performed automatically.
Since it is desired that the shape is different from that of FIG.
In the example of FIG. 3A, the shape is a cross shape.

Next, an eleventh embodiment of the present invention will be described with reference to FIG.
Laser trimming positioning pattern 40 according to embodiment
1 is described. A first insulating film 102 made of a silicon oxide film or the like is formed on a silicon substrate 101, and a dot-like polycrystalline silicon thin film 103 is formed partially on the first insulating film 102. In a region where the polycrystalline silicon thin film 103 is not formed, the flat first insulating film 102 is exposed. On top of this, an aluminum film 10
5 are formed. The surface of the aluminum film 105 located above the region where the dot-shaped polycrystalline silicon thin film 103 is formed is uneven due to the effect of the pattern of the polycrystalline silicon thin film 103. Will diffusely reflect. Therefore, this region can be used as the low light reflectance region 107. On the other hand, the surface of the aluminum film 105 on the region where the polycrystalline silicon thin film 103 is not formed is flat, and the high light reflectance region 1
06.

When the light beam is scanned in the direction of the line AA 'in FIG. 13A, the amount of light reflection is, as shown in FIG. 13C, formed by the aluminum film 105 having a flat surface. It is large in the high light reflectivity region 106 to be formed, and small in the low light reflectivity region 107 formed by the aluminum film 105 having the uneven surface. FIG. 13 (a),
In the examples of (b) and (c), the low light reflectance region 107 was formed by utilizing the diffuse reflection of light. In order to cause irregular reflection of light, a dot-shaped pattern was formed by the polycrystalline silicon thin film 103 which is the same thin film as the fuse element.
It is possible to cause irregular reflection of light even in a pattern other than a dot, such as a lattice or a stripe.
A light reflection pattern as shown in (c) is obtained.

In some cases, a second insulating film or the like may be formed on the first insulating film 102 or the polycrystalline silicon thin film 103 in FIG. Aluminum film 1
Instead of 05, a metal material such as tungsten, chromium, or gold may be used as the high light reflectance film. Although not shown, a silicon oxide film such as a silicon nitride film, an NSG film, a PSG film, or a BPSG film, or a light-transmitting insulating film such as a polyimide film is disposed on the aluminum film 105 in FIG. Then, by increasing the irregular reflection of light in the low light reflectance region 107, a lower light reflectance can be obtained, and the amount of light reflection between the high light reflectance region 106 and the low light reflectance region 107 is reduced. It is also good to increase the contrast.

In particular, when an IC is manufactured on an SOI substrate, the polycrystalline silicon thin film 103 described with reference to FIGS. 4 to 7 is formed on a single crystal silicon device formed on a buried oxide film of the SOI substrate. The first insulating film 102 may be replaced with a buried oxide film of an SOI substrate. In this case, the fuse element is also formed of a single crystal silicon device forming layer, and the laser trimming positioning pattern is formed of the same thin film as the laser trimming fuse element.

As described above, the high light reflectance region 106
Is determined by the pattern of the polycrystalline silicon thin film 103, which is the same thin film material as the fuse element, so that the polycrystalline silicon forming the fuse element has been a problem of the conventional positioning pattern. With silicon,
The problem caused by misalignment with the aluminum film forming the positioning pattern can be relieved.

The laser trimming positioning pattern 401 is arranged at the intersection of the scribe line area 203, and has a so-called theta mark function for performing relatively rough alignment with respect to the rotation direction of the semiconductor wafer. A laser trimming positioning pattern occupying the scribe line area 203 because it has a continuous structure that can also serve as a trimming mark function for accurate X and Y alignment of each integrated circuit chip 201. Can be reduced in area.

FIG. 15A is a plan view of a positioning pattern according to a twelfth embodiment of the semiconductor device of the present invention.
FIG. 5B is a sectional view of a positioning pattern according to a twelfth embodiment of the semiconductor device of the present invention, and FIG. 15C is a light beam on the positioning pattern according to the twelfth embodiment of the semiconductor device of the present invention. FIG. 7 is a diagram showing a change in the amount of light reflection when scanning is performed. The light reflection amount is a value when scanning is performed in the direction of the line BB ′ in FIG.

The laser trimming positioning pattern 401 in the twelfth embodiment of the present invention is arranged at the intersection of the scribe line area 203 as in the eleventh embodiment shown in FIGS. 13 (a) to 13 (c). ing. The difference from the eleventh embodiment is that the high light reflectivity region 106 is interposed between the low reflectivity regions 107, and the shape of the laser trimming positioning pattern 401 is the eleventh embodiment shown in FIG. The embodiment is different from the cross shape in that it is a key shape.

The laser trimming positioning pattern includes a high light reflectance area 106 and a low light reflectance area 107.
15A to 15C may be adopted as long as one of them is sandwiched between the other regions. The twelfth embodiment shown in FIGS. This shows a case where the arrangement is opposite to that of the eleventh embodiment shown above, and shows that such a configuration may be adopted. The shape of the laser trimming positioning pattern 401 may be any characteristic shape different from the pad area 202 in the semiconductor integrated circuit chip 201 or the like so that image recognition can be performed automatically. 13), the shape is a key shape. However, the shape is not limited to the shapes shown in FIGS. 13A and 15A.

For other explanations, see FIG.
The description is replaced by the same reference numerals as in (c). In some cases, a second insulating film or the like may be formed on the first insulating film 102 or the polycrystalline silicon thin film 103 in FIG. Further, instead of the aluminum film 105, a metal material such as tungsten, chromium, or gold may be used as the high light reflectance film. Although not particularly shown, FIG.
A silicon oxide film such as a silicon nitride film, an NSG film, a PSG film, or a BPSG film, or a light-transmitting insulating film such as a polyimide film is disposed on the aluminum film 105 in FIG. It is also possible to increase the contrast of the light reflection amount between the high light reflectance region 106 and the low light reflectance region 107 by increasing the irregular reflection of the light at the light-receiving portion 106 so as to obtain a lower light reflectance.

In particular, when an IC is manufactured on an SOI substrate, the polycrystalline silicon thin film 103 described with reference to FIG.
Is replaced with a single-crystal silicon device formation layer formed on the buried oxide film of the SOI substrate,
02 may be replaced with a buried oxide film of an SOI substrate. In this case, the fuse element is also formed of a single crystal silicon device forming layer, and the laser trimming positioning pattern is formed of the same thin film as the laser trimming fuse element.

FIG. 16A is a schematic plan view showing a part of a laser trimming positioning pattern and a laser beam according to the present invention. In FIG. 16A, a shows the line-and-space size (sum of the size of the dot made of the same material as the fuse element and the size of the portion where no dot is formed) of a set of dot-shaped polycrystalline silicon thin films 103. Also, d indicates the diameter of the laser beam spot 501.

FIG. 16B shows the contrast, which is the difference between the amount of light reflection in the high light reflectance region and the amount of light reflection in the low light reflectance region, and the line and space dimensions of a set of dot-shaped polycrystalline silicon thin films 103. It is a figure showing the relation with a. The contrast is a set of dot-shaped polycrystalline silicon thin films 1
The smaller the line and space dimension a of 03 is, the better. Considering the diameter d of the laser beam spot 501 as an index, a practically available contrast is reached if the line and space dimension a of the set of dot-shaped polycrystalline silicon thin films 103 is about the diameter d of the laser beam spot 501 or less. However, in order to obtain a higher contrast, a set of dot-shaped polycrystalline silicon thin films 103
Is preferably equal to or less than half the diameter d of the laser beam spot 501. In FIG. 16, a dot-like polycrystalline silicon thin film 103 is shown.
However, the same applies to the case of a lattice or stripe pattern. For example, in the case of a stripe pattern, one polycrystalline silicon thin film 103 is used.
Of the short side of the line of FIG.
The sum of the size of the gap with the line of FIG.
You can replace it with

FIG. 17A is a schematic plan view showing a part of a laser trimming positioning pattern and a laser beam according to the present invention. In FIG. 17A, b indicates the dimension of the low light reflectance area 107 in the laser scanning direction, and d indicates the diameter of the laser beam spot 501. FIG. 17B shows the relationship between the contrast, which is the difference between the amount of light reflection in the high light reflectance region 106 and the amount of light reflection in the low light reflectance region 107, and the dimension b of the low light reflectance region 107 in the laser scanning direction. FIG.

The contrast increases as the dimension b of the low light reflectance area 107 in the laser scanning direction increases. Considering the diameter d of the laser beam spot 501 as an index, a practically available contrast is reached if b is about d or more.
It is desirable that the dimension be at least twice as large as d. FIG.
Although the case of the dot type has been described, the low light reflectance region 1 is formed by a lattice or stripe pattern.
The same applies to the case where 07 is formed.

FIG. 17 shows the case where the low light reflectance area 107 is sandwiched between the high light reflectance areas 106, but the high light reflectance area 106 as shown in the example of FIG.
1 is sandwiched between the low light reflectance regions 107, FIG.
The same result can be obtained by replacing b described in 7 with the size of the high light reflectance region 106. In the laser trimming positioning pattern according to the present invention described with reference to FIGS. 16 and 17, the line and space dimension a of the set of dot-shaped polycrystalline silicon thin films 103 and the diameter d of the laser beam spot 501 are set. And the desirable dimensional relationship between the dimension b of the low light reflectance region 107 in the laser scanning direction and the diameter d of the laser beam spot 501 are the same as those of the first embodiment of the present invention described above.
It is possible to apply to all of the twelfth to twelfth embodiments.

Further, particularly when an IC is manufactured on an SOI substrate, the polycrystalline silicon thin film 103 described with reference to FIGS. 16 and 17 is formed on a buried oxide film of the SOI substrate to form a single crystal silicon device. What is necessary is just to replace it with a layer. In this case, the fuse element is also formed of a single crystal silicon device forming layer, and the laser trimming positioning pattern is formed of the same thin film as the laser trimming fuse element.

FIG. 18 is a plan view of a fuse element laser-trapped using the positioning pattern of the present invention. The laser spot 32 can irradiate the center of the fuse element 31. The semiconductor device of the present invention is very suitable for a semiconductor integrated circuit including semiconductor elements having large variations. For example, FIG.
FIG. 3 is a block diagram of a voltage detection IC composed of transistors. MOSICs have larger variations in analog characteristics than bipolar ICs. In particular, in the case of high withstand voltage characteristics,
Since the thickness of the gate insulating film is increased, variations in analog characteristics are further increased. Therefore, the analog MOSI
In the case of C, a large fuse element area is required as shown in FIG. By providing ten or more fuse elements, analog characteristics with small variations can be obtained.

By using the laser trimming positioning pattern of the present invention, the area occupied by the fuse element of the voltage detecting IC as shown in FIG. 10 can be reduced, and the entire IC can be reduced in area. Although not shown, the same effect can be obtained by using the laser trimming positioning pattern according to the present invention for a series regulator IC, a switching regulator IC, a lithium battery protection IC, and the like. Further, since the alignment accuracy of laser trimming is improved, it is possible to arrange the fuse elements used in these ICs in two or more places by differentiating the arrangement direction in a plane.

The positioning pattern of the present invention can be embodied in a scribe line area, a TEG chip, or a semiconductor integrated circuit chip. When placed in the scrub line area or TEG chip,
This has the effect of reducing the area of the semiconductor integrated circuit chip.
The present invention is suitable for an analog MOSIC,
It can also be used for digital ICs. It is also suitable for high-density analog bipolar ICs with very small variations.

In the embodiments described so far, the case where the fuse element for laser trimming is formed of a polycrystalline silicon thin film has been described. However, the present invention is not limited to the polycrystalline silicon thin film. What is necessary is just to form the low light reflectance area 107 as a dot-like pattern that causes irregular reflection of light by using the same thin film as the element forming thin film. Therefore, the structure is suitable for an IC manufactured on an SOI substrate.

[0067]

According to the laser trimming positioning pattern of the present invention, the boundary between the high light reflectance area and the low light reflectance area, that is, the place where the light reflectance changes sharply, is formed by the same thin film as the laser trimming fuse element. Can be defined by the specified pattern. Furthermore, a desirable relationship between the size inside the laser trimming positioning pattern and the laser beam spot diameter was shown. This has the following effects. (1) It is possible to stably cut the fuse element. (2) In an IC requiring a plurality of fuse elements,
The fuse element region can be formed with a small area. (3) In an IC that requires a plurality of fuse elements, it is possible to design the fuse element regions at two or more locations in different directions.

The laser trimming positioning pattern according to the present invention is formed in an existing pad area in a semiconductor integrated circuit chip, or a so-called theta mark for performing a relatively rough alignment with respect to the rotation direction of a semiconductor wafer. It can be arranged at the intersection of scribe lines as a continuous structure that can serve both the function and the function of a trimming mark for performing accurate alignment for each of the repeatedly arranged semiconductor integrated circuits. .

This has the following effects. (4) In cutting out the semiconductor integrated circuit (dicing step), the dicing blade is hardly damaged, and the throughput is improved. Further, the risk of damaging the semiconductor integrated circuit is reduced. (5) In the scribe line region, a region for inserting a test pattern, a mark for pattern matching, and the like used in a semiconductor integrated circuit forming process (so-called previous process) is expanded, and sufficient process management can be performed.

[Brief description of the drawings]

FIG. 1A is a plan view of a laser trimming positioning pattern of a semiconductor device of the present invention.
FIG. 2B is a diagram illustrating the amount of light reflection along the line AA ′ in FIG.

FIG. 2 (a) is a plan view of a laser trimming positioning pattern of a semiconductor device according to a second embodiment of the present invention, and FIG. 2 (b) is a sectional view taken along the line CC of FIG. 3 (a). It is a figure which shows the light reflection amount along a line.

FIG. 3A is a plan view of a laser trimming positioning pattern of a conventional semiconductor device.
FIG. 3B is a diagram illustrating a light reflection amount along the line BB ′ in FIG.

FIG. 4 (a) is a plan view of a laser trimming positioning pattern of a third embodiment of the semiconductor device of the present invention, and FIG. 4 (b) is a third view of the third embodiment of the semiconductor device of the present invention. FIG. 4C is a cross-sectional view of the laser trimming positioning pattern according to the example, and FIG. 4C is a diagram illustrating a light reflection amount along the line AA ′ in FIG.

FIG. 5 (a) is a plan view of a laser trimming positioning pattern according to a fourth embodiment of the semiconductor device of the present invention, and FIG. 5 (b) is a fourth view of the fourth embodiment of the semiconductor device of the present invention. FIG. 5C is a cross-sectional view of the laser trimming positioning pattern according to the example, and FIG. 5C is a diagram illustrating a light reflection amount along the line CC ′ in FIG.

FIG. 6A is a plan view of a laser trimming positioning pattern according to a fifth embodiment of the semiconductor device of the present invention, and FIG. 6B is a plan view of the fifth embodiment of the semiconductor device of the present invention. FIG. 6C is a cross-sectional view of the laser trimming positioning pattern according to the example, and FIG. 6C is a diagram illustrating a light reflection amount along the line DD ′ in FIG.

FIG. 7A is a plan view of a laser trimming positioning pattern according to a sixth embodiment of the semiconductor device of the present invention, and FIG. 7B is a sixth view of the sixth embodiment of the semiconductor device of the present invention. FIG. 7C is a cross-sectional view of the laser trimming positioning pattern according to the example, and FIG. 7C is a diagram illustrating a light reflection amount along the line EE ′ in FIG.

FIG. 8 (a) is a schematic plan view of a semiconductor integrated circuit chip including a laser trimming positioning pattern of a seventh embodiment of the semiconductor device according to the present invention. FIG. 8B is an enlarged schematic plan view of a pad region where the laser trimming positioning pattern of FIG. 8A is arranged.

FIG. 9A is a plan view of a laser trimming positioning pattern according to a seventh embodiment of the semiconductor device of the present invention, and FIG. 9B is a seventh view of the semiconductor device of the present invention. FIG. 9C is a cross-sectional view of the laser trimming positioning pattern according to the example, and FIG. 9C is a diagram illustrating a light reflection amount along the line AA ′ in FIG.

FIG. 10A is a plan view of a laser trimming positioning pattern according to an eighth embodiment of the semiconductor device of the present invention, and FIG. 10B is a plan view of the laser according to the eighth embodiment of the semiconductor device of the present invention. It is sectional drawing of the pattern for trimming positioning, (c) is a figure which shows the light reflection amount along CC 'line of FIG.10 (a).

FIG. 11A shows a ninth semiconductor device according to the present invention;
FIG. 11B is a plan view of the laser trimming positioning pattern of the ninth embodiment, and FIG. 11B is a cross-sectional view of the laser trimming positioning pattern of the ninth embodiment of the semiconductor device of the present invention, and FIG. FIG. 12 is a diagram showing a light reflection amount along a line DD ′ in FIG.

FIG. 12A shows a first example of the semiconductor device of the present invention.
FIG. 12B is a plan view of a laser trimming positioning pattern according to the tenth embodiment, and FIG. 12B is a cross-sectional view of the laser trimming positioning pattern according to the tenth embodiment of the semiconductor device of the present invention. ) Indicates E- in FIG.
It is a figure which shows the light reflection amount along E 'line.

FIG. 13A shows a first example of the semiconductor device of the present invention.
FIG. 13B is a plan view of the laser trimming positioning pattern of the first embodiment, and FIG. 13B is a cross-sectional view of the laser trimming positioning pattern of the eleventh embodiment of the semiconductor device of the present invention. ) Is A- in FIG.
It is a figure which shows the light reflection amount along A 'line.

FIG. 14 is a plan view of a fuse element of a conventional semiconductor device.

FIG. 15A is a first view of the semiconductor device of the present invention.
FIG. 15B is a plan view of the laser trimming positioning pattern according to the second embodiment, and FIG. 15B is a cross-sectional view of the laser trimming positioning pattern according to the twelfth embodiment of the semiconductor device of the present invention. ) Is B- in FIG.
It is a figure which shows the light reflection amount along the B 'line.

FIG. 16 (a) is a schematic plan view showing a part of a laser trimming positioning pattern and a laser beam spot according to the present invention, and FIG. 16 (b) shows light reflection in a high light reflectance region. FIG. 4 is a diagram showing a relationship between contrast, which is a difference between the amount of light and the amount of light reflection in a low light reflectance region, and a line and space dimension a of a set of dot-like polycrystalline silicon thin films.

FIG. 17A is a schematic plan view showing a part of a laser trimming positioning pattern and a laser beam spot according to the present invention, and FIG. 17B shows light reflection in a high light reflectance region. FIG. 7 is a diagram illustrating a relationship between a contrast, which is a difference between an amount and a light reflection amount in a low light reflectance region, and a dimension b of the low light reflectance region in a laser scanning direction.

FIG. 18 is a plan view of a fuse element of the semiconductor device of the present invention.

FIG. 19 is a block diagram of a semiconductor device of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 31 fuse element 32 laser irradiation spot area 33 area where base is scorched 34 remaining part of fuse cut 101 silicon substrate 102 first insulating film 103 polycrystalline silicon thin film 104 second insulating film 105 aluminum film 106 high light reflectance region 107 Low light reflectance area 201 Semiconductor integrated circuit chip 202 Pad area 203 Scribe line area 204 Laser trimming positioning pattern 301 Theta mark 302 X direction trimming mark 303 Y direction trimming mark 401 Laser trimming positioning pattern 501 Laser beam spot a One set Of the line-and-space of the dot-shaped polycrystalline silicon thin film 103, b. The dimension of the low light reflectance area 107 in the laser scanning direction, d.

Claims (43)

[Claims] 1. A semiconductor integrated circuit repeatedly arranged in a two-dimensional matrix on a surface of a semiconductor wafer via a scribe line, a fuse provided in the semiconductor integrated circuit and cut by laser trimming,
A semiconductor device comprising a laser trimming positioning pattern provided on a surface of the semiconductor wafer, wherein the laser trimming positioning pattern is formed of the same thin film as the fuse. 2. The semiconductor device according to claim 1, wherein the laser trimming positioning pattern includes a high light reflectance region and a low light reflectance region sandwiched between the high light reflectance regions. 3. The semiconductor device according to claim 1, wherein the laser trimming positioning pattern comprises the low light reflectivity region and the high light reflectivity region sandwiched between the low light reflectivity regions. 4. The semiconductor device according to claim 2, wherein the low light reflectivity region is a dot, lattice, or stripe pattern for diffusely reflecting light. 5. The semiconductor device according to claim 3, wherein the low light reflectance region is a dot, a lattice, or a stripe pattern for diffusely reflecting light. 6. The semiconductor device according to claim 2, wherein said fuse is made of a polycrystalline silicon thin film. 7. The semiconductor device according to claim 3, wherein said fuse is made of a polycrystalline silicon thin film. 8. The semiconductor integrated circuit repeatedly arranged in a two-dimensional matrix on the surface of the semiconductor wafer via the scribe line, the fuse provided in the semiconductor integrated circuit, In the semiconductor device comprising the laser trimming positioning pattern provided on the surface, the laser trimming positioning pattern comprises the high light reflectance region and the low light reflectance region, and the high light reflectance region is flat. The low light reflectivity region is formed on a dot, lattice or stripe pattern for diffusely reflecting light, which is formed of the same thin film as the fuse. A semiconductor device comprising the high light reflectance film formed as described above. 9. The semiconductor device according to claim 8, wherein the laser trimming positioning pattern includes the high light reflectivity region and the low light reflectivity region sandwiched between the high light reflectivity regions. 10. The semiconductor device according to claim 8, wherein the laser trimming positioning pattern comprises the low light reflectance region and the high light reflectance region sandwiched between the low light reflectance regions. 11. The semiconductor device according to claim 8, wherein said fuse is made of a polycrystalline silicon thin film. 12. The semiconductor device according to claim 8, wherein said high light reflectance film is made of aluminum. 13. The semiconductor device according to claim 8, wherein the laser trimming positioning pattern is arranged in a pad area for making an electrical connection with the outside in the semiconductor integrated circuit chip. . 14. The semiconductor device according to claim 8, wherein said laser trimming positioning pattern is arranged at an intersection of said scribe lines. 15. The laser trimming positioning pattern includes a so-called theta mark for relatively coarse positioning with respect to the rotation direction of the semiconductor wafer, and an X-direction and a Y-direction for each of the semiconductor integrated circuits. 9. The semiconductor device according to claim 8, wherein a so-called trimming mark for precise positioning is integrated with the continuous high reflectivity film. 16. A set of line-and-space dimensions of a thin film formed of the same material as the fuse in the form of dots, grids, or stripes for forming the low light reflectance region in the laser trimming positioning pattern. The semiconductor device according to claim 1, wherein is smaller than the diameter of the laser beam spot. 17. A set of line-and-space dimensions of a thin film formed of the same material as that of the dots, grids, or stripes of the fuses forming the low light reflectance region in the laser trimming positioning pattern. 2. The semiconductor device according to claim 1, wherein is less than half the diameter of the laser beam spot. 3. 18. The semiconductor device according to claim 2, wherein a size of the low light reflectance area in a laser beam scanning direction is equal to or larger than a diameter of the laser beam spot. 19. The semiconductor device according to claim 3, wherein a size of the high light reflectance area in the laser beam scanning direction is equal to or larger than a diameter of the laser beam spot. 20. The semiconductor device according to claim 2, wherein a size of the low light reflectance area in the laser beam scanning direction is at least twice a diameter of the laser beam spot. 21. The semiconductor device according to claim 3, wherein a size of the high light reflectance area in the laser beam scanning direction is at least twice a diameter of the laser beam spot. 22. In the laser trimming positioning pattern, a set of line-and-space dimensions of a thin film made of the same material as the dots, grids, or stripes of the fuse forming the low light reflectance region. The semiconductor device according to claim 8, wherein is smaller than the diameter of the laser beam spot. 23. In the laser trimming positioning pattern, a set of line-and-space dimensions of a thin film made of the same material as the dots, grids, or stripes of the fuses forming the low light reflectance region. 9. The semiconductor device according to claim 8, wherein is less than half the diameter of the laser beam spot. 24. The semiconductor device according to claim 9, wherein a size of the low light reflectance area in a laser beam scanning direction is equal to or larger than a diameter of the laser beam spot. 25. The semiconductor device according to claim 10, wherein a dimension of the high light reflectance area in the laser beam scanning direction is equal to or larger than a diameter of the laser beam spot. 26. The semiconductor device according to claim 9, wherein a size of the low light reflectance area in the laser beam scanning direction is at least twice a diameter of the laser beam spot. 27. The semiconductor device according to claim 10, wherein a size of the high light reflectance region in the laser beam scanning direction is at least twice a diameter of the laser beam spot. 28. The semiconductor device according to claim 1, wherein the number of the fuses provided in the semiconductor integrated circuit is 10 or more. 29. The semiconductor device according to claim 8, wherein the number of the fuses provided in the semiconductor integrated circuit is 10 or more. 30. The semiconductor device according to claim 1, wherein a plurality of fuse groups formed by arranging at least one or more fuses in the same direction in different directions are provided in the semiconductor integrated circuit. 31. The semiconductor device according to claim 8, wherein a plurality of fuse groups formed by arranging at least one or more fuses in the same direction in a different direction are provided in the semiconductor integrated circuit. . 32. The semiconductor integrated circuit is a voltage detection IC.
The semiconductor device according to claim 1, wherein 33. The semiconductor device according to claim 1, wherein said semiconductor integrated circuit is a series regulator IC. 34. The semiconductor device according to claim 1, wherein said semiconductor integrated circuit is a switching regulator IC. 35. The semiconductor device according to claim 1, wherein said semiconductor integrated circuit is a lithium battery protection IC. 36. The semiconductor integrated circuit is a voltage detection IC.
9. The semiconductor device according to claim 8, wherein 37. The semiconductor device according to claim 8, wherein said semiconductor integrated circuit is a series regulator IC. 38. The semiconductor device according to claim 8, wherein said semiconductor integrated circuit is a switching regulator IC. 39. The semiconductor device according to claim 8, wherein the semiconductor integrated circuit is a lithium battery protection IC. 40. The semiconductor device according to claim 1, wherein an insulating film capable of transmitting light is disposed on an uppermost layer of the laser trimming positioning pattern. 41. The semiconductor device according to claim 8, wherein an insulating film capable of transmitting light is disposed on the high light reflectance film of the laser trimming positioning pattern. 42. The semiconductor device according to claim 1, wherein said semiconductor wafer is formed of an SOI substrate, and said fuse is formed of a single crystal silicon device forming layer on said SOI substrate. 43. The semiconductor device according to claim 8, wherein said semiconductor wafer is made of an SOI substrate, and said fuse is formed by said single crystal silicon device forming layer on said SOI substrate.