JP2000340623A - Semiconductor device, method for controlling the same, and test controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be subjected to a collective wafer test, while the self-heating value of the device is being adjusted. SOLUTION: A simultaneously measuring number control adapter 212 gives a monitor input signal indicating whether peripheral chips are being tested to each chip. When a temperature detecting circuit 208 detects an abnormal temperature, a BIST circuit 206 suppresses the heating values of the chips by stopping prescribed time test on waiting time. At temporary stop of the tests, the BIST circuit 206 decides the temporary stop duration of the tests by taking the tested states of the peripheral chips into consideration by referring to the monitor input signal. Therefore, all wafers as a whole can be tested within a relatively short processing time, while the self-heating value is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method for testing a semiconductor device, and a test control device for a semiconductor device. More specifically, the present invention relates to a semiconductor device having a self-test function and a plurality of such semiconductor devices simultaneously. The present invention relates to a test method and a test control device for measuring.

[0002]

2. Description of the Related Art In recent years, as the scale of semiconductor devices has increased and become more complex, the testing of semiconductor devices has become more difficult year by year. 2. Description of the Related Art Semiconductor devices having a built-in self-test function have come to be seen in order to reduce the load on a semiconductor test device and facilitate testing. This self-test function is B
It is called IST (built-in self test). BIS
With the advancement of the T technology, a function test, that is, a function test, which has conventionally been performed using a semiconductor test apparatus, can be performed by the chip itself. If a power supply and a clock signal are supplied to the chips from the outside, the test can be performed. Accordingly, all the chips on the wafer can be simultaneously measured.

FIG. 14 is a flowchart showing a flow of inspection of a conventional semiconductor device having a built-in BIST.

Referring to FIG. 14, first, at step S10
At 0, a DC measurement is made on the semiconductor device.
The DC measurement is a test for measuring a DC electrical characteristic of a semiconductor device such as a power supply current. Thus, a defect such as an abnormal current is detected and recorded by the semiconductor tester.

Next, in step S102, an operation of removing the defective chip recorded in step S100 is performed. The term “removal” does not mean that the chip is physically cut off, but the connection of the chip is cut off by cutting a fuse element built in the chip or applying an insulator on the chip surface. As a result, a defective chip is excluded from the measurement target of the next function test.

Next, in step S103, a power supply and a clock signal are supplied to the wafer, and a function test is performed on the chips on the wafer at once by a self test circuit, ie, a BIST circuit built in each chip. The result of the function test is recorded, and in step S104, pass / fail is determined based on the result.

[0007]

What is problematic in performing a wafer batch test is a measure against chip self-heating. In recent years, the degree of integration of semiconductor devices has been increased and the operating speed has been increased, so that self-heating of chips has been increased. In the final product, a heat radiating plate or the like can be attached to each semiconductor device to cope with the problem. However, in a wafer state, each chip is not separated and heat generation is deteriorated.

For example, in the case of chips arranged in a matrix of three rows and three columns, even if the heat generation of nine chips is uniform, the heat radiation of the center chip is poor due to the heat influence of the surrounding chips. Temperature rises abnormally.

If the temperature rise exceeds the operable temperature range of the semiconductor device, there is a problem that the test becomes impossible.

An object of the present invention is to provide a semiconductor device, a semiconductor device test method, and a semiconductor device test control device capable of performing a wafer batch test by controlling heat generation during a test in a wafer state.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device formed on a main surface of a semiconductor substrate, comprising: an internal circuit; a temperature detecting circuit for detecting a temperature of the semiconductor substrate; And a self-test circuit for performing a self-test on the internal circuit. The self-test circuit temporarily stops the self-test according to the output of the temperature detection circuit.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect.
In addition to the configuration of the semiconductor device described in the above, further comprising an input pad to which a monitor input signal according to the test execution status of another semiconductor device close to the semiconductor device on the semiconductor wafer is provided, The suspension period is determined according to the traffic light.

According to a third aspect of the present invention, there is provided a semiconductor device according to the second aspect.
In the configuration of the semiconductor device described in the above, when the monitor input signal indicates that the other semiconductor device has completed the self-test, the self-test circuit sets the suspension period to the first time, When the signal indicates that the self-test of the other semiconductor device is not completed, the suspension period is set to a second time longer than the first time.

According to a fourth aspect of the present invention, there is provided a semiconductor device according to the second aspect.
In addition to the configuration of the semiconductor device described in 1 above, the semiconductor device further includes an output pad for outputting a test monitor output signal indicating that the self-test is not completed to other semiconductor devices.

According to a fifth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
In addition to the configuration of the semiconductor device described in the above, the temperature detection circuit,
A measuring current generating circuit for generating a predetermined current, a temperature detecting element for receiving a predetermined current to generate a first potential according to a temperature of the semiconductor substrate, and a potential corresponding to an upper limit temperature at which the semiconductor device can operate. A reference voltage generating circuit for outputting a second potential having a small temperature dependency with respect to the first potential; a voltage comparing circuit for comparing the first potential with the second potential to detect a temperature abnormality; including.

According to a sixth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
In addition to the configuration of the semiconductor device described in the above, the temperature detection circuit,
A measuring current generating circuit for generating a predetermined current for measuring the temperature of the semiconductor substrate, a temperature detecting element for receiving the predetermined current and generating a first potential according to the temperature of the semiconductor substrate,
And an A / D conversion circuit for AD-converting the potential of the A / D converter.

According to a seventh aspect of the present invention, there is provided a method of controlling a semiconductor device, comprising: a temperature detecting circuit formed on a main surface of a semiconductor substrate for detecting a temperature of the semiconductor substrate; A plurality of semiconductor devices each including a self-test circuit for temporarily suspending a self-test, and controlling the semiconductor devices when testing the plurality of semiconductor devices in parallel when the plurality of semiconductor devices are arranged on a semiconductor wafer The method comprises the steps of: starting a self-test; detecting a self-temperature abnormality during a test period; and interrupting the self-test for a predetermined waiting time when the self-temperature is abnormal.

According to a eighth aspect of the present invention, in addition to the configuration of the semiconductor device control method according to the seventh aspect, a step of detecting a test execution state of a peripheral chip on the semiconductor wafer is provided. Switching a predetermined waiting time according to the test execution status.

According to a ninth aspect of the present invention, there is provided a test control device formed on a main surface of a semiconductor substrate, for detecting a temperature of the semiconductor substrate, performing a self test, and providing an output of the temperature detection circuit and an external signal. When a plurality of semiconductor devices each including a self-test circuit that suspends a self-test in response to a monitor input signal received are arranged on a semiconductor wafer, the plurality of semiconductor devices are tested in parallel by a measuring device. A test control device for controlling the operation of the semiconductor device when the second semiconductor device is provided in correspondence with the first semiconductor device of the plurality of semiconductor devices, and is provided on the semiconductor wafer in proximity to the first semiconductor device. A gate circuit that supplies a monitor input signal to the first semiconductor device according to a test execution state of the semiconductor device;

According to a tenth aspect of the present invention, in the test control device according to the ninth aspect, each of the semiconductor devices outputs a test monitor output signal indicating that the self-test is incomplete. The gate circuit outputs a monitor input signal according to the test monitor output signal output from the second semiconductor device.

The test control device according to claim 11 is the test control device according to claim 10, wherein
The main surface of the semiconductor substrate of the first, second, third and fourth
And the second semiconductor device on the semiconductor wafer has the first side as a boundary on the first side.
And the third, fourth and fifth semiconductor devices on the semiconductor wafer are adjacent to the first semiconductor device with the second, third and fourth sides as boundaries, respectively. Test monitor output signals output from the fifth to fifth semiconductor devices are respectively referred to as first to fifth monitor output signals, and test monitor input signals supplied to the first to fifth semiconductor devices are respectively referred to as first to fifth monitors. Assuming that the input signal is an input signal, the gate circuit deactivates the first test monitor input signal when any of the second to fifth monitor output signals indicates the end of the test.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a block diagram for explaining measurement of a semiconductor device 100 according to a first embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 100 includes a memory circuit 102 having memory cells arranged in a matrix and a memory circuit 102 which receives a clock signal CLK, a command signal CMD, and a suspension signal SUSPEND from outside. And a test result signal F
It includes a BIST circuit 104 that outputs S and a test end signal END, and a diode element 106 for measuring a chip temperature.

The semiconductor device 100 has n chips, that is, devices DUT1 to DUTn, arranged on a semiconductor wafer. The devices DUT <b> 1 to DUTn are collectively measured by the measuring device 120, and after the measurement is separated into chips after the measurement, defective chips are removed according to the quality of the measurement result.

The measuring device 120 includes devices DUT 1 to DUT
A program power supply 122 for supplying a power supply potential Vcc and a ground potential Vss to UTn, and devices DUT1 to DUTn
The clock signal CLK is supplied to the BIST circuit 104 mounted on the
Signal PG (pattern generator) 124 for providing a command signal CMD for setting a test mode to perform a self-test, and devices DUT1 to DUT
A constant current is passed through the diode element 106 mounted on n.
DC that detects temperature by measuring generated voltage
And a measuring unit 128.

The measuring apparatus 120 further controls a program power supply 122 and an input signal PG 124 to control each of the devices DUT1 to DUTn according to the output of the DC measuring unit 128.
Recognizes the temperature status of the
A CPU 126 for sending PEND to a required device;
A storage unit 130 for storing test results of all chips included in the wafer given by test end signal END and test result FS.

FIG. 2 is a flowchart for explaining a test flow in the first embodiment.

Here, for the sake of simplicity, a case where three chips DUT1, DUT2, and DUT3 arranged on a wafer are simultaneously tested will be described.

Referring to FIGS. 1 and 2, first, at step S1
, The tests of the devices DUT1 to DUT3 are started at the same time.

Next, in step S2, the device D
The temperatures of the UT1 to DUT3 are monitored by the DC measuring unit 128 of the measuring device 120. This value is transferred to the CPU 126 in step S3, and an abnormality is determined.
If the temperature is normal, the temperature of each device is monitored while the test operation is continued in step S2. On the other hand, if a temperature abnormality is detected, for example, in step S4, the test of the device DUT2 is temporarily stopped, and heat generation on the wafer is suppressed.
In this case, the CPU 126 activates the suspension signal SUSPEND for the device DUT2. And
In step S5, the test of the devices DUT1 and DUT3 ends. The end of the test is detected by the CPU 126 observing the test end signal END. Subsequently, in step S6, the device DUT1
In step S7 where the temperature of the DUT 3 is monitored, an abnormality in the temperature is determined. If the temperature is abnormal, the process returns to step S6 again, and waits until the temperature becomes normal. On the other hand, if the temperature is normal,
Proceeding to step S8, the test of the device DUT2 suspended in step S4 is restarted.

As described above, when there is an abnormality while monitoring the temperature of each chip, the BIST circuit of the chip is temporarily stopped, and the number of chips that are being tested is adjusted to reduce heat generation and reduce the temperature. This makes it possible to perform the wafer batch test at a lower temperature.

[Embodiment 2] In Embodiment 1, FIG.
The temperature is detected by the DC measuring unit 128 incorporated in the measuring device shown in FIG. 3 and the measuring device 120 outputs a pause signal to adjust the number of measurements.

However, in this case, the number of chips is 3
Twice the number of wirings is required for measuring the temperature and instructing a temporary stop, resulting in a problem that the number of wirings for connecting the semiconductor device and the test equipment increases and the test equipment becomes expensive.

FIG. 3 is a block diagram for explaining measurement of semiconductor device 200 according to the second embodiment of the present invention.

Referring to FIG. 3, a semiconductor device 200 receives a clock signal CLK and a command signal CMD from a memory circuit 202 having memory cells arranged in a matrix and performs a self-test of the memory circuit 202. And a test circuit 204.

The test circuit 204 receives a clock signal CLK and a command signal CMD for setting a test mode from the outside in response to a temperature detection circuit 208 for detecting a temperature of a chip and outputting a temperature detection signal ET for notifying an abnormal temperature. A BIST circuit 206 that performs a self-test of the memory circuit in accordance with the input monitor input signal MI and the temperature detection signal ET, activates the monitor output signal MO during the test, and outputs a test result signal FS when the test ends.

In the semiconductor device 200, n devices are arranged on a wafer. The n semiconductor devices 200, that is, the devices DUT1 to DUTn are collectively measured by the measuring device 220.

The measuring device 220 includes devices DUT1 to DUT
A program power supply 222 for supplying a power supply potential Vcc and a ground potential Vss to UTn, and devices DUT1 to DUTn
PG for input signal, which supplies clock signal CLK to clock signal and command signal CMD for setting the test mode
224, a program power supply 222 and an input signal PG
The CPU 226 controls the H.224, receives the monitor output signal MO from the devices DUT1 to DUTn, detects the end of the test, and fetches the test result signal FS, and includes a storage unit 230 that stores the test result fetched by the CPU 226.

Test apparatus 220 and devices DUT1 to DUT
UTn is connected via the interface unit 210. The interface unit 210 includes a simultaneous measurement number control adapter 212 that receives the test monitor output signal MO and supplies the test monitor input signal MI to DUT1 to DUTn.

FIG. 4 shows the temperature detection circuit 208 shown in FIG.
FIG. 2 is a block diagram for explaining the configuration of FIG.

Referring to FIG. 4, temperature detection circuit 208 includes:
A measuring current generating circuit 242 for generating a constant current, a temperature detecting element 244 for receiving a current from the measuring current generating circuit 242 and outputting a predetermined potential, and a reference voltage generating circuit for generating a reference potential with little temperature dependency 245, and a voltage comparison circuit 246 that compares the output voltage of the temperature detection element 244 with the output voltage of the reference voltage generation circuit.

The reference potential generated by reference voltage generating circuit 245 is set to a potential corresponding to the upper limit temperature at which the semiconductor device can operate.

Voltage comparison circuit 246 outputs an L level when the output potential of temperature detecting element 244 is higher than the reference potential output from reference voltage generation circuit 245, and outputs an H level when the output potential is lower than the reference potential. Is output. The temperature detection signal ET, which is an output signal of the voltage comparison circuit 246, is at the L level when the temperature is normal, and at the H level when the temperature is abnormally high.
Level.

CPU 248 receives temperature signal ET and monitor input signal MI and determines whether to continue the self-test or to suspend the self-test. The monitor output signal MO is activated until the self test is completed.

FIG. 5 is a diagram for explaining the arrangement of the interface section 210 shown in FIG. 3 at the time of measurement.

Referring to FIG. 5, head 254 is connected to the measuring apparatus main body by cable 252. The head 254 is provided with pogo pins 255 for all signals exchanged between the test apparatus and the device.

The interface unit 256 includes the head 25
4 is mounted to make electrical contact between the pogo pins 255 on the wafer 4 and the wafer connection part 258. Wafer connection part 25
8 is provided with terminals for contacting pads on the wafer 260 to be measured.

The wafer chuck 262 is connected to the wafer 2 to be measured.
It is provided on an X, Y, and Z movement mechanism 264 for adjusting the positional relationship between the wafer connection part 258 and the wafer 260 to be measured.

FIG. 6 is a plan view showing the structure of wafer connection portion 258. Referring to FIG.
On the 60, terminals for electrically connecting the chips C # 11 to C # 44 arranged in a 4 × 4 matrix are provided. For example, on AA, chip C
Terminals Ta # 21 to Ta # 2 corresponding to # 21 to C # 24
4 and terminals Tb # 21 to Tb # 24.

FIG. 7 is a sectional view taken along the line AA in FIG. In FIG. 7, the wafer to be measured 26
0 shows a state in which the wafer connection portion 258 is in contact with the wafer connection portion 258.
The wafer connection unit 258 is connected to the substrate 272 and the wafer 2 to be measured.
60, terminals Ta # provided corresponding to pads 274 on
21 to Ta # 24 and terminals Tb # 21 to Tb # 24. Wiring connected to the measuring device via the interface unit is connected between the terminals.

FIG. 8 is a plan view for explaining the positions of the terminals of the simultaneous measurement number control adapter 212 shown in FIG.

Referring to FIG. 8, simultaneous measurement number control adapter 212 includes terminals Ta # 1 corresponding to chips C # 11-C # 44 arranged in a matrix on the wafer, respectively.
1 to Ta♯44 and Tb♯11 to Tb♯44.

Terminal Ta # 11 is connected to chip C # 1 during measurement.
1 is a terminal that comes into contact with a pad to which the monitor output signal MO # 11 is output from 1 during measurement. Terminal Tb # 11 is a terminal that contacts a pad to which chip C # 11 receives monitor input signal MI # 11 during measurement.

Similarly, the terminal Ta @ mn is connected to the chip C @ m
n is a terminal that contacts a pad from which a monitor output signal MO # mn is output. Terminal TB {mn is chip C}.
mn is a terminal that comes into contact with a pad for inputting a monitor input signal MI @ mn. (M and n are integers of 1 to 4) FIG. 9 is a circuit diagram for explaining a circuit included in the simultaneous measurement number control adapter 212.

Referring to FIG. 9, the simultaneous measurement number control adapter includes an OR circuit G # mn for supplying a monitor input signal MI # mn to each chip. The OR circuit G @ mn is
Monitor output signal MO♯ (m-1) n, MO♯ (m + 1)
n, MO♯m (n−1) and MO♯m (n + 1) are input and output a monitor signal MI♯mn applied to the chip.

That is, the logical sum of the monitor output signals of the vertically and horizontally adjacent chips is given as the monitor input signal of the m-th row and n-th column chip. When the position of the chip is in the periphery of the wafer, there may be no adjacent chip. In this case, an L-level signal is supplied instead of the monitor output signal from the non-existing adjacent chip or input to the OR circuit. The number of signals used is reduced accordingly.

FIG. 10 is a circuit diagram showing a state in which OR circuits provided corresponding to respective chips of the simultaneous measurement number control adapter shown in FIGS. 8 and 9 are arranged.

The connection relationship of each of OR circuits G # 11 to G # 44 is as described with reference to FIG. 9, but for a more specific description, the connection relationship of OR circuit G # 22 will be described again.

Referring to FIG. 10, OR circuit G # 22 includes:
This is a circuit for supplying the monitor input signal MI # 22 to the chip C # 22, and the chip C # 22 is adjacent to the chip C # 22.
12, C # 21, C # 23, and C # 32 from the monitor output signals MO # 12, MO # 21, MO # 23, and MO, respectively.
In response to # 32, the logical product of these four monitor output signals is calculated, and the result of the logical sum is input to chip C # 22 by monitor input signal M
Provided as I♯22.

The chip # 1 located around the wafer
OR circuit G # 11 provided corresponding to 1 will also be described. Chip C # 11 is such that the adjacent chip is chip C
There are only two chips, # 12 and C # 21. Therefore,
OR circuit G # 11 outputs monitor output signals MO # 12, MO # 12
The logical sum of the value output from $ 21 is applied to monitor input signal MI # 1
It is output as 1 and given to chip C # 11.

FIG. 11 is a flowchart showing how the test proceeds in each chip when a wafer test is performed in the second embodiment.

Referring to FIG. 11, first, in step S21, the test apparatus instructs each chip to execute a test mode, and the BIST circuit starts a self test. In step S22, each chip outputs a test monitor output signal as an H level at the start of the test. Then the self-test is started.

If the self-test has not been completed in step S23, the process proceeds to step S24, where the BIST circuit 2
06 monitors the temperature detection signal ET from the temperature detection circuit 208 to determine whether the chip temperature is abnormally high. In particular, when there is no abnormality in the temperature, the self test is continued as it is, and the process returns to step S23.

If a temperature abnormality has occurred, the process proceeds to step S25, and the BIST circuit 20 determines whether or not the test monitor input provided from the simultaneous measurement number adjustment adapter is under test.
6. If the test monitor input indicates that the test is being performed, the adjacent chip is also performing the self-test and is generating heat, so the process proceeds to step S26, and the self-test is temporarily stopped. The stop time at this time is defined as TB. After the elapse of the time TB, the process again proceeds to step S24, and it is determined whether the temperature abnormality has been resolved.

If it is determined in step S25 that the test monitor input does not indicate that the test is being performed, the process proceeds to step S27.
Proceed to. In this case, since none of the adjacent chips is in a state where the self-test is performed, the heat source is mainly the chip itself. In this case, the operation is temporarily stopped for a relatively short time TA with respect to the time TB. And
Proceeding to step S28, it is determined whether the temperature abnormality has been resolved. If the temperature abnormality has been resolved, step S
Proceeding to 23, the self-test will be continued again.

In step S28, if the temperature abnormality is not resolved, it is considered that some problem has occurred in the chip, so that the result of the self test is determined to be defective, and the test is terminated. Then, the process proceeds to step S29 to output a test result and set the test monitor output to the L level.

If it is detected in step S23 that the self test has been completed, the process also proceeds to step S29, where the test monitor output indicating the end of the test is set to the L level, and the result of the self test is output.

FIG. 12 is an operation waveform diagram for describing an operation when a wafer batch test is performed.

Referring to FIG. 3 and FIG.
From 0, a power supply and a clock signal CLK are supplied first.

Here, the device DUT1 and the device DU
It is assumed that T2 is an adjacent chip on the wafer. It is assumed that the device DUTn-1 and the device DUTn are adjacent chips on the wafer.

At time t1, a command signal C for setting a BIST command from test apparatus 220 is set.
MD is given.

At time t2, a self test is started simultaneously in each chip in response to a command. Accordingly, monitor output signals MO1 to MOn from each chip attain H level. In the temperature detection signal ET output from the temperature detection circuit of each chip, an L level indicating that the temperature is normal is output at the beginning of the self-test.

At time t3, a temperature abnormality is detected in device DUT2, and temperature detection signal ET goes high. In response, device DUT2 suspends the self test.

At time t5, when the temperature abnormality of the device DUT2 is resolved, in this case, the monitor output signal of the adjacent device DUT1 is at the H level and the test is being performed, so that a relatively long waiting time is required. At time t6 after time TB, the self-test is restarted.

Device DUTn-1, Device DUTn
With regard to (2), at time t4, a temperature abnormality occurs in the device DUTn, and the device DUTn suspends the self test.

At time t6, device DUTn-1
Of the device DUT
The monitor input signal Min supplied to n falls from the H level to the L level. At this time, the device DUT
FIG. 12 shows a case where the temperature abnormality of n has not been eliminated.

Then, when the temperature abnormality of the device is resolved at time t7, the device DUTn restarts the self test after a waiting time TA shorter than the waiting time TB.

At time t8, when the monitor output signals from all the devices go to the L level, the test result signals FS1 to FSn output from each device are taken in by the CPU 226 incorporated in the test apparatus 220. Then, the test result is stored in the storage unit 230.

The temperature detection circuit built in each chip is:
It is a circuit to stop the time (TA) when its own temperature drops when the temperature becomes abnormal due to self-heating, but when the adjacent chip is under test, Since the temperature is less likely to decrease due to heat than in the case of a single unit, loss of a test can be prevented by further increasing the stop time.

By performing the test with such a configuration, it is possible to take measures against heat generation when performing the wafer batch test, and it is possible to perform the test with a test apparatus having a relatively simple configuration.

The OR circuit provided in the simultaneous measurement number control adapter according to the second embodiment has a maximum of 4 inputs and monitors only the test status of the adjacent chip. By using an OR circuit that receives all test monitor outputs of eight or more chips surrounding the chip, control including a wider range of test conditions can be performed.

[Modification 1 of Embodiment 2] FIG. 13 is a block diagram for describing a configuration of a temperature detection circuit 300 used in place of temperature detection circuit 208 in Modification 1 of Embodiment 2. .

Referring to FIG. 13, temperature detecting circuit 300
Is a measuring current generating circuit 242 that generates a constant current for measuring temperature, a temperature detecting device 244 that receives a current of the measuring current generating circuit 242 and outputs a voltage corresponding to a temperature, and an output of the temperature detecting element 244. And an A / D conversion circuit 302 that converts an analog signal into a digital signal.

The A / D conversion circuit 302 outputs a temperature signal ET corresponding to the temperature of the chip to the CPU 248 included in the BIST circuit 206. The CPU 248 generates the temperature signal E
In response to T and the monitor input signal MI, the self-test is determined to be continued or temporarily stopped. The monitor output signal MO is activated until the self test is completed.

With this configuration, the BIS
Since the CPU 248 included in the T circuit 206 can directly receive the temperature data, the CPU 248 can easily change the temperature abnormality determination level by changing the setting condition. Therefore, it is easy to optimize the test, and the test time can be further reduced.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0088]

According to the semiconductor device of the present invention, the self-heating of the chips during the test in the wafer state can be appropriately controlled by temporarily suspending the test when the temperature is abnormal, so that the wafer batch test can be performed. become.

In the semiconductor device according to the second to fourth aspects, in addition to the effect of the semiconductor device according to the first aspect, the interruption time of the test is changed in accordance with the test situation of the surrounding chips on the wafer. Further, the test time of the wafer batch test can be reduced.

The semiconductor device according to the fifth aspect is the first aspect.
In addition to the effects of the semiconductor device, the temperature anomaly can be detected and the self-heating of the chip during the test in the wafer state can be controlled appropriately by temporarily suspending the test, so that the wafer batch test is possible become.

The semiconductor device according to the sixth aspect is the first aspect.
In addition to the effects of the semiconductor device described above, the self test circuit can recognize the temperature data and can easily change the temperature abnormality determination level, so that it is easy to optimize the test.

According to the semiconductor device test method of the present invention, the self-heating of the chips during the test in the wafer state can be appropriately controlled by temporarily suspending the test when the temperature is abnormal. It is possible.

The test method of the semiconductor device according to the present invention has the effect of the test method of the semiconductor device according to the present invention, and has a test interruption time in accordance with a test situation of a peripheral chip on a wafer. Changes, so
The test time of the wafer batch test can be reduced.

The test control device for a semiconductor device according to the ninth aspect transmits a test status of surrounding chips to each chip at the time of performing a wafer batch test.
It is possible to select the time for temporarily stopping the test when the temperature is abnormal, and the test time can be reduced.

The semiconductor device test control device according to the tenth to eleventh aspects has the effects of the semiconductor device test control device according to the ninth aspect, as well as recognizing a test state of an adjacent chip, and It can be provided to the chip as a monitor signal.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining measurement of a semiconductor device 100 according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a test flow according to the first embodiment;

FIG. 3 shows a semiconductor device 2 according to a second embodiment of the present invention.
It is a block diagram for explaining measurement of 00.

FIG. 4 is a block diagram illustrating a configuration of a temperature detection circuit shown in FIG. 3;

FIG. 5 is a diagram for explaining the arrangement of the interface unit 210 shown in FIG. 3 at the time of measurement.

FIG. 6 is a plan view showing a structure of a wafer connection portion 258.

7 is a cross-sectional view taken along a line AA in FIG.

8 is a simultaneous measurement number control adapter 212 shown in FIG.
FIG. 3 is a plan view for explaining the positions of the terminals of the device.

9 is a circuit diagram for explaining a circuit included in the simultaneous measurement number control adapter 212. FIG.

FIG. 10 is a circuit diagram showing a state in which OR circuits provided corresponding to respective chips of the simultaneous measurement number control adapter shown in FIGS. 8 and 9 are arranged.

FIG. 11 is a flowchart showing how a test proceeds in each chip when a wafer test is performed in the second embodiment.

FIG. 12 is an operation waveform diagram for explaining an operation when a wafer batch test is performed.

FIG. 13 is a block diagram illustrating a configuration of a temperature detection circuit 300 used in place of the temperature detection circuit 208 according to the first modification of the second embodiment.

FIG. 14 is a flowchart showing a flow of inspection of a conventional semiconductor device having a built-in BIST.

[Explanation of symbols]

100, 200 semiconductor device, DUT1 to DUTn device, 101, 202 memory circuit, 104, 206
BIST circuit, 106 diode element, 120, 2
20 test equipment, 122, 222 program power supply,
124, 224 input signal PG, 126, 226 CP
U, 128 DC measurement unit, 130, 230 storage unit, S
1 to S8, S21 to S29 step, 204 self-test circuit, 210 interface unit, 212 simultaneous measurement number control adapter, 242 measurement current generation circuit, 24
4 Temperature detection element, 245 Reference voltage generation circuit, 246
Voltage comparison circuit, 248 CPU, Ta {11 to Ta}
44, Tb # 11 to Tb # 44 terminal, G {11 to G}
44 OR circuit, 208,300 Temperature detection circuit, 30
2 A / D conversion circuit.

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Claims (11)

[Claims] 1. A semiconductor device formed on a main surface of a semiconductor substrate, an internal circuit, a temperature detection circuit for detecting a temperature of the semiconductor substrate, and a self-test circuit for performing a self-test on the internal circuit. A semiconductor device, wherein the self-test circuit suspends the self-test in accordance with an output of the temperature detection circuit. 2. The semiconductor device according to claim 1, further comprising: an input pad to which a monitor input signal according to a test execution status of another semiconductor device adjacent to the semiconductor device on the semiconductor wafer is provided, wherein the self-test circuit responds to the monitor input signal. The semiconductor device according to claim 1, wherein a period of the suspension is determined by using a command. 3. The self-test circuit sets the temporary stop period to a first time when the monitor input signal indicates that the other semiconductor device has completed a self-test. When the input signal indicates that the self-test of the other semiconductor device is not completed, the pause period is set to a second time longer than the first time;
The semiconductor device according to claim 2. 4. The semiconductor device according to claim 2, further comprising an output pad for outputting a test monitor output signal indicating to said another semiconductor device that said self-test has not been completed. 5. The temperature detection circuit, comprising: a measurement current generation circuit that generates a predetermined current; a temperature detection element that receives the predetermined current and generates a first potential according to a temperature of the semiconductor substrate; A reference voltage generation circuit that outputs a second potential having a small temperature dependency with respect to the first potential, which is a potential corresponding to an upper limit temperature at which the semiconductor device can operate; The semiconductor device according to claim 1, further comprising: a voltage comparison circuit that compares the second potential to detect a temperature abnormality. 6. The temperature detection circuit, comprising: a measurement current generation circuit that generates a predetermined current for measuring a temperature of the semiconductor substrate; and a first current detection circuit that receives the predetermined current and responds to the temperature of the semiconductor substrate. The semiconductor device according to claim 1, further comprising: a temperature detection element that generates a potential; and an A / D conversion circuit that performs an AD conversion on the first potential. 7. A temperature detection circuit formed on a main surface of a semiconductor substrate for detecting a temperature of the semiconductor substrate, and a self-test for performing a self-test and temporarily stopping the self-test according to an output of the temperature detection circuit. A control method for controlling semiconductor devices when testing a plurality of semiconductor devices in parallel when a plurality of semiconductor devices each including a test circuit are arranged on a semiconductor wafer, comprising: , A step of detecting an abnormality in the self-temperature during the test period, and a step of interrupting the self-test for a predetermined waiting time when the self-temperature is abnormal, the method for controlling a semiconductor device. 8. The semiconductor according to claim 7, further comprising: detecting a test execution status of peripheral chips on the semiconductor wafer; and switching the predetermined waiting time according to the test execution status. How to control the device. 9. A temperature detection circuit formed on a main surface of a semiconductor substrate and detecting a temperature of the semiconductor substrate, performing a self-test and responding to an output of the temperature detection circuit and a monitor input signal given from outside. When a plurality of semiconductor devices each including a self-test circuit for temporarily stopping the self-test are arranged on a semiconductor wafer, the plurality of semiconductor devices are tested in parallel by a measuring device. A test control device for performing operation control, wherein the second semiconductor device is provided corresponding to a first semiconductor device of the plurality of semiconductor devices and is close to the first semiconductor device on the semiconductor wafer. A test control device, comprising: a gate circuit that supplies the monitor input signal to the first semiconductor device according to the test execution status of the test. 10. Each of the semiconductor devices outputs a test monitor output signal indicating that the self-test has not been completed, and the gate circuit outputs the test monitor output signal output by the second semiconductor device. The test control device according to claim 9, wherein the test control device outputs the monitor input signal in response. 11. A main surface of the first semiconductor substrate has a quadrangular shape having first, second, third and fourth sides, and on the semiconductor wafer, the second semiconductor device is A third side, a fourth side, and a fifth side on the semiconductor wafer, the third side, the fourth side, and the fifth side being adjacent to the first semiconductor device with the first side as a boundary; The test monitor output signals output from the first to fifth semiconductor devices are respectively defined as first to fifth monitor output signals, the first to fifth monitor output signals being adjacent to the first semiconductor device with Each of the test monitor input signals supplied to the semiconductor device is first to fifth
11. The monitor circuit according to claim 10, wherein the gate circuit deactivates the first test monitor input signal when all of the second to fifth monitor output signals indicate a test end. Test control device as described.