JP2000339219A - Information processor, penalty time counting method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To count exact penalty time when an erroneous hit cache is caused. SOLUTION: A fact that a read request to be issued when the erroneous hit cache is caused by a processor 4 is received is notified to a read pending flag 3 and a read frequency counter 1 by a request receiving part 10, thus, count of the read frequency counter 1 is proceeded by 1 and the read pending flag 3 is set as '1'. When response data from a main storage part 5 is received via a system bus 41, the response data is supplied to the processor 4, reception of the response data is notified to the read pending flag 3 by a data transmitting part 20 and the lead pending flag 3 is set as 'zero'. Count of the penalty counter 2 is proceeded by one by every clock while the lead pending flag 3 shows '1'. The penalty time per one read request is counted by dividing a penalty counter value by a read frequency counter value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, a penalty time measuring method, and a recording medium. In addition, the present invention relates to an information processing apparatus for calculating an accurate penalty time, a penalty time measuring method, and a recording medium.

[0002]

2. Description of the Related Art Conventional methods for obtaining performance information of a computer system are disclosed in Japanese Patent Application Laid-Open Nos.
0-133902 and the like.

For example, in Japanese Patent Application Laid-Open No. Hei 10-133902, instructions of a program to be evaluated are fetched in the order of execution. If memory access is involved, a cache hit / miss is probabilistically determined from the reference address of the instruction and the cache hit rate parameter. If a cache hit occurs, the number of clocks required for cache access is obtained from the execution clock table and added to the counter. In the case of a cache miss, a page hit / miss is determined stochastically from the reference address of the instruction and the page hit rate parameter, and the number of clocks required for memory access is obtained from an execution clock table according to the page hit / miss. Is added to And so as to obtain the total number of execution clocks.

[0004]

However, the prior art has the following problems. That is,
The point is that the penalty time required for performance calculation cannot be calculated. The reason is that it has only a counter that counts the number of cache misses, and cannot calculate the penalty time required for performance calculation.

The present invention has been made in view of such a situation, and a counter for accumulating the number of cache misses and a response data after a read request issued when a cache miss is issued by a processor are issued. By providing a counter for accumulating the time until reception, it is possible to measure an accurate penalty time.

[0006]

According to a first aspect of the present invention, there is provided an information processing apparatus comprising a processor, a main storage device, and a cache memory, wherein the processor writes and reads data to and from the main storage device via the cache memory. In the information processing device that performs, a read request receiving means for receiving a read request issued when the processor has a cache miss, response data receiving means for receiving response data supplied from the main storage device in response to the read request, And a time accumulating means for accumulating a time from when the read request is received by the read request receiving means to when the response data is received by the response data receiving means. Further, a read number accumulating means for accumulating the number of times the read request has been received by the read request receiving means is further provided. The time until the data is received is integrated, and the time integrated by the time integrating means is
The penalty time can be measured by dividing by the number of times the read request integrated by the read number integrating means is received. Further, the time integrating means can be configured by a counter that counts in synchronization with a predetermined clock. Further, when the read request receiving means receives the read request, a predetermined flag is set, and when the response data is received by the response data receiving means, the flag is reset. The time can be measured while the flag is set in the flag holding means. The penalty time measuring method according to claim 5,
A penalty time measuring method for measuring a penalty time in an information processing apparatus including a processor, a main storage device, and a cache memory, in which the processor writes and reads data to and from the main storage device via the cache memory, A read request receiving step for receiving a read request issued when the processor makes a cache miss, a response data receiving step for receiving response data supplied from the main storage device in response to the read request, and a read request receiving step. And a time integration step of integrating the time from when the response data is received to when the response data is received in the response data receiving step. A recording medium according to a sixth aspect is characterized by recording a program capable of executing the penalty time measuring method according to the fifth aspect. In the information processing apparatus and the penalty time measuring method according to the present invention, and in the recording medium,
The processor receives a read request issued when a cache miss occurs, receives response data supplied from the main storage device in response to the read request, and receives time from when the read request is received until the response data is received. Is multiplied.

[0007]

FIG. 1 is a block diagram showing a configuration example of an embodiment of an information processing apparatus according to the present invention. As shown in FIG. 1, in the present embodiment, a processor 4 having a cache memory 6 and a read request issued when the processor 4 has a cache miss are received, and a value 1 is set to a read pending flag 3. With
A request receiving unit 10 for incrementing the count of the read number counter 1 by 1, a main memory 5 for storing various data,
According to the read request, the main memory 5 transfers the system bus 4
The data sending unit 20 receives the response data supplied via the "1" and sets the read pending flag 3 to a value "0", and synchronizes with a predetermined clock while the value "1" is set to the read pending flag 3. And a penalty counter 2 for incrementing the count by one for each clock.

When receiving a read request from the processor 4, the request receiving unit 10 notifies the read pending flag 3 and the read counter 1 that the read request has been issued.
The value 1 is set to the read pending flag 3 that has been notified that the read request has been issued, and the read number counter 1 advances the count by one.

[0009] When receiving the response data supplied from the main memory 5 via the system bus 41, the data transmitting section 20 notifies the read pending flag 3 that the response data has been received.
The value 0 is set in the lead pending flag 3 that has been notified that the response data has been received.

While the value 1 is set in the read pending flag 3, the penalty counter 2 increments the count by one every clock in synchronization with a predetermined clock. By dividing the count value of the read counter 1 by the count value of the penalty counter 2,
The penalty time can be calculated.

Next, the operation will be described. Now
Assume that processor 4 has made a cache miss. That is, it is assumed that data that does not exist in the cache memory 6 is referred to. At this time, the processor 4 stores the main memory 5
, A read request, which is an instruction requesting the supply of the data, is issued.

When receiving the instruction issued by the processor 4, the request receiving unit 10 starts decoding,
When it is confirmed that the instruction is a read request, a read request is issued to the main memory 5 and a read request is issued from the processor 4 to the read number counter 1 and the read pending flag 3. Notify. Specifically, for example, the read request issuance notification signal 11 is activated only for one clock, and the read number counter 1 and the read pending flag 3 are notified that the read request has been issued.

The read number counter 1 notified of the issuance of the read request by the read request issuance notification signal 11 advances the count by one. Also,
The value 1 is set to the read pending flag 3 which has been notified that the read request has been issued by the read request issuance notification signal 11.

Assume that the data transmission unit 20 receives response data from the main memory 5 via the system bus 41, for example, 10 clocks after the issuance of the read request by the processor 4. The data transmission unit 20 that has received the response data transmits the currently received response data to the processor 4 and notifies the read pending flag 3 that the response data has been received. Specifically, for example, the response data reception notification signal 21 is activated only for one clock, and the read pending flag 3 is notified that the response data has been received.

In response to the response data reception notification signal 21, the read pending flag 3 that has been notified that the response data has been received by the data transmission unit 20.
Is set to the value 0.

In this case, while the value 1 is set in the read pending flag 3, that is, from when the read request is issued by the processor 4 to when the response data is received by the data sending unit 20, During 10 clocks, a penalty counter addition notification is sent from the read pending flag 3 to the penalty counter 2. Specifically, for example, the penalty counter addition notification signal 31 is activated only for 10 clocks, and notifies the penalty counter 2 that the value 1 is set in the read pending flag 3.

The penalty counter 2 which is notified that the value 1 has been set to the read pending flag 3 by the penalty counter addition notification signal 31 advances the count by one every clock in synchronization with a predetermined clock. In this case, the count value (integrated value) of the penalty counter 2 is 10, and the penalty time can be measured as 10.

Then, by dividing the count value of the penalty counter 2 by the count value (integrated value) of the read number counter 1, the penalty time per one read request can be actually measured.

As described above, after a read request is issued by the processor 4 when a cache miss occurs,
By providing a counter (penalty counter 2) for accumulating the time until response data corresponding to the read request is received, an accurate penalty time can be measured.

As described above, according to the present embodiment, the following effects can be obtained. That is, an accurate penalty time can be measured. The reason for this is that a counter that accumulates the time from when a read request is issued to when response data is received is provided instead of a counter that conventionally accumulates the number of cache misses. .

The specific numerical values used in the above embodiment are examples, and the present invention is not limited to these numerical values.

[0022]

As described above, according to the information processing apparatus, the penalty time measuring method, and the recording medium of the present invention, a read request issued by a processor when a cache miss occurs is received, and the processor responds to the read request. Since response data supplied from the main storage device is received and the time from when the read request is received until the response data is received is added, the accurate penalty time should be measured when a cache miss occurs. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to an embodiment of the present invention.

[Explanation of symbols]

 1 Read Number Counter 2 Penalty Counter 3 Read Pending Flag 4 Processor 5 Main Memory 6 Cache Memory 10 Request Receiving Unit 11 Read Request Issuance Notification Signal 20 Data Transmission Unit 21 Response Data Reception Notification Signal 31 Penalty Counter Addition Notification Signal 41 System Bus

Claims (6)

[Claims] 1. An information processing apparatus comprising a processor, a main storage device, and a cache memory, wherein the processor writes and reads data to and from the main storage device via the cache memory. A read request receiving unit that receives a read request issued at the time, a response data receiving unit that receives response data supplied from the main storage device in response to the read request, and the read request is received by the read request receiving unit. An information processing apparatus comprising: a time integrating unit that integrates a time period from when the response data is received to when the response data is received by the response data receiving unit. 2. The apparatus according to claim 1, further comprising: a read number accumulating means for accumulating the number of times the read request has been received by the read request receiving means, wherein the time accumulating means is provided when the read request is received by the read request receiving means. From the above, the time until the response data is received by the response data receiving means is integrated, and the time integrated by the time integrating means is calculated by the number of times the read request integrated by the read number integrating means is received. The information processing apparatus according to claim 1, wherein a penalty time is measured by dividing. 3. The information processing apparatus according to claim 1, wherein said time integrating means comprises a counter that counts in synchronization with a predetermined clock. 4. A flag holding unit that sets a predetermined flag when the read request receiving unit receives the read request, and resets the flag when the response data is received by the response data receiving unit. The information processing apparatus according to claim 1, wherein the time accumulation unit measures time while the flag is set in the flag holding unit. 5. An information processing apparatus including a processor, a main storage device, and a cache memory, wherein the processor writes and reads data to and from the main storage device via the cache memory, and measures a penalty time. A penalty time measuring method, comprising: a read request receiving step of receiving a read request issued when the processor makes a cache miss; and a response data receiving response data supplied from the main storage device in response to the read request. A receiving step; and a time integration section for integrating the time from when the read request is received in the read request receiving step to when the response data is received in the response data receiving step. A penalty time measuring method, comprising: 6. A recording medium on which a program capable of executing the penalty time measuring method according to claim 5 is recorded.