JP2000332030A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase of the longitudinal size a chip, while reducing source inductance. SOLUTION: First and second source electrodes 11 and 12 are alternately arranged so that the broad sections of the first source electrodes 11 in each of which via holes 41 are formed periodically, and the broad sections of the second source electrodes in each of which via holes 42 are formed periodically may be arranged alternately. As a result, the longitudinal size of a chip can be reduced, by making the arranging pitch of the source electrodes shorter than that in an ordinary source island via hole structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor, and more particularly to a high-power field-effect transistor having a comb-shaped gate electrode structure.

[0002]

2. Description of the Related Art In a high output field effect transistor,
When designing a device with a larger output, it is necessary to increase the total gate width. As a countermeasure, it is possible to increase the finger length of the comb. However, since the length of the source electrode is also increased at the same time, there is a problem that the source inductance increases and the gain decreases. As a method to reduce the source inductance when the gate finger length is extended,
A source island via hole structure has been adopted in which each source electrode is directly connected to a plated heat sink (PHS) on the back surface through a via hole.

FIG. 4 is a plan view schematically showing a basic cell structure of a conventional field effect transistor having a source island via structure, and FIG.
It is a typical sectional view of the B 'part.

Referring to FIG. 4 and FIG.
1, gate electrodes 121 and drain electrodes 131 are alternately arranged. In addition, the gate electrode 121 is connected to the gate pad 105 via the gate bus bar 104, the drain electrode 131 is drawn out in the opposite direction to the gate pad 105 and connected to the drain pad 106, and the source electrode 111 covers the entire substrate immediately below. It is connected to the PHS 103 on the back via a via hole 141 formed therethrough. The ohmic electrode is rectangular like a normal comb gate field effect transistor.

FIG. 6 is a schematic plan view of a multi-cell structure field effect transistor in which four basic cells 110 of FIG. 4 having a conventional source island via structure are arranged.

[0006]

In a conventional field-effect transistor having a source-island-via-hole structure, as shown in FIGS. Since "via hole size (Hw1) + process margin (α)" is required as Sw1, there is a problem that the pitch of the source electrodes is increased, the longitudinal direction of the chip is increased, and the chip size is increased.

An object of the present invention is to provide a high-output field effect transistor in which the source inductance is reduced and the increase in the longitudinal direction of the chip is suppressed by devising the shape and arrangement of via holes provided in the source electrode portion. It is.

[0008]

According to the present invention, there is provided a field effect transistor having a finger-like gate electrode in which a longitudinal direction for selectively covering an active region formed on one main surface of a substrate is a first direction. A plurality of sets of source electrodes and finger-like drain electrodes respectively covering the active regions with a finger-like gate electrode interposed therebetween are arranged in parallel to share the adjacent source electrode and finger-like drain electrode, and each of the source electrodes Has a wide portion in which a via hole that penetrates the substrate periodically in a first direction is formed, and the wide portion of the adjacent source electrode further extends with respect to a second direction perpendicular to the first direction. It has a plurality of unit cells arranged alternately so as not to be on the same straight line.

At this time, it is desirable that each source electrode is connected via a via hole to an electrode serving also as a PHS formed on the back surface of the substrate.

The substrate is a GaAs substrate or InP.
It can be a substrate.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view schematically showing a basic cell structure of a field effect transistor according to one embodiment of the present invention.
FIG. 2 is a sectional view schematically showing a section taken along the line AA ′ of FIG.

Referring to FIGS. 1 and 2, a basic cell 10 of a field-effect transistor according to this embodiment includes a first source electrode 11 or a second source electrode 12, and a finger-shaped gate electrode 21 (hereinafter referred to as a gate electrode 21). The drain electrodes 31 (hereinafter, referred to as drain electrodes 31) are alternately arranged, and the first source electrodes 11 and the second source electrodes are alternately arranged with respect to the source electrodes. The gate electrode 21 is connected to the gate pad 5 via the gate bus bar 4, the drain electrode 31 is drawn out in the opposite direction to the gate pad 5 and connected to the drain pad 6, and the first source electrode 11 and the second The source electrode 12 has octagonal via holes 41 and 4 formed in portions periodically widened so as to penetrate the back surface of the substrate.
2 is connected to the PHS 3 on the back side. Further, when the longitudinal direction of each electrode is a first direction and the arrangement direction of each electrode perpendicular to the first direction is a second direction, the wide portion of the first source electrode 11 in which the via hole 41 is formed and the via hole The wide portion of the second source electrode 12 on which the 42 is formed is periodically arranged so as not to be on a straight line in the second direction. More specifically, the second source electrode 1 is located between the wide portions adjacent to the first source electrode 11.
The arrangement interval and the size of the wide portions are determined so that the two wide portions are included.

Further, the field effect transistor of the present invention comprises:
For example, after forming an active layer (not shown) on a semi-insulating GaAs substrate 1 by a known method, a metal such as Au, Ge, Ni or the like is deposited and alloyed to form a source and drain ohmic electrode (see FIG. (Not shown), and a metal such as WSi is sputtered to form a gate bus bar 4 and a gate pad 5.
And a gate electrode 21, and a drain electrode lead-out portion and a drain electrode 31 are formed by Au plating.

Further, crystal dry etching is performed from the back surface of the semi-insulating GaAs substrate 1, and the back surface is gold-plated to fill the formed via hole 41 to form PHS3.
A source island via hole structure is formed. It goes without saying that the GaAs substrate may be an InP substrate.

In this embodiment, the via holes 41
Has been described as an octagon, but the shape may be a square, a hexagon, or a circle.

It is needless to say that a desired field-effect transistor can be realized by forming the required number of basic cells 10 of FIG. 1 in accordance with a desired output. For example, FIG. 3 is a schematic plan view of a field-effect transistor having a structure in which four basic cells of FIG. 1 are arranged.

As described above, in the field effect transistor of the present invention, the source inductance is reduced by the source island via hole structure periodically provided in each source electrode, and the gain decreases when the finger length is increased. The effective source electrode width can be reduced by arranging the wide portions where via holes are periodically provided in each source electrode so that they are alternately arranged between adjacent source electrodes while suppressing the source electrode. -The gate pitch can be made shorter than in the via hole structure, and the dimension in the chip longitudinal direction can be shortened.

In other words, since the number of fingers can be increased even with the same electrical characteristics and chip size, the total gate width can be increased, and a higher output field effect transistor can be realized.

The effect of reducing the size in the longitudinal direction of the chip will be specifically described with reference to FIG.

FIG. 7A shows a via hole width (Hw), a source electrode wide portion (Sw), a source electrode arrangement pitch (Sp), and one of the adjacent source electrodes in the field effect transistor of the present invention. FIG. 7B is a plan view schematically showing the penetration amount (L) of the other electrode disposed between the wide portions and the internal dimension (W0) between adjacent source electrodes, and FIG. The via hole width (Hw1) and the source electrode width (Sw)
1) is a plan view schematically showing a source electrode arrangement pitch (Sp1), and an inner dimension (W1) between adjacent source electrodes.
For comparison, the gate length, the width of the drain electrode, the process margin (α), and the like are common to the field-effect transistor of the present invention and the conventional field-effect transistor, and Hw = Hw1, Sw = Hw + α, Sw1 = Hw1
+ Α. Then, W0 = W1, Sp = W0 + Sw
−L, Sp1 = W1 + Sw1, Sp1−Sp = L, and the source arrangement pitch can be reduced by “L” as compared with the conventional example using the source island / via hole structure, and the dimension in the chip longitudinal direction is correspondingly reduced. it can.

[0022]

As described above, in the field effect transistor of the present invention, the source inductance is reduced by the source island via hole structure, and the reduction in gain when the finger length is increased is suppressed.
By arranging the wide portions where via holes are periodically provided in each source electrode so that they are alternately arranged between adjacent source electrodes, the pitch of the source electrodes is shorter than that of the normal source island via hole structure, and the The effect that the dimension in the longitudinal direction can be shortened is obtained.

In other words, the field effect transistor of the present invention can increase the number of fingers and increase the total gate width even with the same electrical characteristics and chip size.
An effect that a larger output can be obtained can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a structure of a basic cell of a field-effect transistor according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA ′ of FIG.

FIG. 3 is a schematic plan view of a field effect transistor having a multi-cell structure in which four basic cells of FIG. 1 are arranged.

FIG. 4 is a plan view schematically showing a structure of a basic cell of a conventional field effect transistor having a source island via hole.

FIG. 5 is a sectional view schematically showing a section taken along line BB ′ of FIG. 4;

6 is a schematic plan view of a field effect transistor having a multi-cell structure in which four basic cells of FIG. 4 are arranged.

7A and 7B are diagrams for explaining the effect of reducing the size in the chip longitudinal direction. FIG. 7A shows the via hole width (Hw) and the source electrode wide portion (Sw) of the field effect transistor of the present invention.
), The source electrode array pitch (Sp), the amount of entry (L) of the wide portion of the other electrode located between the wide portions of one of the adjacent source electrodes, and the internal dimension between the adjacent source electrodes (L). W0) is a plan view schematically showing FIG. 7 (b). FIG. 7 (b) shows a conventional field effect transistor having a via hole width dimension (Hw1), a source electrode width dimension (Sw1), a source electrode array pitch (Sp1), and an adjacent one. FIG. 4 is a plan view schematically showing the internal dimension (W1) between source electrodes.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GaAs substrate 3,103 PHS 4,104 Gate bus bar 5,105 Gate pad 6,106 Drain pad 10,110 Basic cell 11 First source electrode 12 Second source electrode 21 Finger gate electrode 31 Finger drain electrode 41 , 42, 141 Via hole 101 Substrate 111 Source electrode 121 Gate electrode 131 Drain electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA04 AA05 BB05 BB09 BB28 CC01 FF06 FF40 GG12 GG18 HH14 5F033 GG02 HH07 HH13 JJ13 KK13 MM04 MM30 NN16 PP27 VV06 VV07 XX03 XX08 5F102 FA01 GB02 GC03 GT05 GV03 HC11 HC30

Claims (6)

[Claims] A first direction in which a longitudinal direction for selectively covering an active region formed on one main surface portion of a substrate is a finger-like gate electrode, and the active region is sandwiched between the finger-like gate electrodes. A plurality of sets of a source electrode and a finger-like drain electrode to be coated are arranged so as to share a plurality of the source electrodes and the finger-like drain electrodes adjacent to each other in parallel, and each of the source electrodes periodically extends in the first direction. A wide portion in which a via hole penetrating the substrate is formed, and the wide portions of the adjacent source electrodes are alternately arranged so as not to be on the same straight line in a second direction perpendicular to the first direction. A field-effect transistor comprising a plurality of unit cells arranged. 2. The field effect transistor according to claim 1, wherein the source electrode is connected to an electrode formed on a back surface opposite to one main surface of the substrate via a via hole. 3. The method according to claim 1, wherein the shape of the via hole is square, hexagonal,
3. The field-effect transistor according to claim 1, wherein the field-effect transistor is octagonal or circular. 4. A plurality of source electrodes disposed with a finger-shaped gate electrode interposed therebetween are independently formed on one main surface of the substrate, and are formed on the back surface opposite to the one main surface of the substrate and each via. 4. The field-effect transistor according to claim 1, wherein all the source electrodes are connected in common by connecting via a hole. 5. 5. The field effect transistor according to claim 1, wherein the substrate is one of a GaAs substrate and an InP substrate. 6. An electrode formed on the entire back surface facing one main surface of the substrate is a plated heat sink (PHS).
The field-effect transistor according to any one of claims 1 to 5, wherein