JP2000331307A - Write-in compensating method in magnetic recording and magnetic recording device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve recording density further in a magnetic recording device using a MTR (3) code limiting continuous magnetization inversion to three times of the maximum. SOLUTION: Write-in compensation is performed at the time of recording data. A normal write-in pulse generates the write-in pulse lagging for a reference clock by a WPC1. For a pattern in which magnetization inversion is continued three times, in the first magnetization inversion, the write-in pulse is generated with the same timing as the reference clock, in the second, it is generated lagging by the WPC1, in the third, it is generated lagging by a WPC2. Consequently, an interval of the magnetization inversion in the pattern in which the magnetization inversion is continued three times is made wider, amplitude of a reproduced signal in the recording pattern is expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing method for a magnetic recording / reproducing apparatus, and more particularly to a pre-compensation method for writing data in a magnetic recording / reproducing apparatus using a PRML system.

[0002]

2. Description of the Related Art Conventionally, in a magnetic recording device represented by a hard disk device, various techniques have been devised along with an improvement in recording density. In particular, in the recording / reproducing method, the PRML channel method applying the technology in the communication field has been generally used, and thereafter, the extended PRML method has been put to practical use in order to further improve the recording density. Therefore, first, the PRML channel system will be briefly described.

The partial response (PR) reproduces data while compressing a necessary signal band by positively utilizing intersymbol interference (interference between reproduced signals corresponding to bits recorded adjacent to each other). Is the way. Depending on how the intersymbol interference occurs at this time, it can be further classified into a plurality of classes, but the most mainstream is a class 4 partial response "PR4". The Viterbi decoding method (ML) is a kind of a so-called maximum likelihood sequence estimation method, and effectively utilizes a rule of intersymbol interference of a reproduced waveform to reproduce data based on signal amplitude information over a plurality of times. Do. For this purpose, a synchronous clock synchronized with the reproduced waveform obtained by the magnetic head is generated, and the reproduced waveform itself is sampled by this clock and converted into amplitude information. After that, by performing appropriate waveform equalization, it is converted into the response waveform of the predetermined partial response,
The Viterbi decoding unit uses the past and present sample data and outputs the most probable data series as reproduction data. A method that combines the above partial response method and the Viterbi decoding method (maximum likelihood decoding) is called a PRML channel method.

A specific processing procedure in the magnetic disk device will be described with reference to FIG. In this figure, the host I / F7
01 is a part for controlling data transfer between the magnetic disk device and a host computer such as a personal computer. The encoding circuit 702 modulates the user data to be recorded in accordance with a predetermined recording and converts (encodes) the data into data that can be recorded on a medium. The write compensation circuit 703
Correct the data recording timing according to the characteristics of 05. The recording / reproducing amplifier 704 reads the magnetization of the recording medium and the magnetization information on the recording medium via a recording head as an electric signal. This read signal is subjected to appropriate band limitation in the data processing circuit 706 and then sampled by a synchronizing signal generated from the signal itself, converted into amplitude information, and a most probable data sequence is obtained based on the amplitude information. . The obtained data sequence is subjected to demodulation (decoding) in the decoding circuit 707 in the reverse order of the encoding circuit 702, and the original recording data is restored. The magnetic disk drive records and reproduces data according to the above procedure.

[0005] As the latest technology of the PRML system, there are methods disclosed in Japanese Patent Application Nos. 10-043186 and 10-120163. In this method, when encoding data to be recorded, the number of consecutive “1” s included in the converted code is limited to three or less. Since the recording is performed such that the converted code “1” corresponds to the magnetization reversal on the magnetic medium, continuous magnetization reversal is limited to three times or less, the signal band can be effectively used, and the recording density can be reduced. Can be improved.

On the other hand, as the recording density increases, a nonlinear waveform shift (NLBS: Non Li
ner bit shift) has been a barrier to performance improvement.
As described above, in the PRML method, a waveform read from a recording medium is sampled by a separately generated synchronous clock, and recorded data is reproduced based on the amplitude value. Therefore, NL
Non-linear waveform distortion typified by BS causes an error in amplitude value, which is a hindrance factor for improving recording density. As a technique for solving this problem, there is a method disclosed in Japanese Patent Application Laid-Open No. H5-282613. According to this method, the generated NLBS
Is measured in advance, and the data write (magnetization reversal) timing is delicately changed so that the influence is minimized. As a specific example, when data to be subjected to magnetization reversal are continuous, an operation of slightly delaying the timing of the second or subsequent magnetization reversal and extending the magnetization reversal interval is performed. When the magnetization reversal is repeated three or more times, the interval between the first magnetization reversal and the second magnetization reversal is slightly widened, and the magnetization reversal after the third is performed at the same magnetization reversal interval as the normal bit interval. These operations will be described with reference to FIG. In this figure, a reference clock is a master clock serving as a time reference for data writing. The write data is a signal from the encoding circuit 702 in FIG.

Here, it is assumed that the NRZI recording system in which the write waveform is inverted (the magnetization is inverted) when the write data is "1". The post-compensation write pulse is the result of the write compensation, and this signal causes magnetization as shown in the last write waveform. Time (1) in FIG. 3 is a single magnetization reversal, and a write pulse is generated at the same timing as the write data. Similarly, at time (3), a write pulse is generated at the same timing as the write data. At time (4), the magnetization is reversed at the immediately preceding time (3),
Generate write pulse delayed by WPC0 from reference clock
(Writing compensation). As a result, the magnetization reversal from time (3) to time (4) is slightly longer than the cycle of the reference clock. Time (5)
Since the magnetization is reversed at the immediately preceding time (4), the write pulse is generated (write compensation) with a delay of WPC0 from the reference clock. As a result, the magnetization reversal from time (4) to time (5) has the same interval as the cycle of the reference clock. In this way,
The effect of nonlinear waveform shift can be reduced.

[0008]

The improvement of the recording density in the magnetic recording apparatus does not stop, and the combination of the above techniques is not sufficient. In particular, Japanese Patent Application No. 10-043186
In the encoding method shown in (1), since the encoding rate is emphasized, there are three consecutive magnetization reversals, and this must allow a read error with a short (probable) Euclidean distance. In particular, the re-extended partial response method (E
In magnetic disk drives using (EPRML), magnetization reversal is continuous.
Most of the determination errors occur in the recording pattern that occurs three times, which is a hindrance to the improvement of the recording density.

SUMMARY OF THE INVENTION An object of the present invention is to provide a write compensation method capable of further improving the recording density in a magnetic recording apparatus using an MTR (3) code for limiting the number of consecutive magnetization reversals to a maximum of three. is there.

[0010]

In order to solve the above-mentioned problems, the present invention uses an MTR (3) code for limiting the number of continuous magnetization reversals to a maximum of three times. Further, in the case of a recording pattern in which the magnetization reversal is repeated three times, the amplitude of the reproduced waveform is expanded by slightly widening the interval between the write pulses, and the reading error in this recording pattern is reduced. To summarize this relationship, control is performed as shown in FIG. In this figure, (k-2), (k-1), k, (k + 1),
(k + 2) indicates the time, and the time k is the current time of interest. “0” and “1” in the figure represent recording codes, and it is assumed that NRZI recording in which magnetization reversal is performed in the case of “1”. “*” Is an arbitrary recording code, and may be either “0” or “1”. The case (A) in the figure corresponds to JP-A-5-282613.
In this method, magnetization reversal is generated at the current time, and “1” is also obtained at (k−1) one time before, and two times before
If it is “0” at (k-2) and “0” at (k + 1) one time later,
The magnetization reversal at this time k is slightly delayed. Similarly, in the case of (B), that is, “0” at time (k−1), time k,
In the case of “1” at (k + 1) and (k + 2), the magnetization reversal at time k is slightly advanced. The case of (C), ie, time (k-2),
If “1” at (k-1), (k) and “0” at time (k + 1), time k
Slightly delays the magnetization reversal at. In cases other than (A) to (C), the magnetization reversal is performed at a timing based on the reference clock. By performing such write compensation, the magnetization reversal interval in a pattern in which magnetization reversal is repeated three times is widened, intersymbol interference is reduced, and the signal amplitude of the reproduced waveform is increased. For this reason, the error occurrence rate in this pattern is reduced, and the overall reproduction performance, that is, the recording density can be improved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. As described above, in the present invention, it is assumed that encoding is performed by the MTR (3) code in which the number of consecutive magnetization reversals is three at the maximum. FIG. 8 is a diagram showing one embodiment of the write compensation circuit according to the present invention. In this figure, reference numeral 801 denotes a pattern determination circuit. Code 802,806,8
07,808,809 are AND circuits. Reference numeral 810 is a logical sum. Reference numeral 803 denotes a delay circuit, which outputs a signal delayed by a delay time WPC1 set separately from the input signal. Sign
A delay circuit 804 outputs a signal delayed by a delay time WPC2 set separately from the input signal. Reference numeral 805 denotes a delay circuit, which is a delay time separately set for an input signal.
Outputs a signal delayed by WPC3. This circuit performs an operation of appropriately delaying a write pulse with respect to output data of the encoding circuit 702 based on a selection result of the pattern determination circuit 801 and then outputting the write pulse to the recording / reproducing amplifier 704. The operation of the pattern determination circuit 801 will be described with reference to FIG. In this figure, (k-2), (k-1), k, (k + 1), and (k + 2) indicate time, and time k is the current data of interest. “0” in the figure,
“1” indicates a recording code, and it is assumed that NRZI recording in which magnetization reversal is performed in the case of “1”. “*” Is an arbitrary recording code, and may be either “0” or “1”. In an actual circuit, it is difficult to output the input write pulse earlier. Therefore, the delay of WPC1 is generated even in the normal case where write compensation is not performed. That is, in a recording pattern that is not the target of write compensation (normal time), Sel1 is activated in the pattern determination circuit, and a write pulse delayed by WPC1 is generated. In the case of (B) where it is desired to advance the write timing, Sel0 is activated, and in this case, the write pulse is output without delay, so that the write timing is advanced by WPC1 as compared with the normal case. In the last case (C) in which the magnetization reversal is repeated three times, Sel2 is activated and a write pulse delayed by WPC2 is generated. Since WPC2 is set to be a value larger than WPC1, the write timing is delayed by (WPC2-WPC1) than usual. Finally, in the conventional case (A), Sel3 becomes active and generates a write pulse delayed by WPC3. Since this WPC3 is set to be a value larger than WPC1, the write timing is delayed by (WPC3-WPC1) more than usual. FIGS. 1 and 2 show the relationship between the recording pattern and the write pulse. In this figure, each signal waveform is a reference clock,
5 shows recording data from an encoding circuit 702, an output of a write compensation circuit 703, and a write waveform to a recording medium 705. Time 1
Is normal writing, and the pattern judgment circuit 801
Select Then, the write pulse is output with a delay of WPC1 with respect to the reference clock. This is a case where the times (3) to (5) are subjected to three consecutive magnetization reversals. Time (3) is the first magnetization reversal for three consecutive times, and the pattern determination circuit 801 at this time is
Is Sel0. At this time, a write pulse is output at the same timing as the reference clock. Time (4) is the second magnetization reversal, and the output of the pattern determination circuit 801 at this time is Sel1. In this case, a write pulse is output at a timing delayed by WPC1 from the reference clock. That is, the magnetization reversal interval from time (3) to (4) is equal to the normal period T
+ (WPC1) interval. Time (5) is the third magnetization reversal, and the output of the pattern determination circuit 801 at this time is Sel2. In this case, a write pulse is output at a timing delayed by WPC2 from the reference clock. That is, time
The magnetization reversal interval from (4) to (5) is equal to the normal cycle T + (WPC2-
This is the interval of WPC1). Since WPC2 is set to be larger than WPC1, the pulse interval is wider than a normal pulse interval. Times (7) and (8) in FIG. 2 are the cases where the magnetization reversal continues only twice. Of these, the time (7) is the first magnetization reversal, so the output of the pattern determination circuit 801 is Sel1. Therefore, the write pulse is output at a timing delayed by WPC1 from the reference clock. Time
In (8), the output of the pattern determination circuit 801 becomes Sel3, and the write pulse is output at a timing delayed by WPC3 from the reference clock. As a result, the magnetization reversal interval from the time (7) to the time (8) becomes a normal cycle T + (WPC3-WPC1).

Next, a second embodiment which is a simplification of the first embodiment will be described with reference to the drawings. FIG. 9 is a diagram illustrating a write compensation circuit according to the second embodiment. In this figure, reference numeral 801 denotes a pattern determination circuit. Code 802,80
6,807,808 are AND circuits. Reference numeral 810 is a logical sum. Reference numeral 803 denotes a delay circuit, which outputs a signal delayed by a delay time WPC1 set separately from the input signal. Sign
A delay circuit 804 outputs a signal delayed by a delay time WPC2 set separately from the input signal. The main difference between the first embodiment and the second embodiment is the operation of the pattern determination circuit shown in FIG. The pattern determination for the pattern (A) in which the magnetization reversal is continued only twice is set to Sel2, and the write delay in the first embodiment was WPC3, which was the same as FIG. 5 (C).
And By such a change, the delay circuit 805 and the logical product 809 required in the first embodiment become unnecessary, and the pattern determination circuit 801 can be realized with a simple configuration. Of course, in this case, since the delay time of the pattern of (A) and the pattern of (C) are the same, there is a possibility that the NLTS cannot be sufficiently corrected. But in many cases, WPC2 and WP
Since C3 is set to a very close value, the circuit scale can be reduced by allowing some error.

[0013]

FIG. 10 shows the result of the effect of the present invention obtained by a computer using a simulated waveform. In this figure, the second
In the case of the embodiment, the effect of the present invention is shown. In this figure, the horizontal axis shows the ratio of the delay time WPC2 to the period T of the reference clock, and the vertical axis shows the error occurrence rate under certain conditions. Here, WPC1 was set to half the value of WPC2. As can be seen from this figure, by setting an appropriate WPC value, the error rate can be reduced to almost one-fifth compared to the case without write compensation, and the recording density can be improved by that much. .

As described above, according to the present invention, in a magnetic recording apparatus using an MTR (3) code that limits the number of continuous magnetization reversals to a maximum of three times, a determination is made based on a recording pattern that undergoes three consecutive magnetization reversals. Since errors can be reduced, it is possible to further improve the recording density. By devising a write compensation method at this time, it is possible to minimize an increase in circuit scale.

[Brief description of the drawings]

FIG. 1 is a diagram (1) showing a write compensation waveform according to the present invention.

FIG. 2 is a diagram (2) showing a write compensation waveform according to the present invention.

FIG. 3 is a diagram showing a conventional write compensation waveform.

FIG. 4 is a diagram showing write compensation control according to the present invention.

FIG. 5 is a diagram showing the operation of the pattern determination circuit.

FIG. 6 is a diagram illustrating the operation of the pattern determination circuit according to the second embodiment.

FIG. 7 is a diagram showing a configuration of a magnetic recording / reproducing circuit.

FIG. 8 is a diagram showing a write compensation circuit according to the present invention.

FIG. 9 is a diagram illustrating a write compensation circuit according to a second embodiment.

FIG. 10 is a diagram showing an effect of the present invention.

[Explanation of symbols]

701: Host I / F, 702: Encoding circuit, 703
.., Write compensation circuit, 704, recording / reproducing amplifier, 705
Recording medium, 706: data processing circuit, 707: decoding circuit, 801: pattern determination circuit, 802, 80
6, 807, 808, 809: AND circuit; 810: OR circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tatsuya Hirai 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside System Development Laboratory, Hitachi, Ltd. (72) Inventor Hirofumi Ide 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 Within Hitachi, Ltd. Semiconductor Group (72) Inventor Takashi Nara 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within Hitachi, Ltd. Semiconductor Group (72) Inventor Tatsuya Komatsu Upper, Kodaira-shi, Tokyo 5-20-1, Mizumotocho Hitachi Semiconductor Co., Ltd. (72) Inventor Terumi Takashi 2880 Kozu, Odawara-shi, Kanagawa Prefecture F-term in Storage Systems Division, Hitachi, Ltd. 5D031 AA04 CC02 HH13

Claims (4)

[Claims] In a magnetic recording apparatus using an encoding rule for limiting continuous magnetization reversal to a maximum of three times, when a recording pattern has three consecutive magnetization reversals, the first magnetization reversal is performed by another magnetization reversal. A magnetic recording apparatus, wherein correction is performed at the time of data recording so that the third magnetization reversal is earlier than the timing and later than the timing of the other magnetization reversals. 2. The magnetic recording apparatus according to claim 1, wherein the recording / reproducing method for reproducing the information recorded on the magnetic recording apparatus uses an EPRML which is a re-extended partial response method. . 3. A signal processing circuit for a magnetic recording device using an encoding rule for limiting continuous magnetization reversal to a maximum of three times.
The first magnetization reversal is earlier than other magnetization reversal timings,
A signal processing circuit for correcting a data write signal so that a third magnetization reversal is delayed from another magnetization reversal timing. 4. The signal processing circuit according to claim 3, wherein the signal processing method is a re-extended partial response method.
A signal processing circuit using EEPRML.