JP2000330936A - Bus controller and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the bus controller which is adaptive to various timing of input/output devices and efficiently performs bus control. SOLUTION: An access timing selecting circuit 12 specifies an input/output device to gain bus access with, for example, an address signal 24, a selection control signal 25, etc., and outputs an access timing register select signal 21. An access timing prescribing register group 11 outputs as a timing specification signal 22 a corresponding set value in a group of set values prescribing access timing previously stored corresponding to various input/output devices including memories according to an access timing register select signal 21. A bus timing generation sequencer 13 generates basic bus timing according to a group of set values prescribing access timing received as a timing specification signal 22, generates a control signal on the basis of it, and outputs it to a bus control line 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device for accessing a memory or other input / output devices connected to a bus in accordance with a bus cycle, and a semiconductor device equipped with such a bus control device. It is.

[0002]

2. Description of the Related Art Conventionally, a microprocessor having a built-in memory and an input / output device and connected by an internal bus has been known. There is also known a system in which a memory is connected to an external bus as an external storage means, or another input / output device is connected to the external bus, and a microprocessor or an external bus master accesses the system.

However, in a memory or an input / output device,
The specifications for the access timing differ depending on the type. Therefore, when configuring the system, the specifications of the access timing may change depending on the memory and the input / output device used. For example, a high-speed read-only memory (ROM) is used to improve the processing speed of an execution program to be stored, and a medium-speed ROM is used for storing characters in a printer. For a large-capacity buffer, a random access memory (RAM) is used to increase the capacity, and a high-speed synchronous dynamic random access memory (SDRAM) is used so as not to hinder processing by a high-speed processor. Or a high-speed static random access memory (SRAM) is used to configure a cache memory. Furthermore, for input / output devices, setting of transfer speed,
There is a difference in processing speed depending on the type of interface. For example, there are a wide variety of devices, from relatively low-speed serial interface and parallel interface control devices to high-speed net control devices and hard disk control devices. As described above, in order to control the memory and the input / output device, various types of timing control are required.

Generally, timing control of a memory or an input / output device is performed by an external bus master such as a microprocessor or a direct memory access controller (DMAC) which can be a bus master, or a bus control for controlling an internal bus of the processor. Department. In these methods, as a method for performing various kinds of timing control for the memory and the input / output device as described above, a method of controlling by inputting a wait request signal or a ready signal indicating a state from an access target is known. An example of a microprocessor using such a method is described in, for example, “Nikkei Electronics”, 1989, 4.3 (No. 470) P.
199-209. This microprocessor has a memory access control circuit, determines an access target memory based on address information output from the microprocessor, and inputs an access preparation state signal of the access target memory as a microprocessor ready signal. Then, the access time of the memory is extended until the access preparation state signal indicates the access preparation state, and the bus cycle width is changed. Thereby, it is possible to access various memories that require various access controls.

However, in this technique, the memory access control circuit must determine each memory to be accessed and notify an access preparation state signal before the microprocessor executes the first access time extension cycle. Therefore, the speed of the memory and the memory access control circuit must be increased in accordance with the increase in the speed of the microprocessor. As a result, the system cost may increase, or the speed of the microprocessor may increase in order to construct an inexpensive system. There is a problem that conversion is hindered.

In order to solve such a problem, it has been considered to have a bus cycle setting register inside and extend the bus cycle according to the set value. Further, there is also known a method of controlling a bus cycle by applying a method of inputting a wait request signal of a bus cycle based on a ready signal and extending the bus cycle by the above-described bus cycle setting register setting value. In fact, there are known microprocessors that perform such bus cycle control. Further, a method of controlling a plurality of bus cycles by dividing an address space, making different bus cycles correspond to each divided address space, and generating a corresponding bus cycle based on the address is known. I have.

For example, the bus control unit of the data processing device described in Japanese Patent Application Laid-Open No. Hei 5-307519 has a bus cycle setting register inside and controls a bus cycle. At this time, whether or not to use a wait request from the outside is determined based on the use setting of the wait request signal from the outside, and the bus cycle extension control is performed by the wait request signal from the outside. Further, by dividing the address space and selecting an address of the divided area, a corresponding wait control is performed to control a bus cycle.

A method is also known in which attention is paid only to memory access, the access to a high-speed memory and the access to a low-speed memory are discriminated, and the number of bus cycles is controlled. further,
There is known a method of controlling the number of bus cycles of a first data access and a subsequent data access at the time of a burst access to a memory having a burst transfer mode. For example, a memory access cycle control circuit of a data processing apparatus described in Japanese Patent Application Laid-Open No. 5-81126 controls the number of bus cycles by a signal input from an access cycle setting unit to perform memory access, thereby increasing the speed from a low speed. It supports memory up to high speed. Further, in this document, when it is determined that an instruction or data related to memory access can be stored in the connected cache memory, the access is switched to burst access, and the number of bus cycles thereafter is controlled to access the cache memory. Control is also performed.

As described above, the conventional access timing control method changes the bus cycle width by changing the number of bus cycles. However, such a method of merely changing the bus cycle width cannot control the timing of a plurality of signal lines that are slightly different from each other in a memory or an input / output device, and cannot optimize access. For example, when reading data from memory, the timing between signals such as address, chip enable, and read enable is important.
There are memories in which the timing of the rise or fall of these signals is slightly different. For such a memory, optimal control cannot be performed by changing only the number of bus cycles.

In recent years, the internal operating frequency of an external bus master such as a processor or a DMAC has become higher than the operating frequency of a bus cycle or the basic cycle frequency of a bus cycle, and the timing between control signals that could not be controlled before can be controlled. ing. However, conventionally, the bus cannot be used efficiently because the conventional bus cycle control is performed only with the number of bus cycles as described above.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and enables efficient bus control corresponding to various types of bus timings of an input / output device including a memory. It is an object of the present invention to provide a bus control device and a semiconductor device equipped with such a bus control device.

Further, the present invention provides a bus control device capable of easily adding a new bus timing or changing the bus timing by changing an input / output device to be accessed, and a bus control device having such a bus control device. It is an object to provide a semiconductor device.

Further, according to the present invention, a bus control device capable of constructing a low-cost system with a small circuit size while improving the integration efficiency while enabling flexible bus timing control corresponding to the input / output device as described above. It is an object of the present invention to provide a semiconductor device having the above configuration.

[0014]

As a basic configuration of a bus control device according to the present invention, an access timing defining means for holding a plurality of sets of setting values for defining an access timing, and an access timing defining means for holding the set values. Access timing selecting means for selecting any of a set of setting values, and bus timing generating means for creating a bus cycle based on the set of setting values selected by the access timing selecting means. The bus is accessed according to the bus cycle.

With such a configuration, if the timing of a plurality of control lines for performing bus access is held in the access timing defining means as a set of set values for each input / output device, Since a set of set values is selected and a bus cycle is created, fine timing control according to each input / output device can be performed. As a result, a more optimal bus cycle can be generated, and efficient bus control can be performed. In the access timing defining means, a set of set values for defining the access timing may be stored in a register, or may be held as a designation table.
Further, as the set value to be held, for example, the timing of the change point of each bus control line is defined with reference to the bus cycle start position, or the timing between the change points of any bus control line is defined. Can be.

Further, since the timings of a plurality of control lines for performing bus access are held in the access timing defining means as a set of set values, the access timing can be easily changed only by changing the set of set values. can do. If the access timing defining means has a margin, a new bus timing can be added without a new additional circuit.

Further, the bus timing generating means for generating a bus cycle includes address data at the time of bus access and a set value held by the access timing defining means selected by the access timing selecting means by an external selection control signal. , A bus cycle indicating the basic timing of a plurality of control lines is created. Therefore, even if there are input / output devices that require various types of timing control, basically only one bus timing generation unit is required. As a result, an inexpensive system can be constructed. Further, since the circuit scale can be small, it is advantageous when integrated as a semiconductor device. Note that the bus timing generating means can also create a bus cycle so that a plurality of input / output devices connected to the bus are accessed in the same bus cycle.

The bus timing generating means can generate a bus cycle according to a clock signal having an internal operating frequency higher than the operating frequency of the bus. As a result, fine timing control becomes possible, and a more optimal bus cycle can be created. Further, even when the internal operating frequency of the processor or the bus master is increased, it is possible to cope with it only by changing the set value of the access timing defining means.

Furthermore, a set of set values held in the access timing defining means is selected, and a control line controlled by a bus cycle created corresponding to the selected set of set values is selected by the bus control line selecting means. It can also be configured to select. Thus, the created bus cycle can be output to different control lines, and the bus can be more flexibly accessed to the input / output device.

A plurality of the above-described bus timing generating means can be connected to one bus, or can be provided for each of the buses to be controlled which controls the bus timing among the plurality of buses. At this time, access timing selecting means corresponding to each bus timing generating means is provided.
The access timing defining means can be provided in common for a plurality of bus timing generating means. For example, even if the system configuration becomes complicated, the circuit scale can be suppressed.

The access timing selecting means and the bus timing generating means may be provided in common for a plurality of control target buses, and the bus to be accessed may be selected by the bus selecting means. In this case, it is possible to perform optimal access to the plurality of buses with a smaller configuration.

When a system is constructed using the bus control device as described above or incorporated in a semiconductor device,
It can be configured using a plurality of bus controllers. When incorporated in a semiconductor device, the bus control device is connected to an internal bus. The internal bus may be connected to an external bus.

[0023]

FIG. 1 is a block diagram showing a first embodiment of a bus control device according to the present invention. In the figure, 11
Is an access timing definition register group, 12 is an access timing selection circuit, 13 is a bus timing generation sequencer, 21 is an access timing register selection signal, 2
2 is a timing designation signal, 23 is a bus control line, 24 is an address signal, and 25 is a selection control signal.

Access timing definition register group 11
Holds a plurality of sets of setting values that define the access timing at the time of performing bus access, and functions as access timing defining means. The access timing definition register group 11 receives the access timing register selection signal 2 sent from the access timing selection circuit 12.
1 and a set of the selected setting values is output as the timing designation signal 22. Here, it is assumed that each set of set values is held in the access timing definition register, and one of them is selected. However, the present invention is not limited to this. For example, the set of set values may be selectably held in various configurations, such as a configuration in which the set of set values is stored as a designation table.

The access timing selection circuit 12 controls the access timing definition register group 11 so that a set of set values that define the access timing is selected according to the access timing of the input / output device including the memory to be accessed. , An access timing register selection signal 21 is sent. This access timing selection circuit 1
2 functions as access timing selection means. The access target can be determined, for example, by acquiring address data set on an address bus as an address signal 24, or by a selection control signal 25 input from outside the bus control device or a control line of a control bus. . Here, both the address signal 24 and the selection control signal 25 are shown, but either one of them may be used, or the access target may be determined based on another signal.

The bus timing generation sequencer 13 generates a basic bus cycle in accordance with a set of set values that define the access timing selected by the access timing selection circuit 12 and output from the access timing specification register group 11 as the timing specification signal 22. Function as bus timing generating means. Further, a control signal is generated based on the created bus cycle, and the bus control line 2
Output to 3.

When a bus access is made to an input / output device including a memory connected to the bus, the access timing selection circuit 12 becomes a target of the bus access based on, for example, an address signal 24 and a selection control signal 25. Identify I / O devices. The access timing selection circuit 12 selects the access timing register from the access timing selection circuit 12 so that a set of set values that define the access timing corresponding to the input / output device is selected in the access timing definition register group 11. A signal 21 is output.

When the access timing register group 11 receives the access timing register selection signal 21 sent from the access timing selection circuit 12,
An access timing defining register holding a set of setting values defining the corresponding access timing is selected. The selected access timing regulation register is
The held set value is output as the timing designation signal 22. When a set of setting values for defining the access timing is held, for example, in the form of a table, an entry of the table is specified according to the access timing register selection signal 21, and the setting for defining the access timing included in the entry is specified. What is necessary is just to output a set of values as the timing designation signal 22.

When the timing specification signal 22 output from the access timing specification register group 11 is input to the bus timing generation sequencer 13, a basic bus timing is created in accordance with a set of set values that specify the received access timing. A control signal is generated and output to the bus control line 23.

In this manner, the bus access can be performed at the access timing according to the input / output device to be accessed. At this time, by changing the set of set values that define the access timing, for various input / output devices having different access timings,
Bus access is possible with the same hardware configuration. Also, even if an input / output device that must be accessed at a new access timing is connected to the bus,
If a set of set values defining the access timing is added so as to be selectable, or if the set value is changed, it can be easily handled. Such addition and change of the set of set values that define the access timing can be easily performed only by holding the set of set values in the access timing definition register.

FIG. 2 is a block diagram showing a second embodiment of the bus control device according to the present invention. In the figure, the same parts as those in FIG. 14 is a bus control line selection unit, 26 is a basic timing signal, and 27 is a bus control line selection signal.

The access timing selection circuit 12 responds to an input / output device including a memory or the like to be accessed.
An access timing register selection signal 21 is sent to the access timing definition register group 11, and a bus control line selection signal 27 for causing the bus control line selection unit 14 to select a control line to be controlled by the bus control line selection unit 14 is transmitted. Output.

The bus timing generation sequencer 13 creates a basic bus cycle in accordance with a set of setting values that define the access timing selected by the access timing selection circuit 12 and output from the access timing specification register group 11 as the timing specification signal 22. do it,
The signal is output to the bus control line selection unit 14 as the basic timing signal 26.

The bus control line selection section 14 receives the bus control line selection signal 2 output from the access timing selection circuit 12.
7, a control line to be controlled is selected, and the selected control line is controlled according to a basic timing signal 26 output from the bus timing generation sequencer 13.

As in the first embodiment, when performing bus access to an input / output device including a memory connected to the bus, the access timing selection circuit 1
2 specifies an input / output device to be accessed by a bus from, for example, the address signal 24 or the selection control signal 25,
An access timing register selection signal 21 is output to the access timing definition register group 11. The access timing specification register group 11 selects a corresponding access timing specification register in accordance with the access timing register selection signal 21 sent from the access timing selection circuit 12 and outputs a held set of set values as a timing specification signal 22. I do. When receiving the timing specification signal 22 output from the access timing specification register group 11, the bus timing generation sequencer 13 creates a basic bus timing according to a set of setting values that specify the received access timing, and generates a bus as the basic timing signal 26. Output to the control line selection unit 14.

The access timing selection circuit 12
Sends a bus control line selection signal 27 for selecting a bus control line to be used to the bus control line selection unit 14 according to the specified input / output device. The bus control line selection unit 14 selects a bus control line 23 to be output based on a bus control line selection signal 27 input from the access timing selection circuit 12.
Then, it generates a control signal according to the basic timing signal 26 sent from the bus timing generation sequencer 13 and outputs it to the selected bus control line 23.

In this manner, bus access can be performed at access timings corresponding to various input / output devices. In particular, in the second embodiment, the basic bus timing created by the bus timing generation sequencer 13 can be output to a different bus control line 23.

FIG. 3 is a block diagram showing a first example of a system using the first or second embodiment of the bus control device of the present invention. In the figure, 31 is a bus control unit, 32 is a CP.
U and 33 are memories, 34 is an I / O device, 41 is an address bus, 42 is a data bus, and 43 is a control bus. The system shown in FIG. 3 includes a CPU 32, a memory 33, and an I / O device 34, which are connected by an address bus 41, a data bus 42, and a control bus 43, respectively.

The bus control unit 31 is a bus control device of the present invention, and has, for example, the configuration shown in FIG. 1 as the first embodiment or the configuration shown in FIG. 2 as the second embodiment. ing. In the system configuration example shown in FIG. 3, the bus control unit 31 functions as a bus interface unit of the CPU 32.

The memory 33 and the I / O device 34 are provided with a bus control line 23 which forms a control bus 43, according to the functions possessed and the corresponding bus interface.
And the operation timing of the bus control line 23 may be different depending on the operation speed or the like.

The memory 33 is not directly connected to the address bus 41, the data bus 42, and the control bus 43, but the memory control device is connected to the address bus 41, the data bus 42, and the control bus 43, and It may be connected to each bus via the same. Also,
Instead of CPU 32, address bus 41, data bus 4
2 and a bus control unit 3 for controlling the control bus 43
1 may be a bus master, for example, a DMAC.

FIG. 4 shows an operation timing of the bus control line 23 at the time of memory access or I / O device access in the first example of the system using the first or second embodiment of the bus control device of the present invention. 6 is a timing chart showing one example. Address Adrs is address bus 4
1. Data Data indicates the data bus 42, respectively.
For convenience, a chip select CS # (# indicates a signal line at a low level when activated and a high level when deactivated.
The same applies hereinafter. ), Write enable WE #, and output enable OE # are bus control lines 23 included in the control bus 43. The bus control line 23 that does not change is not shown. FIG. 4 (A)
4 shows a typical timing example at the time of write access.
(B) shows a typical timing example at the time of read access, in which a part defining each access timing is described. It should be noted that the bus control line to be used differs depending on the manufacturer, each device, or the method of using the device, or the point at which the timing is specified changes. Therefore, detailed description of each timing specification is omitted here.

At the time of the write access shown in FIG.
As the bus control line 23, a chip select CS # and a write enable WE # are used. After outputting the address Adrs and the data Data to be written, the chip select C
S # falls, and write enable WE # falls. Then, data Data when the write enable WE # is activated is written. For example, in the case of a write access to the memory 33, the data Data is stored at the address indicated by the address Adrs. In the case of a write access to the I / O device 34, the I / O device 34 or the I / O device 34 depends on the address Adrs.
The function of the / O device 34 is selected, and the data of Data is taken into the I / O device 34. afterwards,
The chip select CS # is activated, and the write access cycle ends.

In such a write access, each signal line
As the control timing, as shown in FIG.
The specified value may be set. First, t_WCIs light
The time of one cycle at the time of access is shown. Also t_AWIs a rye
Write enable WE # from the start of the write access cycle
Time to start up is t_AHIs a write enable
End of write access cycle after starting WE #
Indicates the time until. Settings related to chip select CS #
As a value, t_CWIs Chip Select CS # Falling?
Time until the write enable WE # starts up,
t_CHIs the chip after starting write enable WE #
Indicates the time until the start of select CS #. Also la
The set value for the write enable WE # is t_ASIs la
Write enable WE from the start of the write access cycle
# The time to fall is t _WPIs write enable
WE # falls, then write enable WE # rises
The time to raise is shown. Further data
Stabilize the data at the time of writing as the set value for
Required before the write enable WE # falls.
Time t_DSAnd the required time t_DHIs shown.

Similarly, at the time of the read access shown in FIG. 4B, a chip select CS # is set as the bus control line 23,
Output enable OE # is used. Address Ad
After outputting rs, the chip select CS # falls and the output enable OE # falls. After the output enable OE # falls, data is output as data Data at a predetermined time interval. For example, in the case of a read access from the memory 33, the data stored at the address indicated by the address Adrs is the data Data
Is output to In the case of read access to the I / O device 34, the I / O device 34 or the function of the I / O device 34 is selected by the address Adrs,
The I / O device outputs data to data Data.
Then, at the time when the output enable OE # is activated, the data output as the data Data may be obtained. Thereafter, the chip select CS # is activated, and the write access cycle ends.

As a control timing of each signal line at the time of such read access, various prescribed values may be set as shown in FIG. First, t _RC indicates the time of one cycle at the time of read access. As the set values related to the chip select CS #, t _CO is the time from when the chip select CS # falls to when the output of the data Data is started, and t _CH is the output enable OE #.
Shows the time from the start of the operation to the start of the chip select CS #. As a set value related to the output enable OE #, t _OE is the output enable OE #.
The time from the fall of E # to the start of output of data Data is shown. Further, as a set value related to data Data, t _AA is a time from the start of the read access cycle to the start of output of data Data, t t
_OH indicates the time from when the output enable OE # rises to when the output of the data Data is completed.

As described above, the operation timing of the bus control line 23 is specified for each of the read access and the write access. The specified value of the operation timing of the bus control line 23 varies depending on the type and function of the input / output device, the corresponding operation frequency, and the like, and is usually specified in the order of several nanoseconds to several hundred nanoseconds. When there are a plurality of timing control units that satisfy the respective operation timing specified values, the circuit scale becomes large. Therefore, in order to realize the bus operation timing in all the input / output devices such as the memory 33 and the I / O device 34 connected to the bus, the bus control device of the present invention as shown in FIG. Bus controller 31 is provided.

In the bus controller 31, as described in the first and second embodiments of the bus controller of the present invention,
The operation timing definition value for accessing the memory 33 and the I / O device 34 is held in the access timing definition register group 11 and is selected by the access timing selection circuit 12 when accessing. Based on the selected specified value, the bus timing generation sequencer 13 generates the operation timing of the bus control line 23 used as the basic bus timing.

FIG. 5 is a basic bus timing chart created by the bus timing sequencer 13 in the bus control unit 31 in the first example of the system using the first or second embodiment of the bus control device of the present invention. FIG. 3 is an explanatory diagram of an example of an access timing definition point set in an access timing definition register group. FIG. 5A shows a timing chart and an access timing regulation point at the time of a write access, and FIG. 5B shows a timing chart and an access timing regulation point at the time of a read access. In FIG. 5, a data direction DD # is shown as one of the bus control lines 23. The data direction DD # is a control line for controlling the input / output direction of a bidirectional buffer arranged on the data bus 42. In FIG. 5, read access is performed for the purpose of reducing the number of timings specified. Sometimes it is activated at the same timing as the chip select CS #. In addition, read enable RE # is shown instead of output enable OE #.

At the access timing at the time of the write access shown in FIG. 5A, the read enable RE # and the data direction DD # are not activated and remain at the high level. Then, the chip enable CS # and the write enable WE # are activated. At this time, the address Ad
After the chip select / setup period t _CS from the output of rs, the chip enable CS # falls and is activated, and thereafter, the write enable / setup period t _WS
Later, the write enable WE # falls and is activated.
After this state is maintained for the write enable activation period _tWW , the write enable WE # is activated and deactivated. Further, after the chip select / hold period _tCH , the chip enable CS # also rises and is deactivated. Further, after the address hold period t _AH , the address Adrs switches, and the bus cycle ends. At the time of write access, these periods t _CS , t _WS , t _WW , t _CH , and t _AH may be held as set values in the access timing definition register.

At the access timing at the time of the read access shown in FIG. 5B, conversely, the write enable WE # is not activated and remains at the high level. Then, the chip enable CS #, the read enable RE #, and the data direction DD # are activated. At this time, after the address Adrs is output, the chip enable CS # falls and is activated after a chip select / setup period t _CS , and the data direction DD # falls and is activated. After that, the read enable RE # falls and is activated after a read enable setup period t _RS . After this state is maintained for the read enable activation period t _RW , the read enable RE # is activated and deactivated. Further, after the chip select / hold period _tCH , the chip enable CS # also rises and is deactivated. After the read enable RE # is activated, the data direction DD # is also activated and deactivated when the data direction hold period _{tDH has} elapsed. The address Adrs is switched after the address hold period t _AH from the rise of the chip enable CS #, and the bus cycle ends. At the time of read access, these periods t _CS , t _RS , t _RW , t _CH , t _DH , and t _AH
May be held as a set value in the access timing definition register.

FIG. 6 is a comparison diagram of an example of bus timing control using a bus clock and an example of bus timing control using a higher-speed internal clock.
FIG. 6 shows the case of read access. According to the set value that defines the access timing as described above, the bus timing generation sequencer 13
Create a bus cycle as shown in FIG. At this time, when creating a bus cycle using the bus clock, FIG.
As shown in (A), each bus control line is controlled in synchronization with the rising edge or falling edge of the bus clock CLKb. In this case, each bus control line can be controlled in units of a cycle or a half cycle of the bus clock CLKb according to the set value. For example, FIG.
The read cycle width t _RW in (A) can be changed or extended.

In recent years, the internal operating frequency of a device such as a CPU or a bus master has become higher than the operating frequency of a memory or an I / O device, and the use of this internal operating frequency allows finer operation timing. Control is possible. As shown in FIG. 6B, the internal clock C having a higher frequency than the bus clock CLKb.
By using the LK, finer control of each bus control line can be performed in units of a cycle or a half cycle of the internal clock CLK.

In recent years, the internal operating frequencies of CPUs, bus masters, and the like have been steadily increasing. However, even if the internal operating frequency is changed, only the set value for defining the access timing is changed. Bus access corresponding to the operating frequency is possible.

FIG. 7 is an explanatory diagram of an example of a set value for defining the access timing to be set in the access timing defining register group 11. Here, for example, as shown in FIG. 6B, each set value is indicated by the number of clocks when a high-frequency internal clock is used. Each setting item has been described with reference to FIG. When the set value is 0, it indicates that the control line changes at the same time as the previous control line changes. For example, the write enable setup period t _WS and the read enable setup period t _RS of pattern 4 are zero. This is based on the chip select C period according to the chip select setup period t _CS.
At the same time as the fall of S #, the write enable WE # or the read enable RE # falls and is activated.

The set of set values according to a plurality of access timing patterns can be stored in the access timing definition register group 11 as shown in FIG.
The access timing selection circuit 12 decodes, for example, the address signal 24 on the address bus 41, or selects one of a set of set values stored in the access timing definition register group 11 according to an external selection control signal 25. Is determined, and an access timing register selection signal 21 is sent to the access timing definition register group 11. The access timing definition register group 11 outputs a set of set values from the selected access timing definition register according to the access timing register selection signal 21 sent from the access timing selection circuit 12. Alternatively, as shown in FIG. 7, a set of set values may be held as a designation table, and a set of set values of the selected pattern may be read and output.

The set of set values output from the access timing definition register group 11 is input to the bus timing generation sequencer 13 to create a bus cycle for read access or write access as shown in FIG. 5, for example. Whether the bus cycle is a read access or a write access may be input to the bus timing generation sequencer 13 before any of the enable signals is generated, or may be input at the start of the bus cycle.

The bus control line 23 is controlled based on the bus cycle generated by the bus timing generation sequencer 13 and a control signal is output to the control bus 43 shown in FIG. 3 so that the memory 33 or the I / O device 34 Access to the input / output device. At this time, since the bus cycle is created by using a set of set values defining the access timing according to the input / output device such as the memory 33 and the I / O device 34, the bus access is performed at the optimum timing for each device. It can be performed.

FIG. 8 shows another example of the access timing definition point set in the access timing definition register group in the first example of the system using the first or second embodiment of the bus control device of the present invention. FIG. 9
FIG. 4 is an explanatory diagram of another example of a set value that defines an access timing set in the access timing definition register group 11. The setting points for defining the access timing shown in FIG. 5 and the access timing shown in FIG. 7 were set using the period (the number of clocks) from the related already changed point. However, the setting value defining the access timing is not limited to this example, and various setting methods can be applied. As another example, FIGS. 8 and 9
In, a set value that defines each access timing is set in a period (the number of clocks) from the first point where a bus cycle occurs. The occurrence of the bus cycle can be determined, for example, at the point where the effective address starts to be output to the address Adrs, or based on the bus cycle start signal BS # included in the control bus.

In FIG. 8, bus cycle start signal BS
# Is the first point of the bus cycle, and each set value is defined by the period from this point. Each of the setting values defined in this way may have a large value. However, in the processing inside the bus timing generation sequencer 13, it is not necessary to reset the internal counter at each signal change point, and the internal counter needs to be reset only at the first point where a bus cycle occurs. Therefore, although the circuit scale is increased, the operating frequency of the entire bus timing generation sequencer 13 can be reduced.

When each set value is specified as shown in FIG. 8, each set value held in the access timing specifying register group 11 is operated at a high internal operating frequency, for example, as shown in FIG. In this case, the number of clocks is shown. Here, the address hold period t _AHW and chip select hold period t _CHW during write access and the address hold period t _AHR and chip select hold period t _CHR during read access are shown as different set values. However, when these setting values are exactly the same at the time of write access and at the time of read access in all patterns, the setting values may be combined. Or
The address hold period t _AH and the chip select hold period t _CH may each be one, and patterns used for write access and read access may be changed so that different access timings can be handled.

The set value for defining the access timing stored in the access timing definition register group 11 is defined by the number of operation clocks in FIGS. 7 and 9, but is not limited to this. As long as the timing can be specified, the time value may be, for example, in nanoseconds.

FIG. 10 shows a bus timing sequencer 13 in a bus control unit 31 in a first example of a system using the first or second embodiment of the bus control device of the present invention.
FIG. 11 is an explanatory diagram of still another example of the set value that specifies the access timing set in the access timing specifying register group 11. In the examples shown in FIGS. 4 and 5, general access timing is shown, but there may be a bus signal which does not need to be input depending on a device to be accessed. For example, in the example of the bus timing chart shown in FIG. 10, when the memory 33 is accessed, the write enable WE #
Alternatively, an example is shown in which read enable RE # is used but chip select CS # is not used.

As a method corresponding to such a case, a method in which the second embodiment of the present invention shown in FIG. 2 is used and the bus control line selecting unit 14 does not output to the bus control line 23 is used. It is. Bus timing generation sequencer 1
3 is input to the bus control line selection unit 14 as a basic timing signal 26, and unnecessary bus control is performed when selecting the bus control line 23 to be output based on the bus control line selection signal 27. What is necessary is just to control so that a control signal is not output to the line 23.

As another method, there is a method of setting a set value for defining the access timing so as not to generate unnecessary signal timing. Of the setting values that define the access timing stored in the access timing definition register group 11, a setting value that is not used as a default timing value is set in the access timing definition register for the bus control line 23 that is not necessary for bus access. deep. For example, "-1" can be set as shown in pattern 3 in FIG. And
When the bus timing generation sequencer 13 creates a bus cycle based on the set value, if a set value that is not used appears, the configuration may be such that the basic timing is not generated. Thus, the bus control line 2 which does not need to be controlled is
3 can be controlled so as not to output a control signal. FIGS. 10 and 11 show an example in which the period from the start of the bus cycle is set as the set value, as in FIGS. 8 and 9. However, as shown in FIGS. It is possible to set various values as described above, such as setting the period of time as a set value.

FIG. 12 shows a bus timing sequencer 13 in a bus control unit 31 in a first example of a system using the first or second embodiment of the bus control device of the present invention.
6 is a bus timing chart showing an example of a burst access created by the first embodiment. In the description of the operation of the first example of the system up to this point, when accessing the input / output devices such as the memory 33 and the I / O device 34, the bus cycle is generated and accessed. However, some devices are permitted to perform burst access. FIG. 12 shows a bus timing chart when such a burst access is performed.

The bus timing chart shown in FIG. 12 shows an example in which read is performed twice by burst access. During burst access, chip select C
S # and data direction DD # hold the state. During this time, the area where the address Adrs is different is specified, and the read enable RE
# Is activated and data Data is read.

When burst access is designated,
For example, using the bus control device according to the second embodiment of the present invention shown in FIG. 2, the bus control line selecting unit 14 controls the bus control lines 23 for maintaining the state for successive bus cycles.
Is selected. Bus timing generation sequencer 13
Generates a basic bus timing for burst access that is different from the normal bus timing and outputs it as a basic timing signal 26. During the burst access, for example, the chip select CS # and the data direction DD # are held in the bus control line selector 14, so that continuous access is possible.

The address Adrs is not limited to this setting.
The access timing selection circuit 12 is configured to specify the bus control line 23 for holding the state to the bus control line selection unit 14 in accordance with a device that forms a burst cycle, such as a method for holding a state for #. You may.

Further, a set of prescribed values for burst access may be stored as a set of set values for defining the access timing held in the access timing defining register group 11. In this case, a method may be used in which all of the prescribed values for burst access are set as one pattern, or the first access pattern and the subsequent access patterns may be set separately and used continuously.

Although the example shown in FIG. 12 shows an example in which the read access is performed in the burst mode, the same applies to the case in which the write access is performed in the burst mode.

FIG. 13 shows the bus timing in the bus control unit 31 when a plurality of devices are simultaneously accessed in the first example of the system using the first or second embodiment of the bus control device of the present invention. 4 is a timing chart illustrating an example of a bus timing created by a sequencer 13. In each of the above examples, only one device is accessed in one bus cycle. However, a plurality of devices may be accessed in one bus cycle. As described with reference to FIGS. 10 and 11, the device is not necessarily a bus control line 23 generated from the basic bus timing generated by the bus timing generation sequencer 13.
Not all of them are needed. In addition, there is a bus master such as a DMAC that generates a read bus cycle for reading data from one device and generates a write bus cycle for writing the data to another device. If the timing can be adjusted, one bus cycle is performed. To finish reading and writing. FIG. 13 shows an example that can be used in such a case, in which two devices are accessed, one for read access and the other for write access.

The bus cycle shown in FIG. 13 differs from the normal bus cycle in that both read enable RE # and write enable WE # are activated. For example, the memory 33 is a read device, and the bus control line 23 required for access is an address Adrs and a read enable RE #. The write device is an I / O device 34, and the bus control line 23 required for access is a write enable WE #. Chip enable CE #
And the data direction DD # may be input to both devices, may be input to one device, or may not be used, depending on the system configuration.

Data direction D to read device
The operation of a system in which D # is connected to a chip enable CE # to a write device will be described. The read enable RE # and the write enable WE # are connected to a read device and a write device, respectively.
Alternatively, the bus control lines 23 connected to the respective devices may be controlled by the bus control line selection unit 14 in the second embodiment of the bus control device of the present invention shown in FIG.

In the read device, data is read by the address Adrs and the read enable RE #.
Valid data is output to the data bus Data. on the other hand,
In the write device, data on the data bus Data is written according to the timing of the write enable WE #. If valid data is output on the data bus Data at the time of writing data, the data read in the same bus cycle can be written. In this way, the data transfer performed in two bus cycles is changed to
It can be completed in one bus cycle. In addition,
The combination of the bus control lines 23 to be used or the types of the read device and the write device may be appropriately changed according to the system configuration.

As described above, by using the bus control device of the present invention, it is possible to cope with input / output devices having various bus timings and to cope with various access methods. .

FIG. 14 is a block diagram showing a second example of a system using the first or second embodiment of the bus control device of the present invention. In the figure, the same parts as those in FIG. Reference numeral 35 denotes a bus control unit, 36 denotes a bus master, 37 denotes a bus arbiter, and 38 denotes an I / O device. In the second system example shown in FIG. 8, two or more devices mounting a bus control unit for controlling the address bus 41, the data bus 42, and the control bus 43 are connected.
Is connected.

As in the example shown in FIG. 3, the CPU 32 has the bus control unit 31 and the bus master 3
6 is also provided with a bus control unit 35. Bus control unit 3
5 is also the first or second bus control device of the present invention described above.
This is shown in the embodiment. Of course, the plurality of devices having a bus control device connected to one bus are not limited to the CPU 32 and the bus master 36 as in this example, and both are CPU or DMA.
C may be a bus master, and the number is 2
It is not limited to one. Address bus 4
1, the bus control lines 23 that can be controlled by the respective bus control devices (the bus control unit 31 and the bus control unit 35) among the data bus 42 and the control bus 43 may be completely the same or may be partially different. Good.

The bus arbiter 37 controls the ownership of the bus so that the bus control unit 31 and the bus control unit 35 do not control the bus at the same time. Therefore, bus arbiter 37
And a bus control line 23 connecting the CPU 32 and the bus master 36 to the control bus 43.

In the system shown in FIG. 14, a plurality of devices to be controlled may be connected. Here I / O
An example is shown in which the device 38 is connected to a bus and two I / O devices are connected to the bus. Bus master 3
6 may access the CPU 32.
32 inputs the address bus 41. Furthermore, CP
The U32 or the bus master 36 may access the bus arbiter 37, and the bus arbiter 37 inputs the address bus 41 and the data bus 42.

The operation of the second system example shown in FIG. 14 will be described. Here, parts different from the first system configuration example shown in FIG. 3 will be mainly described.
In the second system example, the CPU 32 is also the bus master 3
Since the bus 6 can also control the bus, a bus arbiter 37 for determining ownership of the bus is provided. Therefore, it is necessary to acquire the bus ownership from the bus arbiter 37 before performing the access shown in FIGS. 4 and 5, for example, and the bus control line 23 is controlled for that.

FIG. 15 is a timing chart showing an example of the bus control operation in the second example of the system using the first or second embodiment of the bus control device of the present invention. In the example shown in FIG. 15, the bus arbiter 37 and the CP
Four control signals are shown as a bus control line 23 for controlling bus ownership between the U32 and the bus master 36. The bus ownership request REQ0 # is a signal for requesting the bus ownership from the CPU 32 to the bus arbiter 37.
The bus arbiter 37 determines that the bus ownership permission GNT0 # is CP.
This is a signal for giving bus ownership to U32.
Further, the bus ownership request REQ1 # is a signal for requesting the bus arbiter 37 to request the bus ownership from the bus master 36, and the bus ownership permission GNT1 # is a signal for the bus arbiter 37 to give the bus master 36 the bus ownership. It is.

The CPU 32 and the bus master 36 can make bus ownership requests independently of each other. This bus ownership request is sent to the CPU 32 by the bus ownership request REQ0 #
Shut down. In the bus master 36, the bus ownership request R
What is necessary is just to make EQ1 # fall. The bus arbiter 37
If the bus is free, the device requesting the bus ownership is given the bus ownership. When giving the bus ownership to the CPU 32, the bus ownership permission GNT0 # is deactivated,
When giving the bus ownership to the bus master 36, the bus ownership permission GNT1 # is dropped. When the bus is in use, various controls are possible, for example, giving the bus ownership alternately, or assigning priorities, and giving the bus ownership preferentially to the device with the higher priority.

The CPU 32 or the bus master 36 having acquired the bus ownership may execute the bus control shown in the above-mentioned first system example by using the own bus control unit 31 or the bus control unit 35, respectively.

In the example shown in FIG. 15, when the bus is released at idle (Idle), the CPU
The bus ownership request REQ0 # from the bus master 36 is issued at time point b.
Q1 # has been issued. The bus arbiter 37 performs a bus ownership determination operation, and in this example, at a time point c,
The bus ownership is given to the CPU 32 by GNT0 #. In response to this, the CPU 32 sets the read cycle (B-0)
Rd). Bus access in this read cycle is performed, for example, at the timing shown in FIG. 4B and FIG. 5B. Since the bus access in this read cycle has already been described in detail, the description is omitted here. By the end of the read cycle, the CPU 32 may have issued the next bus ownership request.
32 issues the next bus ownership request.

When the bus is in use, the bus arbiter 37 gives the bus ownership to the CPU 32 and the bus master 36 alternately. At a time point e immediately before the end of the read cycle (B-0Rd) by the CPU 32, the bus arbiter 37 The arbiter 37 gives the bus master 36 the bus ownership by the bus ownership permission GNT1 #. The bus master 36 acquires the bus ownership and performs the write cycle (B-1Wr). The bus access in this write cycle is performed at the timing shown in, for example, FIG. 4 (A) or FIG. 5 (A). Since the bus access in this write cycle has already been described in detail, the description is omitted here. By the end of the write cycle, the bus master 36 may have issued the next bus ownership request.

As described above, the bus ownership permission GNT0 # and GNT1 # are closely related to the bus control operation and need to be synchronized. However, the bus ownership request REQ
0 #, REQ1 #, and the bus ownership determination operation need not be synchronized with the bus control operation.

The example shown in FIG. 15 shows a case where the CPU 32 performs a read access and the bus master 36 performs a write access. Of course, in any bus cycle, either the read access or the write access is performed. Is also good. Further, the bus timings of the read access and the write access are not limited to the bus timings shown in FIGS. 4 and 5, but may be a case where some bus control lines 23 are not used as shown in FIG. For example, the bus timing may correspond to various system conditions, such as when a burst access is performed, or when a plurality of devices are accessed in the same bus cycle as shown in FIG.

FIG. 16 is a block diagram showing a third embodiment of the bus control device according to the present invention. In the figures, FIGS. 1 and 2
The same reference numerals are given to the same parts as. In the third embodiment, it is assumed that a plurality of bus control lines 23 are connected, and an access timing selection circuit 12 and a bus timing generation sequencer 1
3, a configuration having a bus control line selection unit 14 and commonly using the access timing definition register group 11 is shown. As in the first embodiment, the bus control line selection unit 14 may not be provided for all or some of the bus control lines 23.

Access timing definition register group 11
When the access timing register selection signal 21 is received from one of the two access timing selection circuits 12, the access timing register selection signal 21 is issued using the set of set values defining the selected access timing as the timing designation signal 22. It outputs to the bus timing generation sequencer 13 corresponding to the selected access timing selection circuit 12. Then, the bus timing generation sequencer 13 that has received the timing designation signal 22 from the access timing regulation register group 11 creates a bus cycle, sends the basic timing signal 26 to the corresponding bus control line selector 14, and controls the bus control line 23. A signal will be output.

According to the third embodiment, compared to the configuration in which the first and second embodiments of the bus control device of the present invention shown in FIG. 1 and FIG. The circuit size can be reduced by the amount of sharing the group 11. In the example shown in FIG.
Although an example of connection to three buses has been shown, the same applies to a case of connection to three or more buses. Further, the plurality of bus control lines 23 may be connected to the same bus, and may be given bus ownership by a bus arbiter.

FIG. 17 is a block diagram showing a fourth embodiment of the bus control device according to the present invention. In the figures, FIGS. 1 and 2
The same parts as those described above are denoted by the same reference numerals and description thereof will be omitted. 1
5 is a bus selection unit, and 28 is a bus selection signal. This fourth
Also in the embodiment, it is assumed that the bus control lines 23 are connected to a plurality of bus control lines 23. The access timing definition register group 11, the access timing selection circuit 12, the bus timing generation circuit An example in which a bus control line 23 having a sequencer 13 and outputting a control signal by a bus selection unit 15 is selected is shown. In addition,
As in the second embodiment, the bus control line selection unit 1
4 may be provided for all or some of the bus control lines 23 or in common.

The access timing selection circuit 12 recognizes the bus to which the device to be accessed is connected, and sends a bus selection signal 28 to the bus selection unit 15. The bus selection unit 15 receives the bus selection signal 28 from the access timing selection circuit 12, selects the bus control line 23, and selects a control signal according to the bus cycle generated by the bus timing generation sequencer 13. Output to

According to the fourth embodiment, it is impossible to access a plurality of buses at the same time. can do. The number of buses selected by the bus selection unit 15 is not limited to two, and may be configured to select three or more buses.

FIG. 18 is a block diagram showing an example of a system using the third or fourth embodiment of the bus control device of the present invention. In the figure, the same parts as those in FIG. 14 are denoted by the same reference numerals, and description thereof will be omitted. 44 is a secondary address bus, 45
Is a secondary data bus, 46 is a secondary control bus, 51
Is a bus control unit. The bus master 36 has a primary bus composed of an address bus 41, a data bus 42, and a control bus 43, and a secondary bus composed of a secondary address bus 44, a secondary data bus 45, and a secondary control bus 46. Connected and controlling each. The bus master 36 has a bus control unit 51. The bus control unit 51 is shown in FIGS. 16 and 17 as the third and fourth embodiments of the bus control device of the present invention.

The bus control unit 51 is provided, for example, as shown in FIGS.
Since the present invention has the configuration of the present invention, the bus access can be made to the primary bus and the secondary bus. The timing at the time of each bus access and the like are the same as those in the above-described examples. Of course, burst access can also be performed. In FIG. 18, only the memory 33 is connected to the primary bus, and only the I / O device 38 is connected to the secondary bus. However, the present invention is not limited to this. Can access the bus. In this case, an access method for performing data transfer in one bus cycle as shown in FIG. 13 can be applied.

In FIG. 18, the bus is accessed by the bus master 36, but a CPU 32 that can be connected to a plurality of buses may be connected instead of the bus master 36. Of course, a system configuration in which the bus master 36 and the CPU 32 are connected to the same bus as in the system example shown in FIG. 14 is also possible. Furthermore, two bus control lines 23 of the bus control unit 51 in the bus master 36 may be connected to the same bus, and the bus arbiter may control the ownership of the bus.

In FIG. 18, a system using the third and fourth embodiments of the bus control device of the present invention has been described. However, for example, the bus control device shown as the first and second embodiments of the present invention. A configuration in which a plurality of control devices are provided for each bus, that is, a configuration in which the bus master 36 has a plurality of bus control units may be employed.

In the foregoing, some system configurations using the bus control device of the present invention have been described. These systems can be formed, for example, on one semiconductor device. Hereinafter, several examples will be described for the case where a system is formed on a semiconductor device.

FIG. 19 is a block diagram showing an example of a system formed on a semiconductor device using the bus control device of the present invention. In the figure, 61 and 62 are semiconductor devices, 71 is an internal address bus, 72 is an internal data bus, 73 is an internal control bus, 81 is a bus control unit, and 82 is a CPU.
Unit, 83 is a memory unit, 84 is an I / O unit, and 85 is a buffer.

This example corresponds to the system example shown in FIG. 3, and includes a CPU section 82, a memory section 83, an I / O
The unit 84 corresponds to the CPU 32 and the memory 3 in FIG.
3. A portion corresponding to the I / O device 34 is formed as an internal element of the semiconductor device 61. Further, a bus control unit 81 also corresponds to the bus control unit 31 in FIG. 3 and is a bus control device shown as the first or second embodiment of the present invention.

CPU 82, memory 83, I / O 8
4 is connected to an internal address bus 71, an internal data bus 72, and an internal control bus 73, controls a bus control line of the internal control bus 73 by a bus control unit 81, and stores a memory unit 83 and an I / O unit 84. Bus access can be performed. At this time, since the bus access is performed based on the set value that defines the access timing corresponding to each access target as described above, the bus access can be performed at the optimal timing for each access target. The operation of the bus access is the same as that of the system example shown in FIG. 3, for example, and the description is omitted here.

In the semiconductor device 61 shown in FIG. 19A, an example in which the internal address bus 71, the internal data bus 72, and the internal control bus 73 are applied only to the internal bus of the semiconductor device 61 is shown. FIG.
The semiconductor device 62 shown in (B) connects an internal address bus 71, an internal data bus 72, and an internal control bus 73 to an external bus including an address bus 41, a data bus 42, and a control bus 43 via a buffer 85. An example in which both are used is shown. When the internal bus is used together with the external bus, not all signal lines need to be used together.

FIG. 20 is a block diagram showing another example of a system formed on a semiconductor device using the bus control device of the present invention. In the figure, the same parts as those in FIG. 19 are denoted by the same reference numerals, and description thereof will be omitted. 63 is a semiconductor device, 74 is an internal secondary address bus, 75 is an internal secondary data bus, 7
6 is an internal secondary control bus, 86 is a bus control unit, 8
7 is a bus master unit, 88 is an I / O unit, 89 is a bus arbiter unit, and 90 is a buffer.

This example shows a configuration example of a semiconductor device connected to a plurality of buses based on the system example shown in FIG. 14 and the system example shown in FIG. CPU unit 8
2, memory unit 83, I / O unit 84, bus arbiter unit 8
9 are the CPU 32, the memory 33,
A portion corresponding to the I / O device 34 and the bus arbiter 37 is formed as an internal element of the semiconductor device 63. Further, the bus master unit 87 and the I / O unit 88 correspond to the bus master 36 and the I / O device 3 in FIG.
8 is formed as an internal element of the semiconductor device 63. Note that the bus control unit 81
Corresponds to the bus control unit 31 in the first embodiment, and is a bus control device shown as the first and second embodiments of the present invention. A bus control unit 86 corresponds to the bus control unit 51 in FIG. 18, and is a bus control device shown as the third or fourth embodiment of the present invention.

The CPU section 82 has a bus control section 81, and is connected to an internal primary bus composed of an internal address bus 71, an internal data bus 72, and an internal control bus 73, and controls the bus. The bus master unit 87 has a bus control unit 86 capable of controlling a plurality of buses. The bus master unit 87 has an internal primary bus composed of an internal address bus 71, an internal data bus 72, and an internal control bus 73, and an internal secondary bus. Address bus 74, internal secondary data bus 7
5 and an internal secondary control bus 76 to control each of them. The bus access operation of the bus control unit 81 and the bus control unit 86 is the same as that of the system shown in FIGS. 14 and 18, and the description is omitted here.

The internal primary bus is accessed by the bus control unit 81 of the CPU unit 82 and the bus control unit 86 of the bus master unit 87. Therefore, the bus arbiter 89 controls the ownership of the internal primary bus. The control of the bus ownership at this time is the same as that of the system shown in FIG.

In a semiconductor device having a plurality of internal buses, all or some of the internal buses may be used together with an external bus. For example, in the configuration shown in FIG. 20, the internal secondary address bus 74, the internal secondary data bus 75, and the internal secondary control bus 76
Through the buffer 90,
The secondary address bus 44, the secondary data bus 45, and the secondary control bus 46 are connected to and used together with an external secondary bus. Further, the internal address bus 7
1. Internal data bus 72 and internal control bus 7
The internal primary bus 3 is also connected to an external bus composed of the address bus 41, the data bus 42, and the control bus 43 via the buffer 85, and is also used. Of course, in the configuration shown in FIG. 20, one or both may not be connected to the external bus.

The CPU 82, the memory 83, the I / O
The number of O-ports 84 and 88 and the number of connected buses are arbitrary. The presence or absence of the bus arbiter unit 89 is optional. Of course, the same configuration as FIG.
Alternatively, a configuration similar to that of FIG. 18 can be formed on a semiconductor device.

Further, as the bus control unit 86 provided in the bus master unit 87, a plurality of bus control devices shown in the first and second embodiments of the present invention may be provided. Alternatively, CPU
The bus control unit 81 provided in the unit 82 and the bus control unit 86 provided in the bus master 87 may be integrated by the bus control device shown in the third and fourth embodiments of the present invention. In this case, three buses can be controlled by one bus control unit.
In general, when there are a plurality of CPU units and bus master units and there are a large number of bus control units, all or some of them are integrated by the bus control devices described in the third and fourth embodiments of the present invention. It is possible.

[0111]

As is apparent from the above description, according to the present invention, since the bus access is performed according to the set value that defines the access timing according to each access target, fine timing control becomes possible. A more optimal bus cycle can be created and efficient bus control can be performed. Also, the bus access timing can be changed only by changing the set value that defines the access timing, and new addition is easy. Further, even if the internal operating frequency of the microprocessor or the bus master is changed, it is possible to cope only by changing the set value that defines the access timing.

By using the bus control device of the present invention, the present invention can be applied to various types of access targets as described above. Therefore, it is not necessary to provide a bus control device for each access timing of each access target, and a small circuit A system can be built on a scale. Further, even when performing a plurality of bus accesses to a plurality of buses or to the same bus, it is possible to commonly use a set value that defines the access timing, and the configuration becomes complicated. Can also reduce the circuit scale. According to the present invention, there are various effects as described above.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of a bus control device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the bus control device of the present invention.

FIG. 3 is a configuration diagram illustrating a first example of a system using the bus control device according to the first or second embodiment of the present invention;

FIG. 4 shows an example of an operation timing of a bus control line 23 at the time of memory access or I / O device access in a first example of a system using the bus control device according to the first or second embodiment of the present invention. It is a timing chart shown.

FIG. 5 is a basic bus timing chart and access timing created by a bus timing sequencer 13 in a bus control unit 31 in a first example of a system using the first or second embodiment of the bus control device of the present invention. FIG. 4 is an explanatory diagram of an example of an access timing definition point set in a definition register group.

FIG. 6 is a comparison diagram of an example of bus timing control using a bus clock and an example of bus timing control using a higher-speed internal clock.

FIG. 7 is an explanatory diagram of an example of a set value that defines an access timing set in an access timing definition register group 11;

FIG. 8 is an explanatory diagram of another example of the access timing definition point set in the access timing definition register group in the first example of the system using the first or second embodiment of the bus control device of the present invention. It is.

FIG. 9 is an explanatory diagram of another example of a set value that defines an access timing set in the access timing definition register group 11;

FIG. 10 is another bus timing chart created by the bus timing sequencer 13 in the bus control unit 31 in the first example of the system using the bus control device according to the first or second embodiment of the present invention. .

FIG. 11 is an explanatory diagram of still another example of a set value that defines an access timing set in the access timing definition register group 11;

FIG. 12 shows an example of a burst access created by the bus timing sequencer 13 in the bus control unit 31 in the first example of the system using the bus control device according to the first or second embodiment of the present invention. 6 is a bus timing chart.

FIG. 13 is a block diagram showing the bus timing sequencer 13 in the bus control unit 31 when a plurality of devices are simultaneously accessed in the first example of the system using the first or second embodiment of the bus control device of the present invention. 6 is a timing chart showing an example of a bus timing to be created.

FIG. 14 is a configuration diagram illustrating a second example of a system using the first or second embodiment of the bus control device of the present invention.

FIG. 15 is a timing chart showing an example of a bus control operation in a second example of the system using the bus control device according to the first or second embodiment of the present invention.

FIG. 16 is a block diagram showing a third embodiment of the bus control device of the present invention.

FIG. 17 is a block diagram showing a fourth embodiment of the bus control device of the present invention.

FIG. 18 is a configuration diagram illustrating an example of a system using a bus control device according to the third or fourth embodiment of the present invention.

FIG. 19 is a configuration diagram showing an example of a system formed on a semiconductor device using the bus control device of the present invention.

FIG. 20 is a configuration diagram showing another example of a system formed on a semiconductor device using the bus control device of the present invention.

[Explanation of symbols]

11: access timing definition register group, 12: access timing selection circuit, 13: bus timing generation sequencer, 14: bus control line selection unit, 15: bus selection unit, 21: access timing register selection signal, 22
.. Timing designation signal, 23 bus control line, 24 address signal, 25 selection control signal, 26 basic timing signal, 27 bus control line selection signal, 28 bus selection signal, 31, 35 bus control unit, 32 CPU, 33 memory, 34, 38 I / O device, 36 bus master, 37 bus arbiter, 41 address bus, 42
... data bus, 43 ... control bus, 44 ... secondary address bus, 45 ... secondary data bus, 46 ... secondary control bus, 51 ... bus control unit, 61, 62, 63 ... semiconductor device, 71 ... internal address bus 72 internal data bus 73 internal control bus 74 internal secondary address bus 75 internal secondary data bus 76 internal secondary control bus 81 and 86 bus control unit 8
2 CPU unit 83 memory unit 84 88 I / O
Section, 85, 90 ... buffer, 87 ... bus master section, 89
… Bus arbiter section.

Claims (26)

[Claims] 1. A bus controller connected to a bus and accessing the bus in accordance with a bus cycle, an access timing defining means for holding a plurality of sets of setting values for defining an access timing, and an access timing defining means holding the set value. Access timing selecting means for selecting any of a set of setting values, and bus timing generating means for generating a bus cycle based on the set of setting values selected by the access timing selecting means. And a bus control device. 2. A bus control device connected to a bus and accessing the bus in accordance with a bus cycle, comprising: an access timing defining means for holding a plurality of sets of setting values for defining an access timing; A plurality of access timing selecting means for selecting any of a set of set values, and a plurality of bus timing generating means for generating a bus cycle based on the set of set values selected by the corresponding access timing selecting means. A bus control device comprising means. 3. A control target bus which is connected to a plurality of buses and controls a bus timing among the plurality of buses.
In a bus control device that accesses according to a bus cycle, an access timing defining means for holding a plurality of sets of setting values for defining an access timing, and a set value provided for the controlled bus and held by the access timing defining means And a plurality of bus timing generating means for generating a bus cycle based on the set of setting values selected by the corresponding access timing selecting means. A bus control device, characterized in that: 4. A control target bus which is connected to a plurality of buses and controls a bus timing among the plurality of buses.
In a bus control device that accesses according to a bus cycle, an access timing defining means for holding a plurality of sets of setting values for defining access timing, and one of a set of setting values held in the access timing defining means is selected. Access timing selecting means, bus timing generating means for generating a bus cycle based on a set of setting values selected by the access timing selecting means, and a bus generated by the bus timing generating means among the controlled buses A bus control device comprising bus selection means for selecting a bus to be accessed according to a cycle. 5. A bus control line selecting means for controlling a selected control line according to a bus cycle created by said bus timing generating means, wherein said access timing selecting means is created by said bus timing generating means. 5. The bus control device according to claim 1, wherein the bus control line selecting means selects a control line to be controlled in accordance with a bus cycle. 6. The access timing defining unit holds a set value defining an access timing as a designation table, and the access timing selection unit selects a set of set values from the designated table. The bus control device according to any one of claims 1 to 5, wherein 7. The access timing defining means according to claim 1, wherein said set value is determined based on a bus cycle start position.
7. The bus control device according to claim 1, wherein a timing of a change point of each bus control line is defined. 8. The apparatus according to claim 1, wherein said access timing defining means defines, as the set value, a timing between transition points of any one of the bus control lines. The bus control device according to the paragraph. 9. The access timing selecting means selects one of a set of set values held in the access timing defining means according to address data at the time of bus access. The bus control device according to claim 8. 10. The access timing selecting means,
9. The apparatus according to claim 1, wherein one of a set of set values held in said access timing defining means is selected by an external selection control signal. Bus control device. 11. The bus timing generating means according to claim 1, wherein said bus timing generating means generates a bus cycle such that access to a plurality of input / output devices connected to said bus is performed in the same bus cycle. Item 11. The bus control device according to any one of items 10. 12. The bus timing generator according to claim 1, wherein the bus timing generator generates a bus cycle in accordance with a clock signal having an internal operating frequency higher than the operating frequency of the bus. A bus control device as described. 13. A semiconductor device comprising an internal bus and a bus control device for accessing said internal bus in accordance with a bus cycle, wherein said bus control device holds a plurality of sets of set values defining access timing. Defining means, access timing selecting means for selecting any of a set of setting values held in the access timing defining means, and a bus based on the set of setting values selected by the access timing selecting means. A semiconductor device having a bus timing generating means for generating a cycle. 14. A semiconductor device comprising an internal bus and a bus control device for accessing said internal bus in accordance with a bus cycle, wherein said bus control device holds a plurality of sets of set values defining access timing. Defining means, a plurality of access timing selecting means for selecting any of a set of setting values held in the access timing defining means, and a set of setting values selected by the corresponding access timing selecting means. A semiconductor device having a plurality of bus timing generating means for generating a bus cycle. 15. A semiconductor device comprising: a plurality of internal buses; and a bus control device that accesses a control target bus for controlling bus timing among the plurality of internal buses in accordance with a bus cycle. The apparatus includes: an access timing defining unit that holds a plurality of sets of setting values that define an access timing; and one of a set of setting values that is provided corresponding to the control target bus and held by the access timing defining unit. And a plurality of bus timing generating means for generating a bus cycle based on a set of setting values selected by the corresponding access timing selecting means. . 16. A semiconductor device comprising a plurality of internal buses and a bus control device for accessing a bus to be controlled for controlling bus timing among the plurality of internal buses in accordance with a bus cycle. Access timing defining means for holding a plurality of sets of setting values to be specified, access timing selecting means for selecting any of the set of setting values held in the access timing defining means, and selection by the access timing selecting means Bus timing generating means for generating a bus cycle based on the set of set values, and bus selecting means for selecting a bus to be accessed according to the bus cycle generated by the bus timing generating means among the plurality of buses. A semiconductor device characterized by the above-mentioned. 17. A bus control line selecting means for controlling a selected control line in accordance with a bus cycle created by said bus timing generating means, wherein said access timing selecting means is created by said bus timing generating means. 14. The bus control line selecting means for selecting a control line to be controlled according to a bus cycle.
The semiconductor device according to claim 16. 18. The semiconductor device according to claim 13, wherein a part or all of said internal bus is connectable to an external bus. 19. The semiconductor device according to claim 13, comprising a plurality of said bus control devices. 20. The access timing defining means,
20. The apparatus according to claim 13, wherein a set value that defines access timing is held as a designation table, and said access timing selection means selects a set of set values from said designation table. 13. The semiconductor device according to item 9. 21. The access timing defining means,
21. The semiconductor device according to claim 13, wherein a timing of a change point of each bus control line is defined based on a bus cycle start position as the set value. 22. The access timing defining means,
14. The method according to claim 13, wherein the set value defines a timing between transition points of any one of the bus control lines.
The semiconductor device according to claim 20. 23. The access timing selecting means,
23. The method according to claim 13, wherein one of a set of set values held in said access timing defining means is selected according to address data at the time of bus access. Semiconductor device. 24. The access timing selecting means,
23. The apparatus according to claim 13, wherein one of a set of set values held in said access timing defining means is selected by an external selection control signal. Semiconductor device. 25. The bus timing generating means according to claim 1, wherein the bus cycle is generated such that access to a plurality of input / output devices connected to the internal bus or the external bus is performed in the same bus cycle. The semiconductor device according to any one of claims 13 to 24. 26. The bus timing generator according to claim 13, wherein the bus timing generator generates a bus cycle in accordance with a clock signal having an internal operating frequency higher than the operating frequency of the bus. 13. The semiconductor device according to claim 1.