JP2000330498A - Driving method for liquid crystal display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress timewise variations in the output of a shift register which are generated by discrepancy of timing of risings and fallings of two-phase shift clock pulses of a horizontal driver. SOLUTION: In this driving method, DC components of shift clock pulses are cut in states in which they are in small amplitudes and biases are added to them and they are supplied to a liquid crystal display panel 7 so that the discrepancy of timing of risings and fallings of shift clock pulses driving shift registers 10a, 10b of the liquid crystal display panel 7 becomes small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for driving a liquid crystal display panel.

[0002]

2. Description of the Related Art A current liquid crystal display panel generally requires a power supply of 10 V or more. The pulse for operating the horizontal / vertical driver built in the liquid crystal display panel also needs to have the same amplitude as the above-mentioned power supply, and 10 V
The pulse is input with the above large amplitude. Also, general IC
In order to drive a liquid crystal display panel with a small amplitude pulse of about 5 V, a level shifter is built in the liquid crystal display, and a power supply voltage of 10 V or more may be generated by the level shifter.

A horizontal / vertical driver is constituted by a shift register, and the shift register is operated by a two-phase shift clock pulse. The shift register operates at the rise and fall of the two-phase shift clock pulse. If the phase relationship between the two-phase shift clock pulse is not appropriate, the operation of the shift register causes a problem in image display of the liquid crystal display device. . In particular, vertical stripes called fixed patterns may occur due to the operation of the shift register of the horizontal driver.

A description will be given below with reference to a conventional liquid crystal display panel and a driving circuit.

FIG. 6 is a configuration diagram of a conventional liquid crystal display panel and a driving circuit, and FIG. 7 is a diagram showing a timing chart thereof. In FIG. 6, 1 is a video signal input terminal, 2 is a drive circuit, 3 is a 5V power supply circuit, 4 is a video signal processing circuit, 5a, 5b, 5c, 5d, 5e, 5f are level shifters, 6a, 6b, 6c, 6d, 6e, 6f are video signal output buffers, 7 is a liquid crystal display panel, 8
Is a horizontal driver, 9 is a vertical driver, 10a and 10b are shift registers, 11 is a signal line, 12 is a gate line, 13
Denotes a pixel portion.

The liquid crystal display panel 7 shown in FIG.
The horizontal driver 8 has one shift register 10a, and the vertical driver 9 has one shift register 10b.
Two-phase shift clock pulses are input. Therefore, two shift clock pulses are input to the horizontal driver 8 and two shift clock pulses are input to the vertical driver 9. A shift start pulse for controlling the operation start of the shift registers 10a and 10b is supplied to the horizontal driver 8 and the vertical driver 9 by 1 respectively.
Is entered.

The drive circuit 2 generates the shift clock pulse, the shift start pulse, and the video signal for driving the horizontal driver 8 and the vertical driver 9 of the liquid crystal display panel 7 based on the video signal of the video signal input terminal 1.
The shift clock pulse and the shift start pulse need to be increased in amplitude up to the power supply of the liquid crystal display panel 7 and supplied to the shift registers 10a and 10b, the horizontal driver 8 and the vertical driver 9, but the output of the power supply circuit 3 is 5
Since the voltage is V, the pulse amplitude of 5 V needs to be boosted to the power supply voltage of the liquid crystal display panel 7. Then, the voltage is boosted using the level shifters 5a, 5b, 5c, 5d, 5e, and 5f, and output to the liquid crystal display panel 7.

The shift register 10a of the horizontal driver 8,
The shift register 10b of the vertical driver 9 is shown in FIG.
As shown in the timing charts shown in b, c, d, e, and f, the operation is performed by two pulses having opposite polarities (hereinafter, referred to as a two-phase shift clock pulse) and the shift start pulse shown in FIGS. 7A, 7B, and 7C show pulses related to the horizontal driver, and FIGS. 7D, 7E, and 7F show pulses related to the vertical driver. Shift register 10a,
From the operation result of 10b, video information to each pixel of the pixel portion is transmitted to the pixel portion 13 by the signal line 11 and the gate line 12, and an image is displayed. In the liquid crystal display panel 7 shown in FIG. 6, the number of video signal inputs is six because the video information for six pixels is selected at a time in the horizontal direction.

Since the shift registers 10a and 10b operate at the rising and falling edges of the two-phase shift clock pulse, the shift registers 10a and 10b operate at the rising and falling edges of the two-phase shift clock pulse.
If the fall timings do not substantially match, a temporal variation occurs in the operation of the shift registers 10a and 10b,
Affects the displayed image. In particular, the shift register 10a of the horizontal driver 8 greatly affects the display image, and it is necessary to suppress the rising and falling timings of the shift clock pulse to several ns or less.

FIG. 8 is a configuration diagram of the horizontal driver 8 of the liquid crystal display panel 7, and FIG. 9 is a timing chart thereof.

In FIG. 8, 14a, 14b, 14c, 1
4d, 14e, 14f, 14g, 14h, 14i, 14
j, 14k, 141, 14m, 14n are transfer gates, 15a, 15b are shift clock pulse input terminals, 16 is a shift start pulse input terminal, 17a, 1
7b, 17c, 17d, 17e, 17f are video signal input terminals, 18a, 18b, 18c, 18d, 18e, 18
f, 18g, 18h, 18i, 18j, 18k, 18l
Is a signal line output. Shift clock pulse input terminal 1
2a large amplitude 14.5Vp- applied to 5a, 15b
By the p shift clock pulse, the transfer gates 14a and 14b enter a conductive state or a high impedance state. Here, when the transfer gates 14a of the odd-numbered stages are conducting, the transfer gates 14b of the even-numbered stages are in a high-impedance state. 14b
Becomes conductive. Such an operation is repeated by the shift clock pulse. The shift start pulse is normally at the L (low) level, and the H (high) level is input at the start of the shift register operation. This H-level information is propagated by the operation of the transfer gates 14a and 14b, and the shift register output A and the shift register output B
The output of the shift register 10a as shown in FIG.

The output of the shift register 10a is connected to transfer gates 14c, 14d, 14e, 14f, 1
4g, 14h, 14i, 14j, 14k, 141, 14
m, 14n are input to the gates of the shift register 10a.
Video signal input terminals 17a, 17
b, 17c, 17d, 17e, and 17f are supplied to the signal line outputs 18a, 18b, 18c, 18d, 1
8e, 18f, 18g, 18h, 18i, 18j, 18
k, 181 and send video information to the pixel. Although only two stages of the transfer gates 14a and 14b are shown in the figure, there are usually about 100 stages and about 100 outputs of the shift register 10a.

[0013]

The transfer gates 14a and 14b switch between the conductive state and the high impedance at the rising and falling edges of the two-phase shift clock pulse input terminals 15a and 15b. As shown in FIG. 9, when there is a difference (phase difference) between the rising and falling timings of the shift clock pulses b and c, the state of the transfer gates 14a and 14b becomes indefinite, and either the conductive state or the high impedance state is performed. I do not know if it will be. Therefore, the output of the shift register 10a varies with time. For example, the output of the shift register A of the odd-numbered stage is long at the H level, and the output of the shift register B of the even-numbered stage is short.

In both the internal and external level shifters of the liquid crystal display panel, especially in a level shifter that handles a shift clock for a horizontal driver, attention must be paid to the phase relationship between two-phase clocks. If this phase difference relationship is not considered, the operation of the shift register varies with time, and vertical stripes occur in the displayed image.

As described above, in the conventional method of driving a liquid crystal display panel, the phase difference between the rise and fall of the two-phase shift clock pulses b and c of the horizontal driver is determined by several n.
If the value is not less than s, the output of the shift register 10a will vary with time, affecting the displayed image and causing vertical stripes.

The present invention has been made in view of the above, and has as its object to provide a high-quality liquid crystal display panel in which vertical stripes are not generated on a display screen.

[0017]

In order to achieve the above-mentioned object, the present invention provides a shift clock pulse for driving a shift register of a liquid crystal display panel, the shift clock pulse having a small phase difference between rising and falling edges. In the state of small amplitude, the DC component is cut, a bias is applied, and the DC component is supplied to the liquid crystal display panel.

In the conventional method of driving a liquid crystal display panel, a shift clock pulse having a small amplitude is supplied to the liquid crystal display panel with a large amplitude by a level shifter. In the present invention, a small-amplitude shift clock pulse input to the level shifter is converted into a DC signal by a DC cut circuit.
The components are cut, biased, and output to a liquid crystal display panel.

The reason why the bias is applied to the shift clock pulse is that a voltage higher than the threshold value of the shift register of the liquid crystal display panel cannot be applied to the shift register if the amplitude remains small. A level shifter for increasing the amplitude generally has long rise and fall times and does not have the same time, so that the phase difference becomes large.

More specifically, a driving method of a liquid crystal display panel according to a first aspect of the present invention is characterized in that a shift register for applying a pulse for selecting a video signal to be supplied to the liquid crystal display panel has a small amplitude of about 5 V or less. , A DC component is cut, and a biased two-phase shift clock pulse is supplied, and the phase difference between the two-phase shift clock pulses is 5 ns or less.

According to a second aspect of the present invention, in the method for driving a liquid crystal display panel, the shift register has a plurality of shift registers.

According to the structure described in the claims, it is possible to supply the shift clock pulse to the shift register of the liquid crystal display panel with a small amplitude of about 5 V, so that the phase difference between the rise and fall of the shift clock pulse is obtained. Can be reduced by the level shifter that increases the amplitude.

[0023]

FIG. 1 is a diagram showing a liquid crystal display panel and a driving circuit thereof according to a first embodiment of the present invention.

In FIG. 1, the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, what differs from FIG. 6 is that the level shifters 5a, 5b, 5
Instead of c, 5d, 5e, 5f, DC cut bias circuits 19a, 19b, 19c, 19d, 19e, 19f
Is provided.

In the circuit of FIG. 1, DC cut bias circuits 19a, 19b, 19c, 19d, 19e, 19f
As a result, a pulse obtained by applying a bias while keeping the output amplitude of 5 V from the power supply circuit 3 is supplied to the liquid crystal display panel 7. DC cut bias circuits 19a, 19b, 1
9c, 19d, 19e, and 19f, as shown in FIG.
After a DC component of the input signal is cut by the capacitor C, a bias potential (R2 / (R1 + R2) × VDD) is created by the bias resistors R1 and R2, added to the input signal having lost the DC component, and output. Circuit.

Two-phase shift clock pulses 15a, 15b
Since the 5Vp-p shift clock pulse after the DC cut inputted to the shift start pulse 16 is set to a pulse that crosses over the threshold value of the buffer, the buffer can output L level and H level. , The subsequent transfer gates 14a and 14b can be driven. The transfer gate in the subsequent stage is driven by the same pulse of 10 V or more by the power supply of the liquid crystal display panel.

FIGS. 3A, 3B, 3C, 3D, 3E, and 3F show DC cut bias circuits 19a, 19b, 19c, 19d, and 19, respectively.
e and 19f show output pulses.

FIG. 4 shows the liquid crystal display panel 7 of FIG.
The configuration of the horizontal driver 8 is the same as that of FIG.
The same numbers are assigned and the description is omitted.

Since the shift clock pulse is a small-amplitude pulse of about 5 V or less, the rise and fall times of the pulse are short, and the level shifters 5a, 5b, 5c, and 5c shown in FIG.
Since the difference between the rise time and the fall time caused by 5d, 5e, and 5f is less than about 5 V, the timing shift between the rise and fall of the shift clock pulse can be reduced.

In this embodiment, the bias is generated by the resistance ratio for simplicity. However, a power supply circuit may be provided for the bias.

The shift clock pulse may have four or six phases, and can be similarly applied to other signal pulses requiring timing accuracy.

In the above embodiment, the case where the horizontal driver 8 has one shift register 10a and the vertical driver 9 has one shift register 10b has been described, but the horizontal driver 8 and the vertical driver 9 have one shift register 10b. A plurality of shift registers may be provided.

[0033]

According to the driving method of the liquid crystal display panel of the present invention, the two-phase shift clock pulse synchronized with the video signal is supplied to the shift register for supplying the pulse for selecting the video signal to be supplied to the liquid crystal display panel. The DC component is cut with a small amplitude less than or equal to about and a bias is applied, and the phase difference between the two-phase shift clock pulses is 5n.
s or less, the rising edge of the shift clock pulse supplied to the liquid crystal display panel,
The falling timing shift can be reduced.

For this reason, the temporal variation in the operation of the shift register of the liquid crystal display panel is reduced, and a high-quality image display in which vertical stripes as display deterioration cannot be recognized can be obtained.

[Brief description of the drawings]

FIG. 1 is a drive circuit diagram of a liquid crystal display panel according to an embodiment of the present invention.

FIG. 2 is a DC cut bias circuit diagram according to the embodiment of the present invention.

FIG. 3 is a timing chart of a shift register according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a horizontal driver of the liquid crystal display panel according to the embodiment of the present invention.

FIG. 5 is a timing chart of a shift register according to the embodiment of the present invention.

FIG. 6 is a drive circuit diagram of a conventional liquid crystal display panel.

FIG. 7 is a timing chart of a shift register of a conventional liquid crystal display panel.

FIG. 8 is a configuration diagram of a conventional horizontal driver of a liquid crystal display panel.

FIG. 9 is a timing chart of a shift register of a conventional liquid crystal display panel.

[Explanation of symbols]

 Reference Signs List 1 video signal input terminal 2 drive circuit 3 5V power supply circuit 4 video signal processing circuit 5a level shifter 5b level shifter 5c level shifter 5d level shifter 5e level shifter 5f level shifter 6a video signal output buffer 6b video signal output buffer 6c video signal output buffer 6d video signal output buffer 6e Video signal output buffer 6f Video signal output buffer 7 Liquid crystal display panel 8 Horizontal driver 9 Vertical driver 10a Shift register 10b Shift register 11 Signal line 12 Gate line 13 Pixel portion 14a Transfer gate 14b Transfer gate 14c Transfer gate 14d Transfer gate 14e Transfer gate 14f transfer gate 14g transfer gate 14h transfer -Gate 14i transfer gate 14j transfer gate 14k transfer gate 14l transfer gate 14m transfer gate 14n transfer gate 15a shift clock pulse input terminal 15b shift clock pulse input terminal 16 shift start pulse input terminal 17a video signal input terminal 17b video signal input terminal 17c video signal Input terminal 17d Video signal input terminal 17e Video signal input terminal 17f Video signal input terminal 18a Signal line output 18b Signal line output 18c Signal line output 18d Signal line output 18e Signal line output 18f Signal line output 18g Signal line output 18h Signal line output 18i Signal line output 18j Signal line output 18k Signal line output 18l Signal line output 19a DC cut bias circuit 19b DC Ttobaiasu circuit 19c DC cut bias circuit 19d DC cut bias circuit 19e DC cut bias circuit 19f DC cut bias circuit

Claims (2)

[Claims] 1. A shift register for sending a video signal to a pixel portion of a liquid crystal display panel is supplied with a biased two-phase shift clock pulse in which a DC component is cut with a small amplitude of about 5 V or less and a bias is applied. A method for driving a liquid crystal display panel in which a phase difference between two-phase shift clock pulses is 5 ns or less. 2. The method according to claim 1, wherein the shift register has a plurality of shift registers.