JP2000324180A - Data receiving circuit for polar rtz signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiving circuit for surely performing data reception in a non-contact bus system. SOLUTION: This data receiving circuit for a non-contact bus system is provided with an input terminal 10 for inputting a polar RTZ signal, a reference voltage supply wire 11, voltage comparators 12 and 13 having a preliminarily set offset voltage Voffs, an RS-FF 14 and an output terminal 15. When voltage inputted to the terminal 10 surpasses a threshold voltage shown by the sum of the voltage Vref of the wire 11 and the voltage Voffs, the comparator 12 sets the output level of an output terminal 15 connected to an RS-FF 14 to an H level. The comparator 13 sets the output level of the terminal 15 connected the RS-FF 14 to an L level when the voltage inputted to the terminal 10 falls down the threshold voltage shown by the difference between the voltage Vref of the wire 11 and the voltage Voffs. The voltage Voffs is defined as smaller than the absolute value of the amplitude of received data in this bus system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving circuit for a non-contact bus and an information processing apparatus provided with the same.

[0002]

2. Description of the Related Art In recent years, in information processing apparatuses such as computers equipped with a bus system, the speed of a bus and the capacity of a memory have been increased, and the transfer rate in the bus system has been increased from several hundred mega bps to giga bps. A table has been requested. Further, the number of functional modules connected to the bus system is increasing. For example, a memory module is required to have a system with a total capacity of the order of gigabytes.

When the number of functional modules connected to the bus wiring increases, the effective characteristic impedance of the bus wiring decreases, and an impedance mismatch occurs between the functional module and the bus wiring, resulting in an increase in signal waveform distortion. This is an obstacle when speeding up the bus system.

As a technique for solving this problem, there is a technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-141079. In this technique, functional modules connected to a bus line are connected in a non-contact manner using crosstalk. FIG. 13 shows a configuration example of this technique.

[0005] Reference numeral 80a is a bus wiring. Reference numeral 80b denotes a stub wiring, and the bus wiring 80a and the wiring are close to each other only in a section of the length L, and a directional coupler (or simply, a coupler) is formed at a portion indicated by 86. 81a and 81b are functional modules, which are connected to a bus wiring 80a and a stub wiring 80b, respectively. 82a, 82
b is an integrated circuit, each of which has a function module 81
a, 81b. 83a and 83b are transmission circuits, which are built in the integrated circuits 82a and 82b.
84a and 84b are receiving circuits.
a, 82b. 85a and 85b are terminating resistors. One end of 85a is connected to the bus wiring 80a, and the other end is connected to a terminating power supply. One end of 85b is connected to the stub wiring 80b, and the other end is connected to the terminal power supply. A terminating voltage of the voltage Vt is supplied to the terminating resistors 85a and 85b. This voltage Vt is a voltage set from 0 V to the power supply voltage (waveform amplitude of the output signal).

In this example, crosstalk occurs in a portion where the bus wiring 80a and the stub wiring 80b are close to each other in a section of length L. This crosstalk signal is generated when the pulse signal output from the transmission circuit 83a or 83b passes through the directional coupler. In this example, the rear crosstalk among the generated crosstalk signals is received.

The bus wiring 80 in the directional coupler 86
FIG. 13 shows the timing at which signals are input to and output from the stub wiring 80b.

The signal output from the transmission circuit 83a to the bus wiring 80a (or from the transmission circuit 83b to the stub wiring 80b) is represented by a signal level state of either H level or L level (zero level). The same signal level is maintained during a period in which no data transition occurs. Such a signal is generally called NRZ (Non Return to Return).
Zero) signal.

On the other hand, the crosstalk signal generated on the stub wiring 80b (or the bus wiring 80a) by the directional coupler 86 holds a zero level (or the termination voltage Vt) during a period in which no data transition occurs. hand,
When a data transition occurs, the level changes. After a certain time elapses after the signal level change, the signal level returns to the original zero level. Such a signal is generally referred to as RTZ (Re
(Turn To Zero) signal. The level of the crosstalk signal transits to two levels, higher (+) or lower (-) than the zero level, depending on the direction in which the level of the NRZ signal passing through the directional coupler 86 changes. Such a signal is called a polar RTZ signal.

The crosstalk signal (polarized RTZ signal) is received by the receiving circuits 84a and 84b, and is decoded into an original signal (NRZ signal).

In this example, there is only one bus wiring 80a. However, when the bus is used for a data bus of an actual system, for example, if the data bus width is 64 bits, there are 64 sets of bus wirings. Also, in this example, only one stub wiring 80b is described, but in an actual system, there are as many modules as are connected to the bus wiring 80a. Although not shown here, the bus lines 80a and 80b are provided on a backplane board or the like, and the modules 81a and 81b are also connected to the backplane board. Either or both of the integrated circuits 82a and 82b may be provided directly on the backplane substrate.

If the bus wiring 80a and the stub wiring 80b are directly connected, as in a normal bus wiring, the stub wiring 80b acts as a load capacitance, so that the effective characteristic impedance of the bus wiring 80a is reduced. At the branch portion of the stub wiring. This causes waveform distortion of a signal passing through the bus wiring 80a. further,
The waveform distortion is further increased by increasing the number of modules connected to the bus wiring 80a.

By using the present technology, it is possible to suppress a decrease in effective characteristic impedance, which is a cause of waveform distortion. Further, even if the number of modules is increased, the waveform distortion can be suppressed low, and it is possible to simultaneously increase the number of modules and increase the speed of the bus system.

[0014]

In the prior art, the level of the crosstalk signal transmitted via the bus wiring is about 20% or less of the signal level before the crosstalk even when the backward crosstalk is used. is there. In addition, the signal level may be distorted due to external noise, fluctuations in the power supply voltage, or the like, and the signal waveform after crosstalk may be distorted. In some cases, data may not be received properly.

An object of the present invention is to provide a receiving circuit capable of reliably performing data transmission in a contactless bus system that handles a polar RTZ signal.

[0016]

According to one aspect of the present invention, there is provided a data receiving circuit for use in a polar RTZ signal, wherein the data receiving circuit comprises 10% of an input signal amplitude. It has two voltage comparators having an offset value of not less than 50% and one RS flip-flop circuit, and outputs signals from the two voltage comparators to a Set input terminal of the RS flip-flop and a Res, respectively.
A data receiving circuit is provided which is connected to an et input terminal and converts a polar RTZ signal into an NRZ signal.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described.

FIG. 1 is a configuration diagram of a data receiving circuit according to the present invention.

In this embodiment, a description will be given of a case where the receiving circuit is built in the integrated circuits 134a and 134b of FIG. 13 described above.

Reference numeral 10 denotes an input terminal, which is a bus wiring 8 shown in FIG.
0a or 80b. This input terminal 10
Is input with a crosstalk waveform generated when a signal output from the transmission circuit 83a or 83b is transmitted between the bus lines 80a and 80b.

Reference numeral 11 denotes a reference voltage supply line. The wiring 11 is a common wiring connected to other circuits not shown here. The voltage of the reference voltage supply line 11 is set to the same voltage as the terminal voltage supplied to the terminal resistors 85a and 85b.

Reference numerals 12 and 13 are voltage comparators. The voltage comparators 12 and 13 have two input terminals (a positive input terminal (+) and a negative input terminal (-)) and one output terminal.

Reference numeral 14 denotes an RS flip-flop (RS-F).
F). The RS-FF 14 has a set input terminal (S), a reset input terminal (R), and an output terminal (Q). When the H level is input to the set input terminal S, the level of the output terminal Q is set to the H level. When the H level is input to the reset input terminal R, the level of the output terminal Q is set to the L level. Both levels of the set input terminal S and the reset input terminal R are L
In the case of (steady state), the level of the output terminal Q maintains the previous state.

The input terminal 10 is connected to a positive input terminal of a voltage comparator 12 and a negative input terminal of a voltage comparator 13. The reference voltage supply line 11 is connected to the voltage comparator 12
And the positive input terminal of the voltage comparator 13 are connected.

The output terminals of the voltage comparators 12 and 13 are connected to the set input terminal (S) and the reset input terminal (R) of the RS-FF 14, respectively. RS-
An output terminal (Q) of the FF 14 is provided with a data output terminal 16 of the present receiving circuit.

FIG. 3 is a graph showing the input / output voltage characteristics of the voltage comparator 12. Although the voltage comparator 13 has the same characteristics as the voltage comparator 12, the characteristics of the voltage comparator 12 or 13 may be different according to the signal waveform to be received.

The horizontal axis of the graph of FIG. 3 is the voltage of the input terminal 10 (the voltage of the positive input terminal of the voltage comparator 12 and the input voltage), and the vertical axis is the voltage of the output terminal of the voltage comparator 12. .

A reference voltage is supplied to a negative input terminal of the voltage comparator 12 through a reference voltage supply line. In the present embodiment, this reference voltage is assumed to be Vref.

When the input voltage is lower than the threshold voltage, the voltage comparator 12 outputs an L level from the output terminal. Also, if the input voltage is higher than the threshold voltage,
H level is output from the output terminal.

Here, the threshold voltage of the voltage comparator 12 is a voltage obtained by adding the offset voltage Voffs to the reference voltage Vref.

In a general voltage comparator, the threshold voltage is almost the same as the reference voltage Vref, and the offset voltage is almost zero. In the voltage comparator used in the present invention, the offset voltage Voffs
Is different from a general voltage comparator.

Next, the operation of the receiving circuit will be described with reference to FIG.

FIG. 4 is a timing chart showing the transition of the signal level in each part of the receiving circuit of FIG.

The waveforms at each stage in FIG.
3a or 83b output terminal (DRV), input terminal 10
(IN), output (A) of voltage comparator 12, voltage comparator 1
3 (B), observed at output terminal 15 (OUT). Hereinafter, each observation point is referred to as DRV, IN, A, B,
OUT.

When data such as DRV shown in FIG. 4 is output from the transmission circuit 83a, crosstalk occurs between the wirings 80a and 80b, and the crosstalk waveform is input to the input terminal 10 in the reception circuit 84b. You. The waveform is shown as IN in FIG. In the crosstalk waveform at IN, a pulse signal 41 is generated where the output of the transmission circuit 83a transitions from L level to H level. Also, where the output of the transmission circuit 83a transitions from the H level to the L level, a pulse signal shown at 42 is generated. The output signal from the transmission circuit 83a is H level, L level
When there is no transition between levels (at steady state), IN
Is maintained at the termination voltage Vt.

The operation of each of the pulse signals 41 and 42 at IN will be described. It is assumed that the reference voltage Vref supplied to the receiving circuit is set to the same voltage as the termination voltage Vt.

When the pulse signal 41 is input to the input terminal 10 and the absolute value of the amplitude of the pulse signal exceeds the offset voltage Voffs of the voltage comparator 12, the voltage comparator 12
A pulse signal 43 is output from the output terminal (A).

This pulse signal 43 is generated only during the period when the absolute value of the signal amplitude at IN exceeds the offset voltage Voffs. When the pulse signal at IN returns to the steady state, the waveform at A returns to the L level.

When the pulse signal 43 is generated from the output terminal of the voltage comparator 12, the output Q of the RS-FF 14 and the voltage of the output terminal 16 are set to the H level.

When the pulse signal 42 is input to the input terminal 10 and the absolute value of the amplitude of the pulse signal exceeds the offset voltage Voffs of the voltage comparator 13, the voltage comparator 13
A pulse signal 44 is output from the output terminal (B).

This pulse signal 44 is generated only during the period when the absolute value of the signal amplitude at IN exceeds the offset voltage Voffs. When the pulse signal at IN returns to the steady state, the waveform at B returns to the L level.

When the pulse signal 44 is generated from the output terminal of the voltage comparator 13, the output Q of the RS-FF 14 and the voltage of the output terminal 16 are set to L level.

Here, the voltage comparator offset voltage Vof
fs is set to a voltage lower than the absolute value of the amplitude of the crosstalk waveform generated in the wirings 130a and 130b. If noise or fluctuations in the terminal voltage can be considered, it is necessary to consider these voltage fluctuations. For example,
The amplitude of the crosstalk waveform is 200m around the termination voltage
When the voltage fluctuation such as V and noise is 50 mV, the offset voltage Voffs may be set to be between 50 mV and 150 mV.

With these two operations, the crosstalk signal can be decoded into the original signal in the receiving circuit of the present embodiment.

Next, the configuration of the voltage comparator 12 will be described with reference to FIG. Note that the voltage comparator 13 is a voltage comparator 1
It has the same configuration as 2. That is, this is a circuit having the same wiring as a general voltage comparator (comparator).

FIG. 5 shows that the voltage comparator 12 is a MOS-FE
FIG. 3 is a configuration diagram in the case of configuring with T.

51 and 52 are P-channel MOSFETs
(Hereinafter, referred to as PMOS). 53, 54, 55
Is an N-channel MOSFET (hereinafter, NMOS).

One MOSFET has one gate terminal (G), one source terminal (S), and one drain terminal (D). In the figure, the terminals extending in the horizontal direction are gate terminals, and the terminals extending in the vertical direction are source terminals and drain terminals. In the PMOS, the terminal on the high potential side (the side near the power supply terminal) is the source terminal. In the NMOS, the terminal on the low potential side (the side near the ground terminal) is the source terminal.

The source terminals of the PMOS 51 and the PMOS 52 are connected to a power supply (VDD).

The gate and drain terminals of the PMOS 51 are connected.

The drain terminal of the PMOS 51 and the NMOS
53 are connected to the drain terminal. Also, PMO
The drain terminal of S52 and the drain terminal of NMOS 54 are connected to each other. Furthermore, PMOS22, NMOS
The output terminal of the voltage comparator is provided at 24 drain terminals.

The positive input terminal of the present voltage comparator is provided at the gate terminal of the NMOS 53. The negative input terminal of the voltage comparator is provided at the gate terminal of the NMOS 54.

The gate terminal of the PMOS 55 is supplied with a bias voltage or a power supply voltage (VDD).

The source terminal of the NMOS 55 is grounded (GND
It is connected to the.

In this voltage comparator, NMOS 53 and N
The channel width of the MOS 54 is set to the same value.

Here, the difference from the general voltage comparator is that when the channel width of the PMOS 51 is W1 and the channel width of the PMOS 52 is W2, W1 and W2 are set so as to satisfy the following relationship. That is.

[0057]

W1> W2 (Equation 1) With this setting, the voltage comparator 12 can have the offset voltage Voffs. W1, W2
Is increased, the offset voltage Voffs can be increased.

In the receiving circuit of the present invention, since the voltage at the positive input terminal and the voltage at the negative input terminal of the voltage comparator in the steady state are the same, the output is undefined in a normal voltage comparator that does not wait for an offset voltage.

By providing the voltage comparator with the offset voltage Voffs, the output of the voltage comparator can be kept stable even in the steady state of the receiving circuit.

Next, another configuration example of the voltage comparator will be described with reference to FIG.

FIG. 6 is a diagram showing a voltage comparator used in the present embodiment, in which the offset voltage of the voltage comparator is variable.

The difference of this configuration from FIG. 5 is that the circuit of FIG. 5 is provided with a PMOS 60, a PMOS 61 and an input terminal (CTRL) for setting the offset voltage Voffs.

By setting the voltage of CTRL to a value between 0 V (GND voltage) and the power supply voltage VDD, CT
Offset voltage V of the voltage comparator corresponding to the voltage of RL
offs can be set.

By configuring the voltage comparator in this way,
Since the offset voltage Voffs can be dynamically set, the offset voltage can be adjusted in accordance with the signal amplitude even after the receiver circuit is mounted on the device.

The receiving circuit of the embodiment can also be used as a hysteresis amplifier having a hysteresis voltage Vhys due to the offset voltage of the voltage comparator 12 and the voltage comparator 13. This hysteresis voltage Vh
ys is the offset voltage of the comparator 12 and the voltage comparator 1
3 is a voltage obtained by adding the offset voltage.

As described above, by using the receiving circuit of the present invention, a weak polar RTZ such as a crosstalk signal can be obtained.
Signals can be received, and a non-contact bus system capable of high speed and multi-module can be realized.

Next, a second embodiment of the present invention will be described with reference to FIGS.

In the first embodiment, the bus wiring 80
a and 80b are configured as one (single end), but the bus lines 80a and 80b
However, the present invention can also be applied to a case where a pair of differential lines is used.

FIG. 12 is a diagram showing the configuration when the present invention is applied to a differential line.
Shown in In this configuration, the bus lines 80c and 80c in FIG.
0d corresponds to the bus wiring 80a in FIG. FIG.
The second stub wirings 80e and 80f correspond to the stub wiring 80b in FIG. Further, the transmission circuits 83c and 83d in FIG. 12 correspond to the transmission circuit 83a in FIG. The receiving circuit 91 in FIG. 12 corresponds to the receiving circuit 84b in FIG. In addition, the directional couplers 86a and 86b are provided in FIG.
Directional coupler 86.

The transmission circuits 83c and 83d are provided in the integrated circuit 82a. The receiving circuit is provided in the integrated circuit 82b.

Although not shown in FIG. 12, the integrated circuit 82a is provided on the module 81a.
The integrated circuit 82b is provided on the module 81b.

In this embodiment, two bus lines 80
c and 80d are a pair of differential wirings, 80c is a wiring on the positive logic side, and 80d is a wiring on the negative logic side. Also, two stub wirings 80e and 80f constitute a set of differential wirings.
Is a positive logic side, and 80f is a negative logic side.

A receiving circuit 91 to be applied to differential wiring
2 is shown in FIG.

In the receiving circuit 91 of FIG. 2, another input terminal 20 is provided instead of the reference voltage supply wiring 11 of FIG. The input terminal 20 is provided for each receiving circuit, like the input terminal 10.

The bus line 80e (positive logic side) is connected to the input terminal 1
0, the bus wiring 80f (negative logic side) is connected to the input terminal 20,
Connect each. The wiring on the negative logic side of the bus wiring is connected to the input terminal 20.

As described above, the receiving circuit of the present invention can be applied to the case of differential wiring, and the same receiving circuit can support both a single line (single-ended) and a differential line.

Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 7 shows an example of an information processing apparatus configured using a non-contact bus. The processor board (PB) shown at 71 is a central processing unit (CP) shown at 72.
U), a cache memory 73, and a bus bridge 74. The CPU 72, the cache memory 73, and the bus bridge 74 are mutually connected by a bus wiring 70d. This bus wiring 70d may be called a processor bus.

Reference numerals 70a and 70b denote bus lines, and these bus lines 70a and 70b may be called system buses.

The bus board 70a is connected to the processor board 7
Bus bridges 1 and 79 are connected. Although not shown, other boards and devices other than the processor board 71 may be added.

A memory board 75 (MB) having a bus bridge 77 and a bus bridge 7
8, and 79 are connected. Although not shown, other boards and devices other than the memory board 75 and the bus bridge 78 may be added.

The memory module 76 and the bus bridge 77
Are connected by a bus wiring 70c. This bus line 70c may be called a memory bus. Although not shown, the memory module 76 is configured by, for example, a printed wiring board on which one or more memory elements are mounted.

Bus lines 70a, 70b, 70c and 7
0d is constituted by a non-contact bus, and data transfer by this bus wiring is performed by an NRZ signal and a polar RTZ signal.

According to the present invention, the bus lines 70a, 70b, 70
c, device connected to 70d, bus bridge 74,
77, 78, 79, memory module 76, CPU 72
By applying the present invention to circuits connected to the non-contact bus such as the cache memory 73 and the like, a high-speed and high-reliability system can be constructed.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 11 shows another example of the configuration of a receiving circuit according to the present invention, in which the offset voltage is variable.
The receiving circuit of this configuration can perform the same operation as that of the receiving circuit of FIG. 1 and that the voltage comparators 12 and 13 are configured by the circuits shown in FIG.

The difference of this configuration from FIG. 1 is that the voltage comparator 1
That is, a voltage comparator 91 with a latch function is provided instead of the RS flip-flop circuits 14 and 13. Further, the voltage comparator with latch function 91 is provided with a Voffs setting terminal 92 for setting an offset voltage.

In the present embodiment, the case where the bus lines 80a and 80b are constituted by one (single end)
Has been described, but as shown in FIG.
The present invention can also be applied to a case where the pair of differential lines 0a and 80b is a pair of differential lines.

FIG. 10 shows the configuration of a receiving circuit when the bus wiring is a differential line. In the case of a differential line, it is assumed that each of the bus lines 80a and 80b includes a pair of lines on the positive logic side and the negative logic side.

In the receiving circuit of FIG. 10, another input terminal 20 is provided instead of the reference voltage supply wiring 11 of FIG. The input terminal 20 is provided for each receiving circuit, like the input terminal 10.

The wiring on the positive logic side of the bus wiring 80a or 80b is connected to the input terminal 10. The wiring on the negative logic side of the bus wiring is connected to the input terminal 20.

Next, a configuration example of the voltage comparator with latch function 91 according to the present embodiment will be described with reference to FIG.

FIG. 11 shows a configuration example of the voltage comparator with latch function 91 used in the present embodiment. The voltage comparator 91 with a latch function has a variable offset voltage, similarly to the voltage comparator described in the first embodiment with reference to FIG. This configuration differs from FIG. 6 in that the PMOSs 51a, 52a, 61a,
2a is further provided. PMOS 51a, 52
a, 61a and 62a are PMOSs 51 and 5 respectively.
2, 61 and 62. Further, the PMOS 51
a, 52a, 61a, and 62a, the offset voltage Vo
Assuming that the channel width of the PMOS 51a is W1a and the channel width of the PMOS 52a is W2a in order to have ffs2, W1a and W2a are set so as to satisfy the following equation (Equation 2).

[0094]

W1a> W2a (Equation 2) The offset voltage Voffs2 can be increased by increasing the difference between W1a and W2a. Note that the channel widths W1a and W2a correspond to the channel width W1 of the PMOS 51 and the channel width W2 of the PMOS 52, respectively. It is preferable that W1 and W1a and W2 and W2a have the same value, but different values may be used as long as the values satisfy the conditions of Expressions 1 and 2.

Further, the receiving circuit of the present embodiment is provided with a Voffs setting terminal 92 which is an input terminal for setting the offset voltages Voffs and Voffs2, and changes the voltage of the setting terminal 92 from 0V (GND voltage). By setting the value up to the power supply voltage VDD, the setting terminal 9
Offset voltages Voffs and Voff corresponding to the voltages of
fs2 can be set.

The receiving circuit according to the embodiment can also be used as a hysteresis amplifier having a hysteresis voltage Vhys based on offset voltages Voffs and Voffs2. This hysteresis voltage Vhys is P
The offset voltages Voffs set by the MOSs 51, 52, 61, and 62, and the PMOSs 51a, 52a,
Offset voltage Vo set by 61a and 62a
ffs2 is the added voltage.

As described above, even if the receiving circuit of the present embodiment is used, a receiving circuit capable of dynamically setting the offset voltage can be realized similarly to the receiving circuit shown in the first embodiment. When the receiving circuit of the present embodiment is used,
The number of circuit elements can be reduced.

[0098]

According to the present invention, high-speed and reliable data transmission in a bus system using a polar RTZ signal can be performed, and a high-speed and high-reliability bus system can be constructed. Become.

[Brief description of the drawings]

FIG. 1 is a configuration diagram schematically showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram schematically showing a first embodiment.

FIG. 3 is a graph showing characteristics of the voltage comparator used in the first embodiment.

FIG. 4 is a timing chart for explaining an operation in the first embodiment.

FIG. 5 is a configuration diagram of a voltage comparator used in the first embodiment.

FIG. 6 is a configuration diagram of a voltage comparator used in the first embodiment.

FIG. 7 is a configuration diagram schematically showing a third embodiment of the present invention.

FIG. 8 is a configuration diagram schematically showing a conventional technique.

FIG. 9 is a configuration diagram schematically showing a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram schematically showing a fourth embodiment.

FIG. 11 is a configuration diagram of a voltage comparator with a latch function used in a fourth embodiment.

FIG. 12 is a configuration diagram schematically showing a second embodiment of the present invention.

FIG. 13 is a timing chart for explaining the operation of the conventional technique.

[Explanation of symbols]

10 data input terminal, 11 reference voltage supply wiring, 1
2, 13 ... voltage comparator, 14, 14a ... RS flip-flop (RS-FF), 15 ... data output terminal, 20 ...
Negative logic data input terminals, 41, 42, 43, 44 ...
Pulse signal, 51, 52, 61, 62, 51a, 52
a, 61a, 62a ... P-channel MOSFET, 53,
54, 55 ... N-channel MOSFET, 70a, 70
b, 70c, 70d: bus wiring, 71: processor board, 72: central processing unit (CPU), 73: cache memory, 74, 77, 78, 79: bus bridge, 75: memory board, 76: memory module,
80a: bus wiring, 80b: stub wiring,
81a, 81b ... module, 82a, 82b ...
Integrated circuit, 83a, 83b ... transmitting circuit, 8
4a, 84b receiving circuit, 85a, 85b
... Terminating resistor, 86 ... Directional coupler, 91a ... Voltage comparator with latch function, 92 ... Offset voltage setting terminal.

Claims (5)

[Claims] 1. A data receiving circuit used for a polar RTZ signal, wherein the data receiving circuit includes two voltage comparators having an offset value of 10% or more and 50% or less of an input signal amplitude, and an RS flip-flop circuit. And output signals from the two voltage comparators are respectively represented by R
A data receiving circuit which is connected to a Set input terminal and a Reset input terminal of an S flip-flop and converts a polar RTZ signal into an NRZ signal. 2. The data receiving circuit for a polar RTZ signal according to claim 1, wherein the voltage comparator provided in the receiving circuit has an offset voltage control circuit for controlling an offset voltage. A data receiving circuit, wherein the offset voltage is variable by the offset voltage control circuit. 3. A data receiving circuit used for a polar RTZ signal, wherein the data receiving circuit has a hysteresis voltage having a hysteresis voltage of 20% or more and 100% or less of an input signal amplitude, and a hysteresis voltage for controlling the hysteresis voltage. A data receiving circuit, comprising a control circuit, wherein a hysteresis voltage is variable by the control circuit. 4. A data receiving circuit for a polar RTZ signal according to claim 1, wherein said data receiving circuit has two input terminals for inputting data. A data receiving circuit, wherein a differential signal is input to the input terminal. 5. An information processing apparatus comprising a data reception circuit in the data reception circuit for a polar RTZ signal according to claim 1, 2, 3, or 4.