JP2000324091A - Bit rate decision circuit, receiver and repeater - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit rate decision circuit that can decide a clock with a bit rate matched with a bit rate of a received signal and to provide a receiver and a repeater employing the bit rate decision circuit. SOLUTION: The bit rate decision circuit is provided with a bit rate selection circuit 6 that selects a clock signal with a required bit rate on the basis of a clock signal with a maximum bit rate extracted from an input signal and a clock signal generated from the clock signal with the maximum bit rate and with a bit rate detection circuit 7 that generates a selection signal to be fed to the bit rate selection circuit 6 depending on a level of an analog signal with a maximum bit rate extracted from the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit rate determination circuit, a receiver, and a repeater, and more particularly, to a bit rate capable of determining a clock having a bit rate matching the bit rate of received data. The present invention relates to a decision circuit and a receiver and a repeater to which the bit rate decision circuit is applied.

In digital transmission technology, digital transmission technology using electric signals has been rapidly spread because of good noise resistance, and furthermore, digital transmission technology using optical signals has shifted to digital transmission technology because of good compatibility with optical transmission. ing.

[0003] In order to transmit efficiently from a subscriber line having a relatively small line capacity to a large-capacity relay line, a multiplexing hierarchy is stipulated. The necessary bit rate is set to transmit information.

[0004] Usually, receivers and repeaters individually corresponding to necessary bit rates are developed and procured to constitute a digital transmission system.

[0005] In an era where the characteristics of the components used are limited, the most economical transmission system can be constructed by developing and procuring a receiver and a repeater which are optimal for a required bit rate. Although it was effective in the sense of this, it is not always effective nowadays when semiconductor technology for forming an electric circuit and a laser diode for performing electric-optical conversion has been greatly developed. That is, even if a semiconductor system corresponding to the highest bit rate is applied and a transmission system with a lower bit rate is configured, the economic disadvantage is reduced.

Therefore, there is a need for a receiver and a repeater that can autonomously determine a clock having a bit rate that matches the bit rate of the received data. It is necessary to realize a bit rate determination circuit that can autonomously determine a clock having a bit rate that matches the rate.

[0007]

2. Description of the Related Art FIG. 14 shows a configuration of a conventional optical receiver.

In FIG. 14, reference numeral 9 denotes an optical-to-electrical conversion circuit (indicated as an O / E conversion circuit in the figure, but is the same; hereinafter, similarly denoted), 1 is a preamplifier,
2 is a branch circuit, 3a is a clock component generation circuit (C in the figure)
Although described as an LK component generation circuit, they are the same. The same applies hereinafter. ), 4 is a band-pass filter,
Reference numeral 5 denotes a limiter amplifier (only LIM is shown in the figure, but it is the same. The same applies hereinafter), 8
Is an identification reproducing circuit.

In the configuration of FIG. 14, the optical reception signal is converted into an electric signal in the optical / electric conversion circuit 9, and the obtained electric signal is amplified to a required level by the preamplifier 1, and 2, the output of the preamplifier 1 is branched.

One of them is guided to the clock component generation circuit 3a to generate a signal including the clock component, the clock component is extracted by the band-pass filter 4, and the band-pass filter 4 is extracted by the limiter amplifier 5. Is converted to a square wave to reproduce the clock signal.

The other output of the branch circuit 2 is supplied as data to the discriminating / reproducing circuit 8, and the discriminating / reproducing of data is performed by the clock signal reproduced by the limiter amplifier 5.

Thus, the received optical signal is converted into an electric signal,
Received data is obtained by the procedure of identifying and reproducing the electric signal.

FIG. 15 shows the configuration of a conventional optical repeater.

In FIG. 15, reference numeral 9 denotes an optical / electrical conversion circuit;
1 is a preamplifier, 2 is a branch circuit, 3a is a clock component generation circuit, 4 is a band-pass filter, 5 is a limiter amplifier, 8
Denotes an identification reproduction circuit, and 10 denotes an electric / optical conversion circuit.

In the configuration shown in FIG. 14, the optical reception signal is converted into an electric signal in the optical / electrical conversion circuit 9, and the obtained electric signal is amplified to a required level by the preamplifier 1, and 2, the output of the preamplifier 1 is branched.

One of them is guided to the clock component generation circuit 3a to generate a signal including the clock component, the clock component is extracted by the band-pass filter 4, and the band-pass filter 4 is extracted by the limiter amplifier 5. Is converted to a square wave to reproduce the clock signal.

The other output of the branch circuit 2 is supplied to the discriminating / reproducing circuit 8 as data, and the data is discriminated and reproduced by the clock signal reproduced by the limiter amplifier 5.

Then, the identified and reproduced electric signal is
The optical signal is again converted into an optical signal by the optical conversion circuit 10 and output to the optical transmission line.

Thus, the received optical signal is converted into an electric signal,
An optical signal can be relayed by a procedure of identifying and reproducing an electrical signal, converting the identified and reproduced electrical signal into an optical signal again, and outputting the optical signal.

[0020]

However, since the pass band of the band-pass filter 4 in the configuration of FIGS. 14 and 15 is specific to the optical receiver and the optical repeater, the limiter amplifier 5 The bit rate of the clock signal generated by is constant.

That is, the optical receiver having the configuration shown in FIG. 14 and the optical repeater having the configuration shown in FIG. 15 can be used only at a fixed bit rate.

Further, the configuration in which the optical-to-electrical conversion circuit 9 and the electrical-to-optical conversion circuit 10 are removed from the configuration of FIG. 14 and the configuration of FIG. 15 is a configuration of an electric signal receiver and a repeater.

Accordingly, receivers and repeaters for electrical signals based on the techniques shown in FIGS. 14 and 15 can only be used at a fixed bit rate.

The present invention has been made in view of the above problems, and has as its object to provide a receiver and a repeater capable of autonomously determining a clock having a bit rate matching the bit rate of received data. Therefore, a bit rate that can autonomously determine a clock having a bit rate that matches the bit rate of the received data required for this purpose
It is an object to provide a rate determination circuit.

[0025]

FIG. 1 is a diagram showing a first means of the present invention.

In FIG. 1, 1 is a preamplifier, 2 is a branch circuit, 3 is a clock component generation circuit, 4 is a band-pass filter, 5 is a limiter amplifier, 6 is a bit rate selection circuit, and 7 is a first Is a bit rate detection circuit, and 8 is an identification reproduction circuit.

In the configuration shown in FIG. 1, the input electric signal is amplified to a required level by the preamplifier 1,
The output of the preamplifier 1 is branched by the branch circuit 2.

One of them is guided to the clock component generation circuit 3 to generate a signal including the clock component, the clock component is extracted by the band-pass filter 4, and the band-pass filter 4 is extracted by the limiter amplifier 5. Is converted to a square wave to reproduce the clock signal. In the bit rate selection circuit 6, a clock signal having a plurality of bit rates is generated from the reproduced clock signal.

The output of the band-pass filter 4 is also supplied to the first bit rate detection circuit 7, and the output of the first bit rate
The rate detection circuit 7 detects the bit rate of the input data according to the level of the output level of the band-pass filter 4, and supplies a selection signal to the bit rate selection circuit, and the bit rate selection circuit At 6, a clock signal with a bit rate matching the bit rate of the input signal is selected.

The other output of the branch circuit 2 is supplied as data to the discriminating and reproducing circuit 8, and the data is discriminated and reproduced by the clock signal reproduced by the bit rate selecting circuit 6.

Thus, according to the first means of the present invention,
Even if the bit rate of the input data is not known in advance, it is possible to reproduce a clock signal that matches the bit rate of the input data and identify and reproduce the input electric signal.

FIG. 2 is a view showing a second means of the present invention.

In FIG. 2, 1 is a preamplifier, 2 is a branch circuit, 3 is a clock component generation circuit, 4 is a band-pass filter, 5 is a limiter amplifier, 6 is a bit rate selection circuit, and 7a is a second Is a bit rate detection circuit, and 8 is an identification reproduction circuit.

In the configuration of FIG. 2, the input electric signal is amplified to a required level by the preamplifier 1,
The output of the preamplifier 1 is branched by the branch circuit 2.

One of them is guided to the clock component generation circuit 3 to generate a signal including a clock component, the clock component is extracted by the band-pass filter 4, and the band-pass filter 4 is extracted by the limiter amplifier 5. Is converted to a square wave to reproduce the clock signal. In the bit rate selection circuit 6, a clock signal having a plurality of bit rates is generated from the reproduced clock signal.

The output of the clock component generation circuit 3 is also supplied to the second bit rate detection circuit 7a, and the second bit rate detection circuit 7a calculates the average value of the output of the clock component generation circuit 3 The bit rate of the input data is detected according to the magnitude, and a selection signal is supplied to the bit rate selection circuit 6. The bit rate selection circuit 6 detects the bit rate of the input signal that matches the bit rate of the input signal. Select a clock signal.

The other output of the branch circuit 2 is supplied as data to the identification and reproduction circuit 8, and the data is identified and reproduced by the clock signal reproduced by the bit rate selection circuit 6.

Thus, according to the second means of the present invention,
Even if the bit rate of the input data is not known in advance, it is possible to reproduce a clock signal that matches the bit rate of the input data and identify and reproduce the input electric signal.

FIG. 3 is a diagram for explaining the third means of the present invention.

In FIG. 3, 1 is a preamplifier, 2 is a branch circuit, 3 is a clock component generation circuit, 4 is a band-pass filter, 5 is a limiter amplifier, 6 is a bit rate selection circuit, and 7b is a third Is a bit rate detection circuit, and 8 is an identification reproduction circuit.

In the configuration shown in FIG. 3, the input electric signal is amplified to a required level by the preamplifier 1,
The output of the preamplifier 1 is branched by the branch circuit 2.

One of them is guided to the clock component generation circuit 3 to generate a signal including a clock component, the clock component is extracted by the band-pass filter 4, and the band-pass filter 4 is extracted by the limiter amplifier 5. Is converted to a square wave to reproduce the clock signal. In the bit rate selection circuit 6, a clock signal having a plurality of bit rates is generated from the reproduced clock signal.

The other output of the branch circuit 2 is supplied as data to the identification reproducing circuit 8, and the data is identified and reproduced by the clock signal reproduced by the limiter amplifier 5.

Then, in the third bit rate detection circuit 7b, the waveform of the data that has been identified and reproduced by the identification and reproduction circuit 8 is converted by the clock signal output from the limiter amplifier 5, and the converted signal is output. The bit rate of the input data is detected based on the average value, and a selection signal is supplied to the bit rate selection circuit 6.

Thus, according to the third means of the present invention,
Even if the bit rate of the input data is unknown in advance, the input electric signal is discriminated and reproduced, and a clock signal matching the bit rate of the input data is reproduced and supplied to a subsequent circuit. be able to.

FIG. 4 is a view for explaining the fourth means of the present invention.

In FIG. 4, 1 is a preamplifier, 2 is a branch circuit, 3 is a clock component generation circuit, 4 is a band-pass filter, 5 is a limiter amplifier, 6 is a bit rate selection circuit, and 7c is a fourth Is a bit rate detection circuit, and 8 is an identification reproduction circuit.

In the configuration of FIG. 4, the input electric signal is amplified to a required level by the preamplifier 1,
The output of the preamplifier 1 is branched by the branch circuit 2.

One of them is guided to the clock component generation circuit 3 to generate a signal including a clock component, the clock component is extracted by the band-pass filter 4, and the band-pass filter 4 is extracted by the limiter amplifier 5. Is converted to a square wave to reproduce the clock signal. In the bit rate selection circuit 6, a clock signal having a plurality of bit rates is generated from the reproduced clock signal.

Both outputs of the branch circuit 2 are supplied to the fourth bit rate detection circuit 7c. The fourth bit rate detection circuit 7c detects a change point of the data input from both outputs of the branch circuit 2, and detects the bit of the input data based on the average value of the signal at which the change point is detected. Detect the rate and supply a select signal to the bit rate select circuit.

The clock signal selected by the bit rate selection circuit 6 is supplied to the identification and reproduction circuit 8, and the output of the branch circuit 2 supplied to the identification and reproduction circuit 8 is identified and reproduced.

Thus, according to the fourth means of the present invention,
Even if the bit rate of the input data is unknown in advance, the input electric signal is discriminated and reproduced, and a clock signal matching the bit rate of the input data is reproduced and supplied to a subsequent circuit. be able to.

[0053]

FIG. 5 shows a basic configuration for clock component generation and bit rate detection.

In FIG. 5, 31 is a delay circuit, and 32 is an exclusive OR circuit. When the frequency of the assumed highest bit rate clock signal is f ₀ , the delay time of the delay circuit 31 is の of the clock cycle, ie,
Set to 1 / (2f ₀ ).

FIG. 6 is a diagram showing the relationship between the speed of the input signal and FIG.
3 is a diagram showing a difference in output of the configuration of FIG.

Generally, in a digital transmission system,
The transmitted signal is scrambled into a pseudo-random signal. Here, in order to clearly show the difference in the output of the configuration of FIG. 5 due to the difference in the speed of the input signal, the logic level is assumed at the assumed bit rate. Will be described with an alternating signal that repeats "0" and "1".

FIG. 6A shows the case where the bit rate is f ₀ , so that “0” and “1” of the input signal have the frequency f _0.
Is repeated. This is reduced by the delay circuit 31 to 1 /
(2f ₀ ).

Since the exclusive OR of the input signal and the signal delayed by the delay circuit 31 is calculated, the output of the exclusive OR circuit 32 is the "EXOR output" of FIG. Thus, the signal has a pulse width of 1 / (2f ₀ ) and a repetition frequency of f ₀ .

[0059] Similarly, when the bit rate shown in FIG. 6 (b) is f _0/2, the output of the exhaust other logical sum circuit 32 as the "output of the EXOR" in FIG. 6 (b) , pulse width repetition frequency 1 / (2f ₀₎ becomes f _0/2 of the signal, if the bit rate shown in FIG. 6 (c) of f _0/3 is the exhaust other logical sum circuit 32 The output is shown in Fig. 6 (c)
The pulse width is 1 / (2
frequency repeatedly with f ₀₎ is the signal of the f _0/3, FIG. 6
If the bit rate shown in (d) of the f _0/4, the output of the exhaust other logical sum circuit 32, FIG. 6 (d) "EXO
As R output of "pulse width repetition frequency 1 / (2f ₀₎ becomes a signal of f _0/4.

That is, an exclusive signal of an alternating signal whose logic level repeats "0" and "1" at an assumed bit rate and the alternating signal shifted by 1/2 of the cycle of the assumed highest bit rate. By taking the sum, a clock component corresponding to the assumed bit rate can be generated.

First, the exclusive OR circuit 3
Output f of 2₀Bit of input signal depending on component level
-The rate can be detected. Because the bit
Rate is f₀The output of the exclusive OR circuit 32
F₀The amplitude of the component is 2 / π and the bit rate is f
₀/ 2, f of the output of the exclusive OR circuit 32 ₀
The amplitude of the component is 1 / π and the bit rate is f₀/ 3
In the case of f, the output f of the exclusive OR circuit 32₀Ingredient
The amplitude is 2 / (3π) and the bit rate is f₀/ 4
In the case of f, the output f of the exclusive OR circuit 32₀Ingredient
The amplitude is 1 / (2π) and the bit rate is f₀/ N
(N is a positive integer), the exclusive-OR circuit 32
Output f₀The amplitude of the component is 2 / (nπ),
About f₀This is because the amplitudes of the components are different.

Second, the output of the exclusive OR circuit 32
The bit rate of the input signal by the average of
be able to. Because the bit rate of the input signal is
f₀, The average of the outputs of the exclusive OR circuit 32
And the bit rate of the input signal is f₀/
In the case of 2, the average value of the output of the exclusive OR circuit 32
Is １ ／, and the bit rate of the input signal is f₀/ 3
In the case of, the average value of the output of the exclusive OR circuit 32 is
And the bit rate of the input signal is f ₀/ 4
In this case, the average value of the output of the exclusive OR circuit 32 is 1
/ 8 and the bit rate is f₀/ N,
The average value of the output of the exclusive OR circuit 32 is 1 / (2n)
And the exclusive logic corresponding to the bit rate of the input signal.
This is because the average value of the output of the OR circuit 32 is different.

However, in a normal digital transmission system, a signal is scrambled at the time of transmission to form a pseudo-random signal. Therefore, when supplying the input signal in the actual digital transmission system to the configuration of FIG. 5, f ₀ component and the average value of the output of the exhaust other OR circuit 32 becomes a value different from the above.

[0064] However, also be pseudo-random signaling, since the input signal is taken over without fail the nature of the signal before being pseudo-randomized, always a difference in the f ₀ component and the average value Different bit rates Occurs. Thus, by measuring the f ₀ component and the average value for the pseudo random signal, it is possible to detect the bit rate of the input signal if the basis of their value.

FIG. 7 shows a basic configuration for bit rate detection.

In FIG. 7, 74-1 and 74-2 are AND circuits, and 75 is a delay circuit. Then, it supplies a clock signal of a highest bit rate f _0, which is extracted and the input signal to the logical product circuit 74-1.

The extracted clock signal having the highest bit rate can be generated based on the configuration shown in FIG.
The delay time of the delay circuit 75 is set to one cycle of the extracted clock signal having the highest bit rate, that is, 1 / f ₀ .

FIG. 8 is a circuit diagram of FIG.
3 is a diagram showing a difference in output of the configuration of FIG.

Generally, in a digital transmission system,
The transmitted signal is scrambled into a pseudo-random signal. Here, in order to clearly show the difference in the output of the configuration of FIG. 5 due to the difference in the speed of the input signal, the logic level is assumed at the assumed bit rate. Will be described with an alternating signal that repeats "0" and "1".

FIG. 8A shows the case where the bit rate of the input signal is f ₀ , so that “0” and “1” of the input signal are repeated at the frequency f ₀ . This is connected to the AND circuit 74.
Is supplied to -1, the bit rate is a logical AND operation between the clock signal of f _0. Therefore, the AND circuit 74-1
Output as shown in "AND 74-1 outputs of" in FIG. 8 (b), the signal bit rate is every other pulse of the clock signal f ₀ of.

Since the output of the AND circuit 74-1 is passed through the delay circuit 75 having a delay time of 1 / f ₀ , the output of the delay circuit 75 is a pulse in the middle of the pulse of "output of AND74-1". Is obtained.

Therefore, the output of the AND circuit 74-2 becomes a signal of the logic level "0".

[0073] By performing the bit rate of the input signal similar investigated for the case of _{f 0/2, f 0/} 3 and f _0/4, if the bit rate of the input signal is f _0/2, the
Pulse duration 1 / f ₀ within the duration of the input signal pulse becomes the signal present one, when the bit rate of the input signal is f _0/3 is the duration of the input signal pulse pulse duration 1 / f ₀ becomes two signal present, if the bit rate of the input signal is f _0/4, the duration 1 / f ₀ within the duration of the pulses of the input signal
And the bit rate of the input signal is f ₀ / n, the pulse of the duration 1 / f ₀ is (n−1) within the duration of the pulse of the input signal. Signals.

As a result, if the average value of the output of the AND circuit 74-2 is obtained, the bit rate of the input signal can be detected.

However, in a normal digital transmission system, a signal is scrambled at the time of transmission to form a pseudo-random signal. Therefore, when an input signal in an actual digital transmission system is supplied to the configuration of FIG.
The average value of the outputs of 2 is different from the above.

However, even if a pseudo-random signal is formed, the input signal always inherits the properties of the signal before being pseudo-randomized, so that if the bit rate is different, a difference always occurs in the average value. Therefore, it is possible to detect the bit rate of the input signal by measuring the average value for the pseudo-random signal and using those values as a reference.

In the present invention, a clock signal having a bit rate f ₀ is extracted from an input signal or the bit rate of the input signal is detected based on the above knowledge.

FIG. 9 shows a first embodiment of the present invention.

In FIG. 9, reference numeral 11 denotes a current switch circuit, which plays a role of the preamplifier 1 and the branch circuit 2 of FIG.

Reference numeral 31 denotes a delay circuit, and 32 denotes an exclusive OR circuit. The delay circuit 31 and the exclusive OR circuit 32 constitute the clock component generation circuit 3 in FIG. The delay time of the delay circuit 31 is set to の of the cycle of the clock having the highest assumed bit rate f ₀ .

[0081] 4 in the band-pass device, it extracts the f ₀ component of the signal output from the exhaust other OR circuit 32.

A limiter amplifier 5 generates a clock signal having a bit rate f ₀ from the output of the band-pass filter 4.

Reference numeral 61 designates the output of the limiter amplifier 5 as １ ／.
A 1/2 frequency dividing circuit for dividing the frequency, 62 is a 1/3 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/3, and 63 is a 1/4 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/4. Divider circuit, 6
4 is the output of the limiter amplifier 5, the 1/2 frequency dividing circuit 61
A selector for selecting one of the output of the 1/3 frequency dividing circuit 62 and the output of the 1/4 frequency dividing circuit 63.
The ２ frequency dividing circuit 61, the １ ／ frequency dividing circuit 62, the ４ frequency dividing circuit 63 and the selector 64
The rate selection circuit 6 is configured.

Reference numeral 71 denotes a peak detection circuit for detecting the output amplitude of the band-pass filter 4, and reference numeral 72 denotes an analog / digital conversion circuit (an A / D conversion circuit in the figure) for converting the output of the peak detection circuit 71 into a digital value. The peak detection circuit 71 and the analog-to-digital conversion circuit 72 constitute the bit rate detection circuit 7 in FIG.

The peak detection circuit 71 can be constituted by an L-shaped circuit having a diode in a series branch and a capacitor in a parallel branch.

Reference numeral 81 denotes a delay circuit whose delay time can be adjusted.
Reference numeral 2 denotes a flip-flop, which is constituted by a delay circuit 81 capable of adjusting the delay time and a flip-flop 82 shown in FIG.
Of the identification reproducing circuit 8 of FIG.

An input signal is supplied to one input terminal of the current switch circuit 11, and a threshold voltage for identifying a logic level of the input signal is supplied to the other input terminal of the current switch circuit 11. .

One output of the current switch circuit 11 is supplied to one input terminal of the delay circuit 31 and one input terminal of the exclusive OR circuit 32, and the output of the delay circuit 31 is supplied to the other end of the exclusive OR circuit 32. It is supplied to one input terminal.

Therefore, the output of the exclusive OR circuit 32 becomes a signal having a different bit rate depending on the bit rate of the input signal as shown in "EXOR output" in FIG.

The frequency f of the output of the exclusive OR circuit 32
_{The zero} component is extracted by the band-pass filter 4.

Since the output of the band-pass filter 4 is made into a rectangular wave by the limiter amplifier 5, the output of the limiter amplifier 5
Is a clock signal having a bit rate f ₀ . The output of the limiter amplifier 5 is divided by the 1/2 frequency divider 6
1. Since the frequency is divided by the 1/3 frequency dividing circuit 62 and the 1/4 frequency dividing circuit 63, the 1/2 frequency dividing circuit 61 and the 1/3 frequency dividing circuit
Frequency dividing circuit 62 and the bit rate output is compared to the bit rate f ₀ of the 1/4 frequency divider 63 is 1 / 2,1 /
3 and 1/4 clock signals.

On the other hand, the output of the band-pass filter 4 is supplied to the peak detection circuit 71, and the output amplitude of the band-pass filter 4 is obtained. As described above, the peak detection circuit 7
One output will be at a different level depending on the bit rate of the input signal.

The output of the peak detection circuit 71 at a different level corresponding to the bit rate of the input signal is digitally converted by the analog / digital conversion circuit 72, and the digitally converted data is sent to the selector 64 as a selection signal. Supply.

Accordingly, the selector 64 selects and outputs a clock signal corresponding to the bit rate of the input signal.

A finite delay time is required from the generation of the clock component to the selection of the clock signal corresponding to the bit rate of the input signal.

The delay circuit 81 capable of adjusting the delay time is provided for canceling the delay time. The input signal provided with a required delay by the delay circuit 81 capable of adjusting the delay time is supplied to the flip-flop. -Discriminated and reproduced by the clock signal supplied to the flop 82 and supplied by the selector 64.

At the same time, the output of the selector 64 is supplied as a clock signal to a subsequent circuit.

As described above, according to the configuration of FIG. 9, the clock signal corresponding to the bit rate of the input signal is reproduced without knowing the bit rate of the input signal in advance, and the input signal is discriminated and reproduced. Can be.

In practice, the number of clock signals to be selected is not so large, and may be 3 to 4 at most. Accordingly, since the number of bits of the analog-to-digital conversion circuit may be small, it is sufficient to configure the analog-to-digital conversion circuit with a so-called window comparator. This can be said for all the embodiments of the invention described below.

FIG. 10 shows a second embodiment of the present invention.

In FIG. 10, reference numeral 11 denotes a current switch circuit, which plays a role of the preamplifier 1 and the branch circuit 2 of FIG.

Reference numeral 31 denotes a delay circuit, and 32 denotes an exclusive OR circuit. The delay circuit 31 and the exclusive OR circuit 32 constitute the clock component generation circuit 3 shown in FIG. Note that the delay time of the delay circuit 31 is set to の of the cycle of the clock having the highest assumed bit rate.

[0103] 4 in the band-pass device, it extracts the f ₀ component of the signal output from the exhaust other OR circuit 32.

A limiter amplifier 5 generates a clock signal having a bit rate f ₀ from the output of the band-pass filter 4.

Reference numeral 61 designates the output of the limiter amplifier 5 as １ ／.
A 1/2 frequency dividing circuit for dividing the frequency, 62 is a 1/3 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/3, and 63 is a 1/4 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/4. Divider circuit, 6
4 is the output of the limiter amplifier 5, the 1/2 frequency dividing circuit 61
A selector for selecting one of the output of the 1/3 frequency dividing circuit 62 and the output of the 1/4 frequency dividing circuit 63.
The 分 divider circuit 61, the ３ divider circuit 62, the 分 divider circuit 63, and the selector 64
The rate selection circuit 6 is configured.

Reference numeral 73 denotes an average value detection circuit for detecting the average value of the output of the exclusive OR circuit 32, and reference numeral 72 denotes an analog / digital conversion circuit for converting the output of the average value detection circuit 73 into a digital value. Value detection circuit 73 and the analog
The digital conversion circuit 72 constitutes the bit rate detection circuit 7a of FIG. Note that the average value detection circuit 73
An L-shaped circuit having a resistor in the series branch and a capacitor in the parallel branch can be configured.

Reference numeral 81 denotes a delay circuit whose delay time can be adjusted.
Reference numeral 2 denotes a flip-flop, which comprises a delay circuit 81 capable of adjusting the delay time and a flip-flop 82 shown in FIG.
Of the identification reproduction circuit.

An input signal is supplied to one input terminal of the current switch circuit 11, and a threshold voltage for identifying a logic level of the input signal is supplied to the other input terminal of the current switch circuit 11. .

One output of the current switch circuit 11 is supplied to one input terminal of the delay circuit 31 and one input terminal of the exclusive OR circuit 32, and the output of the delay circuit 31 is supplied to the other end of the exclusive OR circuit 32. It is supplied to one input terminal.

Therefore, the output of the exclusive OR circuit 32 becomes a signal having a different bit rate depending on the bit rate of the input signal as shown in "EXOR output" in FIG.

The frequency f of the output of the exclusive OR circuit 32
_{The zero} component is extracted by the band-pass filter 4.

Since the output of the band-pass filter 4 is made into a rectangular wave by the limiter amplifier 5, the output of the limiter amplifier 5
Is a clock signal having a bit rate f ₀ . The output of the limiter amplifier 5 is divided by the 1/2 frequency divider 6
1. Since the frequency is divided by the 1/3 frequency dividing circuit 62 and the 1/4 frequency dividing circuit 63, the 1/2 frequency dividing circuit 61 and the 1/3 frequency dividing circuit
Frequency dividing circuit 62 and the bit rate output is compared to the bit rate f ₀ of the 1/4 frequency divider 63 is 1 / 2,1 /
3 and 1/4 clock signals.

On the other hand, the output of the exclusive OR circuit 32 is supplied to the average value detecting circuit 73, and the exclusive OR circuit 3
The average value of the outputs of 2 is obtained. As described above, the output of the average value detection circuit 73 is at a different level corresponding to the bit rate of the input signal.

The output of the average value detection circuit 73 having a different level corresponding to the bit rate of the input signal is digitally converted by the analog / digital conversion circuit 72 and supplied to the selector 64 as a selection signal.

Therefore, the selector 64 selects and outputs a clock signal corresponding to the bit rate of the input signal.

A finite delay time is required from the generation of the clock component to the selection of the clock signal corresponding to the bit rate of the input signal.

The delay circuit 81 capable of adjusting the delay time is provided for canceling the delay time. The input signal provided with the required delay by the delay circuit 81 capable of adjusting the delay time is supplied to the flip-flop. -Discriminated and reproduced by the clock signal supplied to the flop 82 and supplied by the selector 64.

At the same time, the output of the selector 64 is supplied as a clock signal to a subsequent circuit.

As described above, the configuration shown in FIG.
Regenerate a clock signal corresponding to the bit rate of the input signal without knowing the bit rate of the input signal in advance,
The input signal can be identified and reproduced.

FIG. 11 shows a third embodiment of the present invention.

In FIG. 11, reference numeral 11 denotes a current switch circuit, which functions as the preamplifier 1 and the branch circuit 2 in FIG.

Reference numeral 31 denotes a delay circuit, and 32 denotes an exclusive OR circuit. The delay circuit 31 and the exclusive OR circuit 32 constitute the clock component generation circuit 3 shown in FIG. Note that the delay time of the delay circuit 31 is set to の of the cycle of the clock having the highest assumed bit rate.

[0123] 4 in the band-pass device, it extracts the f ₀ component of the signal output from the exhaust other OR circuit 32.

A limiter amplifier 5 generates a clock signal having a bit rate f ₀ from the output of the band-pass filter 4.

Numeral 61 designates the output of the limiter amplifier 5 as １ ／.
A 1/2 frequency dividing circuit for dividing the frequency, 62 is a 1/3 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/3, and 63 is a 1/4 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/4. Divider circuit, 6
4 is the output of the limiter amplifier 5, the 1/2 frequency dividing circuit 61
A selector for selecting one of the output of the 1/3 frequency dividing circuit 62 and the output of the 1/4 frequency dividing circuit 63.
The 分 divider circuit 61, the １ ／ divider circuit 62, the ４ divider circuit 63, and the selector 64
The rate selection circuit 6 is configured.

74-1 and 74-2 are AND circuits;
Is a delay circuit, 73 is an average value detection circuit, 72 is an analog
In a digital conversion circuit, these components constitute the bit rate detection circuit 7b of FIG. The delay time of the delay circuit 75 is set equal to one cycle of the clock signal having the highest assumed bit rate.

Reference numeral 81 denotes a delay circuit whose delay time can be adjusted.
Numeral 2 denotes a flip-flop, which comprises a delay circuit 81 capable of adjusting the delay time and a flip-flop 82 shown in FIG.
Of the identification reproduction circuit.

An input signal is supplied to one input terminal of the current switch circuit 11, and a threshold voltage for identifying a logic level of the input signal is supplied to the other input terminal of the current switch circuit 11. .

One output of the current switch circuit 11 is supplied to one input terminal of the delay circuit 31 and one input terminal of the exclusive OR circuit 32, and the output of the delay circuit 31 is supplied to the other end of the exclusive OR circuit 32. It is supplied to one input terminal.

Therefore, the output of the exclusive OR circuit 32 is a signal having a different bit rate depending on the bit rate of the input signal, as shown in "EXOR output" in FIG.

The frequency f of the output of the exclusive OR circuit 32
_{The zero} component is extracted by the band-pass filter 4.

Since the output of the band-pass filter 4 is converted into a rectangular wave by the limiter amplifier 5, the output of the limiter amplifier 5
Is a clock signal having a bit rate f ₀ . The output of the limiter amplifier 5 is divided by the 1/2 frequency divider 6
1. Since the frequency is divided by the 1/3 frequency dividing circuit 62 and the 1/4 frequency dividing circuit 63, the 1/2 frequency dividing circuit 61 and the 1/3 frequency dividing circuit
Frequency dividing circuit 62 and the bit rate output is compared to the bit rate f ₀ of the 1/4 frequency divider 63 is 1 / 2,1 /
3 and 1/4 clock signals.

A finite delay time is required from the generation of the clock component to the generation of the clock signal having the bit rate f ₀ corresponding to the bit rate of the input signal.

The delay circuit 81 capable of adjusting the delay time is provided for canceling the delay time. The input signal provided with the required delay by the delay circuit 81 capable of adjusting the delay time is supplied to the flip-flop. The signal is supplied to the flop 82 and is discriminated and reproduced by the clock signal of the bit rate f ₀ output from the limiter amplifier 5.

The flip-flop 82 is identified and reproduced.
And the clock signal of the bit rate f ₀ output by the limiter amplifier 5 are
-1.

As described with reference to FIGS. 7 and 8, the output of the AND circuit 74-2 has a different waveform corresponding to the bit rate of the input signal.

The average value of the output of the AND circuit 74-2 is obtained by the average value detection circuit 73. AND circuit 74
Since the output of -2 has a different waveform according to the bit rate of the input signal, the output level of the average value detection circuit 73 differs according to the bit rate of the input signal. Therefore, if the output of the average value detection circuit 73 is converted into a digital signal by the analog / digital conversion circuit 72, the output signal becomes a selection signal for selecting a clock signal corresponding to the input signal in the selector 64.

Accordingly, a clock signal corresponding to the bit rate of the input signal is selected and output from the selector 64, and supplied to a subsequent circuit.

As described above, the configuration shown in FIG.
Regenerate a clock signal corresponding to the bit rate of the input signal without knowing the bit rate of the input signal in advance,
The input signal can be identified and reproduced.

FIG. 12 shows a fourth embodiment of the present invention.

In FIG. 12, reference numeral 11 denotes a current switch circuit, which plays the role of the preamplifier 1 and the branch circuit 2 in FIG.

Reference numeral 31 denotes a delay circuit, and reference numeral 32 denotes an exclusive OR circuit. The delay circuit 31 and the exclusive OR circuit 32 constitute the clock component generation circuit 3 shown in FIG. Note that the delay time of the delay circuit 31 is set to の of the cycle of the clock having the highest assumed bit rate.

[0143] 4 in the band-pass device, it extracts the f ₀ component of the signal output from the exhaust other OR circuit 32.

A limiter amplifier 5 generates a clock signal having a bit rate f ₀ from the output of the band-pass filter 4.

Reference numeral 61 designates the output of the limiter amplifier 5 as １ ／.
A 1/2 frequency dividing circuit for dividing the frequency, 62 is a 1/3 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/3, and 63 is a 1/4 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/4. Divider circuit, 6
4 is the output of the limiter amplifier 5, the 1/2 frequency dividing circuit 61
A selector for selecting one of the output of the 1/3 frequency dividing circuit 62 and the output of the 1/4 frequency dividing circuit 63.
The 1/2 frequency dividing circuit 61, the 1/3 frequency dividing circuit 62, the 1/4 frequency dividing circuit 63 and the selector 64 generate the bit
The rate selection circuit 6 is configured.

Reference numeral 76 denotes a logical sum circuit for calculating the logical sum of the two outputs of the current switch circuit 11 to detect a switching point of the input signal, and reference numeral 73 denotes an average value detection for detecting the average value of the output of the logical sum circuit 76. Circuit 72 is an average value detection circuit 73
4 is converted into a digital value. These components constitute the bit rate detection circuit 7c in FIG.

Reference numeral 81 denotes a delay circuit whose delay time can be adjusted.
Reference numeral 2 denotes a flip-flop, which is constituted by a delay circuit 81 capable of adjusting the delay time and a flip-flop 82 shown in FIG.
Of the identification reproducing circuit 8 of FIG.

An input signal is supplied to one input terminal of the current switch circuit 11, and a threshold voltage for identifying a logic level of the input signal is supplied to the other input terminal of the current switch circuit 11. .

One output of the current switch circuit 11 is supplied to one input terminal of the delay circuit 31 and one input terminal of the exclusive OR circuit 32, and the output of the delay circuit 31 is supplied to the other end of the exclusive OR circuit 32. It is supplied to one input terminal.

Therefore, the output of the exclusive OR circuit 32 is a signal having a different bit rate depending on the bit rate of the input signal as shown in "EXOR output" in FIG.

The frequency f of the output of the exclusive OR circuit 32
_{The zero} component is extracted by the band-pass filter 4.

Since the output of the band-pass filter 4 is converted into a rectangular wave by the limiter amplifier 5, the output of the limiter amplifier 5
Is a clock signal having a bit rate f ₀ . The output of the limiter amplifier 5 is divided by the 1/2 frequency divider 6
1. Since the frequency is divided by the 1/3 frequency dividing circuit 62 and the 1/4 frequency dividing circuit 63, the 1/2 frequency dividing circuit 61 and the 1/3 frequency dividing circuit
Frequency dividing circuit 62 and the bit rate output is compared to the bit rate f ₀ of the 1/4 frequency divider 63 is 1 / 2,1 /
3 and 1/4 clock signals.

The two outputs of the current switch circuit 11 are supplied to the OR circuit 76. If the threshold value of the OR circuit 76 is set to a higher level than usual, the switching point of the input signal can be detected by the OR circuit 76.

If the output of the OR circuit 76 is supplied to the average value detection circuit 73 to calculate the average value, the average value becomes different depending on the bit rate of the input signal.

The output of the average value detection circuit 73 having a different level corresponding to the bit rate of the input signal is digitally converted by the analog / digital conversion circuit 72 and supplied to the selector 64 as a selection signal.

Therefore, the selector 64 selects and outputs a clock signal corresponding to the bit rate of the input signal.

A finite delay time is required from the generation of the clock component to the selection of the clock signal corresponding to the bit rate of the input signal.

The delay circuit 81 capable of adjusting the delay time is provided for canceling the delay time. The input signal provided with the required delay by the delay circuit 81 capable of adjusting the delay time is supplied to the flip-flop. -Discriminated and reproduced by the clock signal supplied to the flop 82 and supplied by the selector 64.

At the same time, the output of the selector 64 is supplied as a clock signal to a subsequent circuit.

As described above, the configuration shown in FIG.
Regenerate a clock signal corresponding to the bit rate of the input signal without knowing the bit rate of the input signal in advance,
The input signal can be identified and reproduced.

FIG. 13 shows a modification of the first embodiment of the present invention.

In FIG. 13, reference numeral 11 denotes a current switch circuit, which plays the role of the preamplifier 1 and the branch circuit 2 of FIG.

Reference numeral 31 denotes a delay circuit, and reference numeral 32 denotes an exclusive OR circuit. The delay circuit 31 and the exclusive OR circuit 32 constitute the clock component generation circuit 3 in FIG. Note that the delay time of the delay circuit 31 is set to の of the cycle of the clock having the highest assumed bit rate.

[0164] 4 in the band-pass device, it extracts the f ₀ component of the signal output from the exhaust other OR circuit 32.

A limiter amplifier 5 generates a clock signal having a bit rate f ₀ from the output of the band-pass filter 4.

Numeral 61 designates the output of the limiter amplifier 5 as １ ／.
A 1/2 frequency dividing circuit for dividing the frequency, 62 is a 1/3 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/3, and 63 is a 1/4 frequency dividing circuit for dividing the output of the limiter amplifier 5 to 1/4. Divider circuit, 6
4 is the output of the limiter amplifier 5, the 1/2 frequency dividing circuit 61
A selector for selecting one of the output of the 1/3 frequency dividing circuit 62 and the output of the 1/4 frequency dividing circuit 63.
The ２ frequency dividing circuit 61, the １ ／ frequency dividing circuit 62, the ４ frequency dividing circuit 63 and the selector 64
The rate selection circuit 6 is configured.

Reference numeral 71 denotes a peak detection circuit for detecting the output amplitude of the band-pass filter 4, reference numeral 72 denotes an analog / digital conversion circuit for converting the output of the peak detection circuit 71 to a digital value, and reference numeral 78 denotes the analog / digital conversion. An AND circuit 77 performs an AND operation on the output of the circuit 72 and the training period signal supplied from the outside. A register 77 stores the output of the AND circuit 78. The bit rate detecting circuit shown in FIG. 7 is configured.

Reference numeral 81 denotes a delay circuit whose delay time can be adjusted.
Reference numeral 2 denotes a flip-flop, which is constituted by a delay circuit 81 capable of adjusting the delay time and a flip-flop 82 shown in FIG.
Of the identification reproducing circuit 8 of FIG.

In the configuration shown in FIG. 13, the current switch circuit 1
1, an alternating signal of "0" and "1" corresponding to an assumed bit rate is supplied as an input signal, and the other input terminal of the current switch circuit 11 is supplied with an input signal of the input signal. A threshold voltage is provided to identify the logic level.

One output of the current switch circuit 11 is supplied to one input terminal of the delay circuit 31 and one input terminal of the exclusive OR circuit 32, and the output of the delay circuit 31 is supplied to the other end of the exclusive OR circuit 32. It is supplied to one input terminal.

Accordingly, the output of the exclusive OR circuit 32 is a signal having a different bit rate depending on the bit rate of the input signal, as shown in "EXOR output" in FIG.

The frequency f of the output of the exclusive OR circuit 32
_{The zero} component is extracted by the band-pass filter 4.

Since the output of the band-pass filter 4 is converted into a rectangular wave by the limiter amplifier 5, the output of the limiter amplifier 5
Is a clock signal having a bit rate f ₀ . The output of the limiter amplifier 5 is divided by the 1/2 frequency divider 6
1. Since the frequency is divided by the 1/3 frequency dividing circuit 62 and the 1/4 frequency dividing circuit 63, the 1/2 frequency dividing circuit 61 and the 1/3 frequency dividing circuit
Frequency dividing circuit 62 and the bit rate output is compared to the bit rate f ₀ of the 1/4 frequency divider 63 is 1 / 2,1 /
3 and 1/4 clock signals.

On the other hand, the output of the band-pass filter 4 is supplied to the peak detection circuit 71, and the output amplitude of the band-pass filter 4 is obtained. As described above, the peak detection circuit 7
One output will be at a different level depending on the bit rate of the input signal.

The output of the peak detection circuit 71 at a different level corresponding to the bit rate of the input signal is digitally converted by the analog / digital conversion circuit 72.

The output of the analog-to-digital conversion circuit 72 is applied to the register 7 by the traffic period signal that maintains the logical level “1” only during the training period.
7 is supplied to the selector 64 as a selection signal.

Therefore, the selector 64 selects and outputs a clock signal having a bit rate corresponding to the bit rate of the input signal.

A finite delay time is required from the generation of the clock component to the selection of the clock signal corresponding to the bit rate of the input signal.

The delay circuit 81 capable of adjusting the delay time is provided for canceling the delay time. The input signal provided with the required delay by the delay circuit 81 capable of adjusting the delay time is supplied to the flip-flop. -Discriminated and reproduced by the clock signal supplied to the flop 82 and supplied by the selector 64.

At the same time, the output of the selector 64 is supplied as a clock signal to a subsequent circuit.

As described above, the configuration shown in FIG.
Regenerate a clock signal corresponding to the bit rate of the input signal without knowing the bit rate of the input signal in advance,
The input signal can be identified and reproduced.

When the training period ends, the logic level of the training period signal drops to "0".
The AND circuit 78 is connected to the analog / digital conversion circuit 72.
From being stored in the register 77. At this time, the signal actually transmitted is the current switch circuit 1
1 and from its input signal f
₀ clock signal is generated while the selector 64
Is stored in the register 77, so that a required clock signal can be selected and the input signal can be identified and reproduced even during operation.

In other words, the feature of the configuration of FIG. 13 is that, during a training period before the operation of the configuration of FIG. The bit rate selection signal detected and digitally converted from the input signal is stored in the register 77 within the training period, and the output of the analog / digital conversion circuit 72 is stored in the register 77 after the training period. In this case, the clock signal of the required bit rate is selected by the selection signal stored during the training period.

In general, once a transmission system is laid, the transmission bit rate is constant, but the nature of the transmitted signal is not always constant, and the ratio of voice, image, and data changes. If the characteristics of the transmitted signal change in this way, it is expected that the amplitude and average value for detecting the bit rate will change.

However, according to the configuration of FIG.
Since the rate detection is performed during the training period and the bit rate can be selected independently of the nature of the transmitted signal, the amplitude at which the nature of the transmitted signal changes and the bit rate is detected The clock signal of the required bit rate can be selected without being affected even if the average value changes.

FIG. 13 shows a case where the above technique is applied to the configuration of FIG. 9, but the same technique is applied to FIGS.
It can also be applied to the configuration of

The configurations shown in FIGS. 9 to 13 are general digital receivers or digital repeaters. And FIG.
If an optical-to-electrical conversion circuit is added to the input side of the configuration of FIG. 13 to FIG. 13, an optical receiver can be obtained, and an optical-to-electrical conversion circuit is added to the input side of the configuration of FIG. If a circuit is added, it becomes an optical repeater.

That is, according to the present invention, the bit
It will be understood that a bit rate determining circuit capable of determining a clock having a bit rate matching the rate, and a receiver and a repeater to which the bit rate determining circuit is applied are realized.

[0189]

As described in detail above, according to the present invention, a bit rate determining circuit capable of determining a clock having a bit rate matching the bit rate of a received signal, and the bit rate determining circuit are applied. A receiver and a repeater can be realized.

Further, it is possible to realize a bit rate determining circuit which is not affected by the properties of a transmission signal, and a receiver and a repeater to which the bit rate determining circuit is applied.

[Brief description of the drawings]

FIG. 1 shows a first means of the present invention.

FIG. 2 shows a second means of the present invention.

FIG. 3 shows a third means of the present invention.

FIG. 4 shows a fourth means of the present invention.

FIG. 5 is a basic configuration for clock component generation and bit rate detection.

FIG. 6 shows a difference in output of the configuration of FIG. 5 due to a difference in speed of an input signal.

FIG. 7 shows a basic configuration for bit rate detection.

FIG. 8 shows a difference in output of the configuration of FIG. 7 due to a difference in speed of an input signal.

FIG. 9 shows a first embodiment of the present invention.

FIG. 10 shows a second embodiment of the present invention.

FIG. 11 shows a third embodiment of the present invention.

FIG. 12 shows a fourth embodiment of the present invention.

FIG. 13 is a modification of the first embodiment of the present invention.

FIG. 14 is a configuration of a conventional optical receiver.

FIG. 15 shows a configuration of a conventional optical repeater.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Preamplifier 2 Branch circuit 3 Clock component generation circuit 3a Clock component generation circuit 4 Band-pass filter 5 Limiter amplifier 6 Bit rate selection circuit 7 Bit rate detection circuit 7a Bit rate detection circuit 7b Bit rate detection circuit 7c Bit rate detection circuit 8 Discrimination reproduction circuit 9 Optical-electrical conversion circuit 10 Electric-optical conversion circuit 11 Current switch circuit 31 Delay circuit 32 Exclusive OR circuit 61 1/2 frequency dividing circuit 62 1/3 frequency dividing circuit 63 1/4 frequency dividing circuit 64 selector 71 peak detecting circuit 72 analog / digital converting circuit 73 average value detecting circuit 74-1 logical product circuit 74-2 logical product circuit 75 delay circuit 76 logical sum circuit 77 register 78 logical product circuit 81 delay Time adjustable delay circuit 82 Flip-flop

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuhiro Suzuki 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Digital Technology Co., Ltd. In-house (72) Inventor Yuji Miyagi 4 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1, Fujitsu Limited (72) Inventor Hiroshi Yamada 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Atsushi Suda 2-chome, Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture No. 3-9 Fujitsu Digital Technology Corporation In-house F-term (reference) 5K028 AA01 BB08 DD02 DD03 NN32 5K047 AA03 BB02 GG08 GG24 MM28 MM33 MM36 MM37 MM53

Claims (7)

[Claims] A clock signal extracted from an input signal;
A bit rate selection circuit for selecting a clock signal of a required bit rate from a clock signal generated from the extracted clock signal; and a bit rate selection circuit for selecting a clock signal having a maximum bit rate extracted from the input signal. A bit rate detection circuit for generating a selection signal to be supplied to the rate selection circuit. 2. A clock signal extracted from an input signal,
A bit rate selection circuit for selecting a clock signal of a required bit rate from a clock signal generated from the extracted clock signal, and a bit rate selection circuit for supplying a clock signal having a clock component generated from the input signal to the bit rate selection circuit A bit rate determination circuit for generating a selection signal. 3. A clock signal extracted from an input signal,
A bit rate selection circuit for selecting a clock signal of a required bit rate from a clock signal generated from the extracted clock signal; a signal identified and reproduced by the clock signal of the highest bit rate extracted from the input signal; A bit rate determination circuit for generating a selection signal to be supplied to the bit rate selection circuit from a waveform logically converted by a clock signal having the highest bit rate extracted from the bit rate determination circuit. 4. A clock signal extracted from an input signal,
A bit rate selecting circuit for selecting a clock signal of a required bit rate from a clock signal generated from the extracted clock signal; and a bit rate selecting circuit for detecting a switching point of the input signal.
A bit for generating a selection signal to be supplied to the rate selection circuit
A bit rate determination circuit, comprising: a rate detection circuit. 5. The bit rate determination circuit according to claim 1, wherein the bit rate detection circuit generates a selection signal to be supplied to the bit rate selection circuit during a training period. A bit rate determination circuit, comprising: 6. A receiver comprising the bit rate determination circuit according to claim 1. 7. A repeater comprising the bit rate determination circuit according to claim 1.