JP2000324023A - Line protection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce a transfer signal on a reception side without requiring a standby circuit even if a fault occurs to a signal line by allowing a transmission part to transmitting parallel data at an increased transfer rate with an error correction code to an error correction code is added by performing error encoding and a reception part to reproduces the transmit signal by decoding the received signal including the error correction code. SOLUTION: A data transfer system has the transmission part 71 and reception part 73 connected by a transmission line 72 composed of 24 independent signal lines; and the transmission part 71 transfers an input signal 70 which is inputted in the form of 24 parallel bits and the reception part 73 decodes the signal into a signal and outputs it as a signal 74. The transmission part 71 is equipped with a means which adds an error correction code to the inputted parallel 24-bit data by performing error correction encoding and transmits the data at a transfer rate increased by the added error correction code through the transmission line 72 and the reception part 73 is equipped with a means which reproduces the transmit signal by decoding the signal, including the error correction code, received from the transmission line 72.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a data transfer system. The present invention relates to a line protection method that can reproduce a transfer signal on a receiving side when a failure occurs in a signal line in a data transfer system that transmits a signal using a plurality of N independent signal lines.

[0002]

2. Description of the Related Art In a data transfer system for transmitting signals in parallel using a plurality of N signal lines, as a redundant configuration method for protecting signals, a protection line is prepared separately from a working line, and a failure occurs in the working line. There is an active / standby switching method for switching from an active line to a standby line when an error occurs.

[0003]

One of the problems of the working protection switching method is that at least one protection line must be provided separately from the working line, and at least one extra line is provided in the device configuration including the line. It is necessary.
Another problem is that a protocol for communication control is required, and a finite switching time is required. In order to share one protection line with multiple working lines,
When a failure occurs, it is necessary to clarify which working line uses the protection line, and communication for switching control must be performed between the transmission side and the reception side. Further, since the switching control is performed, a finite switching time is required for the active standby switching.

The present invention solves the problem of the working protection switching method, and does not require a protection line in addition to the working line, and can reproduce a transfer signal on the receiving side even if a failure occurs in a signal line. The purpose is to provide a protection scheme.

[0005]

According to the present invention, there is provided a line protection system in a data transfer system in which a transmission section and a reception section are connected by a plurality of N lines and which transfers parallel N-bit data. N error-correcting codes are added to the N pieces of parallel data, the number of error-correctable bits is 2 bits or more, and an error correcting code is added. , And the receiving unit includes means for decoding a signal including an error correction code received through N lines and reproducing a transmission signal.

The transmitting unit sets two of the N-bit input signals to be transferred as one block, adds an error correction code of half the number of blocks to this one block, and increases the data transfer rate to 3/2 times. Means for transferring,
The input signal is 24 bits, and the transmitting unit outputs
A means may be provided in which a 12-bit Golay error correction code is added to each 24 bits in 8-bit block units, and the data is transferred at a transfer rate 3/2 times that of a 36-bit input signal.

When transmitting parallel N-bit signals through a transmission line composed of N lines, the transmission unit instantaneously collects N bits of 1-bit data into N independent lines for N independent lines. Considering data, an error correction code is added to this N-bit data, and the data transfer rate is increased by the amount of the added error correction code, and transmitted over N lines. The receiving unit receives the signal to which the error correction code is added, performs error correction decoding, and reproduces the transmission signal. Due to the error correction code's correction capability, it is possible to reproduce the transmission signal even if a failure occurs on some lines in the transmission line, and to cope with failures such as signal loss in the transmission line without using a spare line can do.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of an embodiment of the present invention.

In this embodiment, a transmitting unit 71 and a receiving unit 7
3 are connected by a transmission line 72 composed of 24 independent signal lines, a transmission unit 71 transfers an input signal 70 input in parallel 24 bits, and a reception unit 73 decodes this to reproduce a signal. This is an example of a data transfer system that outputs the data as a signal 74. Here, the transmission unit 71 performs error correction coding on the input parallel 24-bit data, adds an error correction code, and increases the transfer rate by the added error correction code to generate 24 signals. The receiving unit 73 includes means for transmitting a signal including the error correction code received on the transmission line 72 having 24 signal lines and reproducing the transmission signal.

This operation will be described. The transmitting unit 71 considers, as the input signal 70, data obtained by collecting data of 24 1-bit data for each instant. The two input signals are 1
Blocks (A, B) 75 are set, and a 12-bit Golay error correction code is added to each 24-bit input signal. These are a and b. With this error correction code, the input error correction code 12 and the added error correction code 12
Error correction of up to 3 bits in 36-bit data is possible. Then, A, B, a, and b are set as one frame 76, and the data transfer rate is set to 3/2 times the input signal, and transmitted to the receiving unit 73 using the transmission path 72 including 24 signal lines. The receiving unit 73 performs error correction using the error correction code and reproduces the transfer signal. In the configuration of FIG. 1, when two signal lines are disconnected and a signal is disconnected,
Since the damage of each of the signal A and the signal B is 3 bits, a correct signal can be reproduced by the receiving unit 73.

Next, a detailed configuration of the line protection system of the present invention will be described with reference to FIG.

As shown in FIG. 2, a transmission unit 1 and a reception unit 2 are a data transfer system connected by a transmission line 5. The transmission unit 1 receives an input signal 3 and an input clock signal 4 and receives an error correction code. Is transmitted to the receiving unit 2 using the transmission path 5. The receiving unit 2 is configured to perform error correction on the received signal and transmit it as an output signal 6 and an output clock signal 7.

Here, the transmission section 1 is configured to add an error correction code to the input signal from the input signal 3 and the input clock signal 4 and transmit the input signal, and the error correction code calculation device 8, FIFOs 13, 16, 19, 22, Selector 12,
A first control device 9, a clock conversion device 10, and a second control device 11 are provided. The receiving unit performs error correction on the received signal, and outputs the output signal 6 and the output clock signal 7 as a configuration in which the distributor 40, the latches 39 and 42, the error correction devices 48 and 49, the clock generation device 52, A third control device 62 and a selection device 58 are provided.

Next, the data transfer operation in the data transfer system of FIG. 2 will be described.

In the transmitting section 1, the input signal 3 is transmitted to the FIFO1
3 and input to the FIFO 16. The error correction code calculation device 8 receives the input signal 3, calculates an error correction code to be added, and outputs it as a signal 34. Signal 34 is FIFO
19 and the FIFO 22. The FIFO 13 has control terminals 14 and 15, and when the rising of the control terminal 14 is detected, the input signal 3 is taken into the FIFO 13, and when the rising of the control terminal 15 is detected, the signal taken into the FIFO 13 is outputted as a signal 31. . This signal 31 is input to the selector 12. F
The FIFO 16 has control terminals 17 and 18, and when the rising of the control terminal 17 is detected, the input signal 3
When the rising of the control terminal 18 is detected, the signal captured by the FIFO 16 is transferred to the signal 3.
Output as 2. This signal 32 is input to the selector 12. The FIFO 19 has control terminals 20 and 21. When the rising of the control terminal 20 is detected, the signal 34 is taken into the FIFO 19, and when the rising of the control terminal 21 is detected, the signal taken into the FIFO 19 is output as a signal 33. This signal 33 is output from selector 1
2 is input. The FIFO 22 has control terminals 23 and 24. When the rising of the control terminal 23 is detected, a signal 34 is taken into the FIFO 22, and the control terminal 24 is controlled.
When the rising edge is detected, the signal taken into the FIFO 22 is output as the signal 60. This signal 60 is input to the selector 12.

The first controller 9 converts the input signal 3 into a FIFO
13 and the FIFO 16 and the signal 34 to the FIFO 19 and the FIFO
In order to alternately distribute the signals to the FO 22, the control signals 35 and 36 are generated from the input clock signal 4, and the control signal 36 is applied to the control terminals 14 and 20, and the control signal 35 is applied to the control terminals 17 and 2.
Output to 3 for input. The clock converter 10 generates a second clock signal 37 that is 3/2 times the input clock signal 4 used for transmission from the input clock signal 4,
The second clock signal 37 is input to the second control device 11. The second control device 11 includes four FIFOs 13, 16,
Control signals 28, 29, and 30 for generating a transmission signal 38 from the outputs of 19 and 22 are generated and output. Control signal 28
Is input to the control terminal 15 of the FIFO 13 and the control terminal 25 of the selector 12. The selector 12 has a control terminal 25
Is turned on, the output signal 31 of the FIFO 13 is output as the transmission signal 38 of the transmission line 5. The control signal 29 is F
Control terminal 18 of IFO 16 and control terminal 2 of selector 12
6 is input. When the control terminal 26 is on, the selector 12 outputs the output signal 32 of the FIFO 16 to the transmission signal 38 of the transmission line 5. The control signal 30 corresponds to the FIFO 19
, And 22 and the control terminal 27 of the selector 12. When the control terminal 27 is ON, the selector 12 outputs a 24-bit signal in which the output signal 33 of the FIFO 19 is set to the upper 12 bits and the output signal 60 of the FIFO 22 is set to the lower 12 bits as the transmission signal 38 of the transmission line 5.

According to the above configuration, a transmission signal 38 that forms one frame with 36 bits in which a 12-bit error correction code is added to a 2 × 24-bit input signal is generated and transmitted to the receiving unit 2.

The clock generator 52 of the receiving section 2 has a PL
L and a tank circuit, and extracts a clock signal from a signal received from the transmission line 5 to generate and output a third clock signal 53 having the same frequency as the second clock signal 37 in the transmission unit 1. In addition, a fourth clock signal 7 having the same frequency as the input clock signal 4 necessary for obtaining the output signal 6 of the transmitting unit 1 is generated.

The latch 39 latches the signal 38 with the third clock signal 53 and inputs the output signal 61 to the latch 42 and the error correction device 48. The latch 42 outputs the signal 61
Is latched by the third clock signal 53, and the output signal 47
Is input to the error correction device 49. The distributor 40 receives the signal 3
8 are output as a signal 43 and the lower 12 bits are output.
Is output as a signal 42. The signal 43 is sent to the error correction device 4
9 and the signal 42 is input to an error correction device 48.

The error correction device 49 receives the input signal 47
Error correction is performed on the basis of the signal and the signal 43. Here, the error-corrected signal 51 is input to the selection circuit 58. When the error is detected, the error correction device 49 holds the previous value without changing the signal 51. The error correction device 48 receives the input signal 6
Error correction is performed from 1 and the signal 42. Here, the error-corrected signal 50 is input to the selection circuit 58. When detecting an error, the error correction device 48 holds the previous value without changing the signal 50.

The third controller 62 controls the fourth clock signal 7
The control signal 57 is generated and output. The selection circuit 58 receives the signals 50 and 51 and is controlled by a control signal 57 for generating the output signal 6 of the receiving unit 2, and outputs the output signal 6 of the receiving unit 2. When detecting the rising of the control signal 57, the selection circuit 58 takes in the signal 51 and outputs it as a signal 6. When detecting the falling of the control signal 57, the selection circuit 58 takes in the signal 50 and outputs it as the signal 6.

As a result, the error-corrected signal 6 is generated from the transfer signal 38.

Next, the operation of FIG. 2 will be described with reference to the time charts of FIGS.

FIG. 3 is a time chart when the transmitting section 1 operates. The numerals shown in each waveform of FIG. 3 indicate the numbers assigned to the signal lines of FIG.

Formally, it is assumed that the input signal 3 is given in a time series as A → B → C → D like a waveform B. Output 3
The waveform C of No. 4 is shown by the small letter of the input signal. The waveform D of the signal 36 and the waveform E of the signal 35 are as shown in FIG.
Are alternately taken into the FIFOs 13 and 16. Signal 3
4 is similarly taken into the FIFOs 19 and 22. A second clock signal 37 having a waveform F is created from the waveform A of the signal 4. The waveform M of the signal 5 is selected by the selector 12 from the waveform J of the signal 31, the waveform K of the signal 32, and the signal L by the waveform G of the signal 28, the waveform H of the signal 29, and the waveform I of the signal 30. Created with Here, the waveform L is a waveform in which the signal 33 has the upper 12 bits and the signal 60 has the lower 12 bits. The signal 38 to which the error correction code is added is generated by the above operation.

FIG. 4 is a time chart when the receiving section 2 operates. The numerals shown in each waveform of FIG. 4 indicate the numbers assigned to the signal lines of FIG.

In FIG. 4, the signal received by the receiving unit 2 is denoted by "" in the alphabet. As the waveform C of the signal 43, the upper 12 bits of the waveform B of the signal 38 are output. Here, ［[1-12] indicates the upper 12 bits of the signal value 、, and ［[13-24] indicates the lower 12 bits of the signal value ○. Similarly, the waveform D of the signal 42 is obtained by outputting the lower 12 bits of the waveform B. Waveform G of signal 51
Performs error correction using the value of the waveform C at that time as an added error correction code, the value of the waveform F as a target signal value, and outputs a corrected result when no error is detected. . Since the waveform G at time 3 is the added error correction code a 'and the target signal value is A', the error is correctly corrected, and A is output. Here, even if there is damage to a ′ and A ′ due to the transmission line disconnection, both of them are 3 in total.
Up to bits are corrected.

In the waveform G at time 4, since the added error correction code is C '[1-12] and the target signal value is B', the error correction device 49 has detected an error and the signal 51
Holds the previous value, so that A is output as it is. Signal 5
The waveform H of No. 9 is an error correction code to which the value of the waveform D at that time is added, similarly to the waveform G, and the error correction is performed using the value of the waveform E as a target signal value. Since the corrected result is output, it is obtained as shown in FIG. The waveform K of the signal 50 is output by the selector 58 to the signal 7.
Of the signal 57 generated from the waveform I of FIG.
Is created by selecting from the H of the signal 50 of the waveform G. As described above, even if the transmission line is disconnected within an allowable range, the line protection can be performed by performing the error correction.

FIG. 5 shows a time chart at the receiving section when one signal line of the transmission line is cut off. The parentheses in the figure indicate how many bits of the signal have been damaged. At time 3 in FIG. 5, A ′ (1) and a ′ that have received 1-bit damage respectively due to a failure in the transmission path are provided to the error correction device 49.
Although (1) is input, even if the combined 36 bits are 2 bits of damage, the error is corrected accurately by the error correction device, and the waveform G is obtained. Similarly, B ′ (1) that has been damaged by one bit due to a failure in the transmission path and b ′ that has not been damaged are input to the error correction device 48, and finally the waveform K can be obtained. , Line protection is taking place.

[0031]

As described above, according to the present invention, when a fault on a transmission line within an allowable range can be reproduced by the receiving unit, the signal can be protected without a spare transmission line. The number of devices can be reduced. Further, even if a failure occurs in the transmission line, there is no instantaneous interruption, and this is advantageous as compared with the active standby switching method in which the active standby switching requires a finite time. In addition, since there is no need to perform communication for protection between the transmission unit and the reception unit, there is an advantage that a protocol for active / standby switching control is not required for the transmission unit and the reception unit. In addition, since an error correction code is used, a slight bit error on a transmission path is corrected, so that there is an advantage that the accuracy of signal transfer is increased.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an embodiment of the present invention.

FIG. 3 is a time chart illustrating an operation of a transmission unit.

FIG. 4 is a time chart showing the normal operation of the receiving unit.

FIG. 5 is a time chart illustrating an operation when a line disconnection of a receiving unit occurs.

[Description of Code] 1, 71 Transmitter 2, 73 Receiver 5, 72 Transmission Line 8 Error Correction Code Calculator 9 First Controller 10 Clock Converter 11 Second Controller 12 Selector 13, 16, 19, 22 FIFO 39, 42 Latch 40 Distributor 48, 49 Error Correction Device 52 Clock Generation Device 58 Selection Device 62 Third Control Device

Claims (3)

[Claims] 1. A line protection method in a data transfer system in which a transmission unit and a reception unit are connected by a plurality of N lines and transfer data of parallel N bits, wherein the transmission unit is configured to transmit N data in parallel. Means for performing error correction coding with two or more error-correctable bits to add an error correction code, increasing the transfer rate by the added error correction code, and transmitting the data over N lines, A line protection method comprising: a receiving unit that decodes a signal including an error correction code received through N lines and reproduces a transmission signal. 2. The transmitting unit sets two of the N-bit input signals to be transferred to one block, adds an error correction code of half the number of blocks to this one block, and increases the data transfer rate to 3/2 times. 2. The line protection method according to claim 1, further comprising a transfer unit. 3. The input signal is 24 bits, and the transmission unit adds a 12-bit Golay error correction code to each of the 24 bits in units of 48-bit blocks of the input signal, and transmits the 3 bits of the 36-bit input signal. 3. The line protection method according to claim 2, further comprising: means for transferring data at a transfer speed of / 2.