JP2000323675A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device and its manufacturing method in which a mass-storage memory and a highly integrated logic circuit can be combined in the semiconductor device having the semiconductor memory and the logic circuit. SOLUTION: The semiconductor device 1 is constituted by providing a semiconductor memory 5 and a logic cixrcuit 4, forming capacitor devices C above bit lines BL, forming a first metal layer 28 formed of a buried metal layer and connected to diffusion layers 13A or lower wiring layers 14 in a substrate 11, forming a first metal wiring layer 29 connected to the first metal layer 28 and approximately in parallel to the major surface of the substrate 11, forming a second metal layer 31 formed of a buried metal layer and connected to the first metal wiring layer 29, and forming a second metal wiring layer 32 on an insulating layer 30 in an upper layer than the capacitor devices C and connected to the second metal layer 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor memory such as a DRAM and a logic circuit are mounted, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the demand for an LSI in which a large-capacity semiconductor memory and a highly integrated high-speed logic circuit are mixed is rapidly increasing.

In order to realize a large-capacity semiconductor memory, a memory cell having a relatively good consistency with the process of forming a logic circuit and having a small unit cell area is suitable. As a small structure, a so-called COB (Capacitor Over Bitline) memory cell structure in which a capacitor is provided over a bit line is preferable.

However, this COB type memory cell structure has a large step due to a capacitance element and a bit line, so that it has been difficult to mount it in a highly integrated logic circuit.

On the other hand, in a process for manufacturing a high-performance logic circuit, it is required to reduce the resistance of a diffusion layer. As a method for solving both of these problems, a BMD (buried MMD) is used.
An etalon diffusion layer) structure has been proposed (see Japanese Patent Application No. 7-208072).

FIG. 10 is a schematic sectional view of a semiconductor device having the BMD structure and the semiconductor memory. The semiconductor device 101 includes a memory cell unit 102 and a peripheral circuit unit 103
, And a logic circuit 104 are mixedly mounted on the same semiconductor substrate 111. This semiconductor memory is a so-called DRAM (dynamic random access memory).
Access memory).

In the memory cell section 102, although not shown, a large number of parallel word lines WL and bit lines BL are arranged in a matrix. Then, above the bit line (BL) 119, the storage node electrode (lower electrode) 124 and the dielectric film 12
5 and a plate electrode (upper electrode) 126 are formed to form the above-mentioned COB type memory cell structure.

[0008] Storage node electrode (lower electrode) of capacitive element C
Reference numeral 124 is formed separately for each memory cell. The dielectric film 125 and the plate electrode 126 are commonly formed in a plurality (or all) of the memory cells.

In the peripheral circuit portion 103 and the logic circuit 104 of the semiconductor memory, the insulating films 115 and the stacked layers are connected so as to be connected to the diffusion layer 113A formed in the region in the semiconductor substrate 111 separated by the element molecular layer 112. 116,1
18, 120, 121, 122, 127, a first contact having a stacked structure of a barrier layer (adhesion layer) 128A having a stacked structure of, for example, a titanium film and a TiN film and a buried layer 128B made of a tungsten film is formed. Layer 128
Are formed.

Further, a second contact layer 129 having a similar laminated structure 129A, 129B is formed in a connection hole penetrating the flattening insulating layer 130 so as to be connected to the first contact layer 128. . The second contact layer 129 is a three-layer structure 131A, 131, which is an upper layer wiring formed on the planarizing insulating layer 130.
B, 131C are connected to the metal wiring layer 131.

In FIG. 10, 113B is the memory cell unit 1
02, a diffusion layer 114, 114 (114A, 114B) is a gate electrode having a two-layer structure, 117 is a contact layer of a memory cell,
Reference numeral 123 denotes a contact portion of the storage node electrode 124 of the capacitor C. 128 ′ is the first contact layer 1
This is the portion that remains when 28 is formed. In addition, a portion where the gate electrode 114 is formed wide indicates a portion connecting the bit line (BL) 119 of the memory cell portion 102 and the peripheral circuit portion 103. In this portion, the bit line (BL) 119 and the gate electrode 114 are connected by a plug-shaped contact layer 117 '. A dashed line extending leftward from the wide gate electrode 114 indicates that a word line (WL) of the semiconductor memory not present in this cross section is extended to the same height position as the gate electrode 114.

In the semiconductor device 101, the first contact layer 128 and the second contact layer 129 are formed by the above-mentioned B layer.
The upper layer wiring 131 and the diffusion layer 11 which have an MD structure and are largely separated due to a step formed by the capacitive element C
3A and the contact layer 1
By making the layers 28 and 129 made of metal, they can be connected with low resistance.

[0013]

However, even when this BMD structure is adopted, there are still the following problems. 1) In order to form a wiring layer with a high degree of integration, it is necessary to form a metal wiring layer 131 to be an upper wiring layer with a high degree of integration. Therefore, the contact layer 128 having the BMD structure,
After forming 129, the insulating layer 1 is entirely formed in order to further eliminate a step due to the capacitance element C in the memory cell portion 102.
It is necessary to perform the planarization by forming 30.

2) When local wiring is used, a structure in which the BMD structure itself is used for local wiring can be considered. In this case, a BMD structure is formed in a wide groove and connected to a diffusion layer and a lower wiring. However, in the case of using the trench-shaped local wiring, there is a possibility that junction leakage becomes remarkable at a portion crossing the element isolation region from the diffusion layer.

That is, as shown in FIG.
In the case of processing a groove reaching, the element isolation layer 112 is etched by so-called over-etching 141. In a more extreme case, the etching of the element isolation layer 112 proceeds beyond the depth of the diffusion layer 113A,
As shown by the thick arrows in FIG.
(140A, 140B) and the substrate 111 are short-circuited.

In this case, particularly by increasing the width of the groove, the SiO ₂ of the interlayer insulating film 116 and the S
It becomes difficult to obtain a selectivity with i ₃ N _4, and over-etching 141 easily occurs.

3) If the connection hole from the upper wiring layer to the BMD structure becomes too deep due to an increase in the height of the capacitance element with miniaturization, it becomes difficult to form the connection hole. Further, as the connection hole becomes deeper, the amount of over-etching when forming the connection hole also increases. Therefore, when the position of the connection hole is shifted from the BMD structure, that is, for example, as shown in FIG.
As shown in FIG. 1, a first contact layer 1 having a lower BMD structure
If the position of the connection hole is shifted with respect to 28, the first polycrystalline silicon layer (lower wiring) serving as gate electrode 114
And the connection hole reaches the diffusion layer 113A in the substrate 111, and there is a possibility that these 114 and 113A and the metal layer 129A of the contact layer formed in the connection hole are short-circuited.

The portion 150 deviated from the BMD structure 128, that is, the so-called trenching portion occurs because the reactive ion species and radicals for etching are reflected on the inner wall of the connection hole, and the etching rate is reduced. This is because it tends to increase.

In order to solve the above-mentioned problems, the present invention provides a semiconductor device having a semiconductor memory and a logic circuit, which can mix a large-capacity memory and a logic circuit with a high degree of integration. An object of the present invention is to provide a manufacturing method thereof.

[0020]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor memory and a logic circuit comprising a memory cell section and a peripheral circuit section are mixedly mounted on the same semiconductor substrate. In the memory cell section, a capacitor is formed above a bit line, and a semiconductor substrate is formed in the peripheral circuit section and the logic circuit. A first metal layer comprising a buried metal layer buried in a connection hole penetrating the insulating film is formed by being connected to a diffusion layer formed therein or to a lower wiring on a semiconductor substrate. A first metal wiring layer is formed substantially in parallel with the main surface of the semiconductor substrate, and a second metal layer comprising a buried metal layer buried in a connection hole penetrating the insulating film connected thereto. Is formed, and a second metal wiring layer is formed on the insulating layer above the capacitive element so as to be connected to the second metal layer.

According to the method of manufacturing a semiconductor device of the present invention, when manufacturing a semiconductor device in which a semiconductor memory including a memory cell portion and a peripheral circuit portion and a logic circuit are mixedly mounted on the same semiconductor substrate, a bit is formed in the memory cell portion. Forming a capacitive element above the line, forming an insulating film entirely over the capacitive element, and reaching a diffusion layer formed in the semiconductor substrate in the peripheral circuit portion and the logic circuit, or Forming an opening below the insulating film to reach the lower wiring on the semiconductor substrate, embedding a metal layer in the opening, and forming a metal wiring layer connected to the metal layer on the insulating film And a process.

According to the configuration of the semiconductor device of the present invention described above, since the second metal layer and the first metal layer are connected via the first metal wiring layer, the step caused by the capacitance element can be reduced. This can be alleviated by the first metal wiring layer.
Thereby, the second metal layer made of the buried metal layer can be made shallower.

According to the method of manufacturing a semiconductor device of the present invention described above, an opening is formed below an insulating film so as to reach a diffusion layer formed in a semiconductor substrate or to reach a lower wiring on a semiconductor substrate. By embedding a metal layer in the opening, the metal layer is connected to a diffusion layer or a lower wiring. Then, by forming a metal wiring layer connected to the metal layer on the insulating film in which the metal layer is embedded, the metal wiring layer is etched at the time of etching for forming a connection hole from the upper wiring. It can be used as a stopper so that the insulating film is not over-etched even if the etching position is shifted.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention comprises a semiconductor memory comprising a memory cell section and a peripheral circuit section and a logic circuit mixedly mounted on the same semiconductor substrate. In the memory cell section, a capacitor is formed above a bit line. Connected to a diffusion layer formed in the semiconductor substrate in the peripheral circuit portion and the logic circuit or to a lower wiring on the semiconductor substrate, and from a buried metal layer embedded in a connection hole penetrating the insulating film. A first metal layer is formed, and a first metal wiring layer is formed substantially parallel to the main surface of the semiconductor substrate in connection with the first metal layer, and is buried in a connection hole penetrating the insulating film by being connected to the first metal layer. A second metal layer made of a buried metal layer formed on the insulating layer, and a second metal wiring layer connected to the second metal layer on the insulating layer above the capacitor element.

The present invention also relates to the above semiconductor device,
The lower end face of the first metal wiring layer and the lower end face of the capacitive element, and the upper end face of the first metal wiring layer and the upper end face of the capacitive element are each at a height substantially coincident with the surface of the semiconductor substrate.

According to the present invention, in the above semiconductor device,
The first metal wiring layer is formed integrally with the first metal layer using the same metal material.

According to the present invention, there is provided the above-described semiconductor device,
The first metal wiring layer is also formed of a buried metal layer buried in a connection hole penetrating the insulating film.

According to the present invention, there is provided the above semiconductor device,
A first metal wiring layer made of a buried metal layer is also formed on a capacitor of a semiconductor memory via an insulating film.

The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor memory and a logic circuit comprising a memory cell portion and a peripheral circuit portion are mixedly mounted on the same semiconductor substrate. Forming a capacitive element, forming an insulating film entirely over the capacitive element, and reaching a diffusion layer formed in the semiconductor substrate in the peripheral circuit portion and the logic circuit or on the semiconductor substrate. Forming an opening below the insulating film so as to reach the lower layer wiring, embedding a metal layer in the opening, and forming a metal wiring layer connected to the metal layer on the insulating film 6 shows a method for manufacturing a semiconductor device.

Further, according to the present invention, in the method of manufacturing a semiconductor device, the step of forming a metal wiring layer is performed by forming a metal wiring layer on the entire surface of the insulating film and then patterning the metal wiring layer into a predetermined pattern.

Further, according to the present invention, in the method of manufacturing a semiconductor device, the step of forming a metal wiring layer is performed simultaneously with the step of forming a metal layer, and a metal layer for filling the opening is formed over the entire surface. Thus, a metal layer and a metal wiring layer are formed.

Further, in the present invention, in the method of manufacturing a semiconductor device, the step of forming a metal wiring layer includes the step of forming an interlayer insulating layer having a planarized surface covering the insulating film and the metal layer; This is performed by a step of forming a groove defining a wiring pattern in the insulating layer and a step of embedding a metal wiring layer in the groove.

First, as an embodiment of the present invention, FIG. 1 shows a schematic configuration diagram (plan view) of a semiconductor device. The semiconductor device 1 has a configuration in which a semiconductor memory 5 including a memory cell unit 2 and a peripheral circuit unit 3 and a logic circuit 4 are mixedly mounted on the same semiconductor substrate.

In the memory cell section 2, a large number of parallel word lines WL and bit lines BL are arranged in a matrix. In the peripheral circuit section 3, an address decoder or the like is provided as a drive circuit 6 for driving the word line WL. Although not shown, a drive circuit such as an address decoder is similarly provided for the bit line BL.

In the memory cell section 2, a diffusion layer 9 formed in the substrate is disposed obliquely. Since a capacitor is formed above the substrate as described later, the contact portion 8 (marked by x in the figure) connecting the storage node electrode of the capacitor and the diffusion layer 9 has no bit line BL or word line WL. This is because it needs to be formed at a position. Also, in the figure ○
Reference numeral 7 denotes a contact portion between the diffusion layer 9 and the bit line BL, and is formed at a position where there is no word line WL.

FIG. 2 is a sectional view taken along the line AA of the plan view of FIG. As shown in FIG.
Here, the memory cell unit 2, the peripheral circuit unit 3, and the logic circuit 4 of the semiconductor memory 5 are formed on the same semiconductor substrate 11. This semiconductor memory 5 has a DR like that of FIG.
It constitutes AM.

Then, in the memory cell section 2, the capacitive element C is formed above the bit line (BL) 19 to constitute the COB type memory cell structure described above.

First, in the memory cell section 2, the semiconductor substrate 1
1 is provided with a diffusion layer 13 in each region separated by the element isolation layer 12.
B is formed. This diffusion layer 13B is the diffusion layer 9 shown in FIG. These element isolation layer 12 and diffusion layer 1
The surface of 3B is covered with an insulating film 15 made of, for example, Si ₃ N ₄ or SiO ₂ . Further, the insulating film 15 is covered with an interlayer insulating layer 16 whose upper surface is flattened. A connection hole is formed at a position on the diffusion layer 13B between the insulating film 15 and the interlayer insulation layer 16, and a plug-shaped contact layer 17 is formed through the connection hole to connect to the diffusion layer 13B.

A bit line (BL) 19 is formed on the interlayer insulating layer 16 via an insulating film 18 in a two-layer structure 19A, 19B. The bit line 19 is formed of a nitride film (Si
It is covered with an insulating film 20 made of ₃ N _4). On this insulating film (nitride film) 20, an interlayer insulating layer 21 is formed. A connection hole is formed at a position on the contact layer 17 of the insulating film 18, the insulating film (nitride film) 20, and the interlayer insulating layer 21, and through this connection hole, the contact portion 23 of the storage node electrode indicated by a mark X in FIG. Are formed.

In the interlayer insulating layer 21, recesses are formed independently of each other corresponding to each memory cell of the memory cell section 2, and the storage nodes of the capacitive element C are filled so as to fill the recesses and extend further upward. An electrode (lower electrode) 24 is formed separately for each memory cell. This storage node electrode 24 is connected to the above-mentioned contact portion 23.

An insulating film (nitride film) 22 is formed between the storage node electrodes 24 of the interlayer insulating layer 21.
Then, a dielectric film 25 is formed to cover the insulating film (nitride film) 22 and the storage node electrode (lower electrode) 24, and a comb-shaped plate electrode (upper electrode) 26 is formed to cover the dielectric film 25. Have been. The dielectric film 25 and the plate electrode 26 are commonly formed in a plurality (or all) of the memory cells. These storage node electrodes (lower electrodes) 2
4. The above-described capacitance element C is constituted by the dielectric film 25 and the plate electrode (upper electrode) 26.

The capacitive element C is entirely composed of an interlayer insulating layer 27.
, And a flattening insulating layer 30 further covers it. The flattening insulating layer 30 is formed over the entire surface in common with the memory cell section 2 and the other portions 3 and 4, and a second metal wiring layer 32 to be described later is formed thereon as an upper wiring. .

On the other hand, in the peripheral circuit section 3 and the logic circuit 4 of the semiconductor memory, a diffusion layer 13A is formed in a region in the semiconductor substrate 11 separated by the element molecular layer 12. 2 is formed on the substrate 11 via a thin gate insulating film (not shown).
A gate electrode 14 having a layer structure 14A, 14B is formed.

The insulating film (nitride film) 15 covers the gate electrode 14, and the interlayer insulating layer 16 whose upper surface is flattened further covers the insulating film 15, similarly to the memory cell section 2. . On the interlayer insulating layer 16, the memory cell unit 2
Similarly to the above, an insulating film 18 and an insulating film (nitride film) 20 for covering the bit line 19 are formed by lamination. An interlayer insulating layer 21 is formed on the insulating film (nitride film) 20, similarly to the memory cell unit 2, and an insulating film (nitride film) 22 is formed thereon. On the insulating film (nitride film) 22, an interlayer insulating layer 27 that covers the capacitor C in the memory cell unit 2 is formed.

In FIG. 2, the portion where the gate electrode 14 is formed wide is the bit line (BL) 1 of the memory cell portion 2.
9 shows a portion connecting the peripheral circuit unit 9 and the peripheral circuit unit 3. In this portion, the bit line (B) is formed by the plug-like contact layer 17 '.
L) 19 and the gate electrode 14 are connected. Also,
The word lines WL provided at positions other than the position AA in FIG.
Although not shown, it is connected to the wide gate electrode 14 and further extended to the same height position as the gate electrode as shown by a broken line to the left.

In the present embodiment, the interlayer insulating layer 2
7 and a three-layer structure 2 substantially parallel to the main surface of the semiconductor substrate 11.
The first metal wiring layers 29 of 9A, 29B and 29C are formed. The first metal wiring layer 29 is formed, for example, of the Ti film 2
9A, an Al—Cu film 29B, and a TiN film 29C can be formed.

Further, below the first metal wiring layer 29, the laminated insulating films 15, 16, 18, 20, 20
A connection hole penetrating through the holes 1, 2, 27 is formed. In the connection hole, a barrier layer (adhesion layer) 28A having a laminated structure of, for example, a titanium film and a TiN film and a buried layer 28B composed of a tungsten film are formed. One contact layer 28 is formed. The first contact layer 28 allows the first
Metal wiring layer 29 and diffusion layer 13A or gate electrode 1
4 are connected.

The first metal wiring layer 29 is covered with the above-mentioned planarizing insulating layer 30, and the three-layer structure 32A, 32
B, 32C second metal wiring layers 32 are formed.
The first metal wiring layer 29 and the second metal wiring layer 32 are connected by a second contact layer 31 in a connection hole formed in the planarization insulating layer 30. The second contact layer 31 has the same laminated structure as the first contact layer 28. Further, the capacitance element C of the memory cell unit 2
Is connected between the upper electrode 26 and the second metal wiring layer 32 in the connection hole formed in the planarization insulating layer 30 and the interlayer insulating layer 27 and having the same configuration. .

In FIG. 2, reference numeral 28 ′ denotes an etching residue formed when the first contact layer 28 is formed. In this case, since no short circuit occurs with the second contact layer 31,
No problem in characteristics of the semiconductor device 1 occurs.

According to the configuration of the semiconductor device 1 of the present embodiment, the first metal wiring layer 29 is formed by the first contact layer 28 and the second contact layer 31 and the diffusion layer 13A or the second
Is formed, the first metal wiring layer 29 can be used as an etching stopper when a connection hole for the second contact layer 31 is formed, and the position of the etching can be shifted. , The occurrence of trenching can be prevented. Therefore, the short-circuit of the contact layer 31 due to the above-described over-etching does not occur, so that the incidence of defective semiconductor devices can be reduced.

The first metal wiring layer 29 is a metal layer and can be formed relatively thick, so that the resistance can be easily reduced.

Thus, the first metal wiring layer 29 can be used for the local wiring. When a local wiring is formed for the purpose of high integration, a step is usually newly generated. However, the above structure can be used to eliminate the step.

With the above-described effects, according to the present embodiment, the peripheral circuit section 3 and the logic circuit 4 can be further highly integrated.

Further, since the first metal wiring layer 29 can be formed thick, the difference in height between the lower end surface of the first metal wiring layer 29 and the lower end surface of the capacitive element C, and Both the height difference between the upper end surface of the wiring layer 29 and the upper end surface of the capacitive element C can be reduced. Thereby, the step formed by the capacitive element C can be reduced by the first metal wiring layer 29, and the second contact layer 31 can be formed shallow, that is, with a reduced aspect ratio. The contact layer 31 can be easily formed. In addition, the amount of over-etching when forming the connection hole for the second contact layer 31 can be reduced. More preferably, the height difference between the first metal wiring layer 29 and the upper end surface and the lower end surface of the capacitive element C is made substantially equal to each other with almost no difference in height.

Next, a method for manufacturing the semiconductor device 1 of the present embodiment will be described. 3 and 4 show manufacturing process diagrams of the semiconductor device 1 of the present embodiment. First, as shown in FIG. 3A, an insulating film (nitride film) 22 is formed by using a conventionally known method or the like.
After the formation, the capacitor C (24, 25, 26) is formed.

Next, as shown in FIG. 3B, a non-doped silicate glass, for example, is entirely covered with the low-pressure (reduced-pressure) CVD (chemical vapor deposition) using TEOS (tetraethylorthosilicate) to cover the capacitive element C. The interlayer insulating layer 27 is formed by depositing a film having a predetermined thickness, for example, about 150 nm by the method. Thereafter, the interlayer insulating layer 27 and the lower insulating films 15, 16, 18, 20, 21, 22 are added to
Contact hole 33 corresponding to BMD structure pattern
To form

Next, as the barrier layer 28A, for example, a TiN film is formed to a predetermined thickness, for example, about 50 nm, and a Ti film is formed to a predetermined thickness by using a long distance sputtering method or a collimated sputtering method. , For example, 30n
The layers are sequentially deposited to a thickness of about m. Further, the buried layer 28
As B, for example, a W film is formed to a predetermined thickness, for example, 600 nm.
Deposit to a thickness of the order.

Then, these layers are etched back to form a first contact layer 28 made of a buried metal layer in the contact hole 33 as shown in FIG. 4C. This step is basically the same as the manufacturing method used for forming a plug-like W film or the like using a normal blanket connection.

Next, the area excluding the memory cell section 2 is
As shown in D, the first metal wiring layer 29 is formed in a desired pattern. It is desirable that the first metal wiring layer 29 has a thickness such that the total thickness substantially matches the step of the memory cell. For example, as shown in FIG. 2, when the first metal wiring layer 29 has a laminated structure of the Ti film 29A, the Al—Cu film 29B, and the TiN film 29C, the step due to the capacitance element C of the memory cell unit 2 is, for example, 650 nm. If it is about, each Ti film 29A is, for example, about 100 nm,
The Al-Cu film 29B can be, for example, about 500 nm, and the TiN film 29C can be, for example, about 50 nm.

Subsequently, a flattening insulating layer 30 made of, for example, non-doped silicate glass is formed using a so-called high-concentration plasma CVD apparatus. At this time, since the first metal wiring layer 29 is provided in a portion other than the memory cell portion 2, the portion serves as a dummy for a step in the memory cell portion 2, and then is subjected to CMP (chemical mechanical polishing).
By performing the method, the upper surface of the wafer can be substantially flattened.

Then, a non-doped silicate glass having a predetermined thickness, for example, about 800 nm is deposited by, for example, a high-concentration plasma CVD method.
The non-doped silicate glass is deposited to a predetermined thickness, for example, about 1400 nm by a method, and is polished to a predetermined thickness, for example, about 1000 nm by a normal CMP method, whereby the flattening insulating layer 30 can be formed.

The flattening insulating layer 30 may be formed by only one growth method.

Subsequently, a connection hole is formed in the flattening insulating layer 30 by etching. At this time, the first metal wiring layer 2
9 can be used as an etching stopper, whereby over-etching of the underlying insulating film can be suppressed. Therefore, a short circuit due to over-etching does not occur, so that the incidence of defective semiconductor devices can be reduced.

Next, the second contact layer 31 is formed in the connection hole.
For example, a laminated film of, for example, a Ti film / TiN film of the barrier layer 31A and a W film of the buried layer 31B are sequentially formed.
The thickness of the barrier layer 31A is, for example, about 5 nm for a Ti film,
The TiN film can have a thickness of about 50 nm.

Further, a three-layer structure of, for example, a Ti film 32 A, an Al—Cu film 32 B, and a TiN film 32 C is formed as the second metal wiring layer 32 on the flattening insulating layer 30. Each film thickness is, for example, about 100 nm for the Ti film 32A,
Al-Cu film 32B is about 500 nm, TiN film 32C
Can be set to about 50 nm. Thereafter, although not shown, an insulating layer or the like covering the second metal wiring layer 32 is formed.
Thus, the semiconductor device 1 having the structure shown in FIG. 2 can be manufactured.

The second metal wiring layer 32, which is the upper wiring,
As a result, the word line W of the memory cell unit 2 of the semiconductor memory 5 is
L lining wiring or a shunt wiring of the drive circuit 6 such as a decoder of the peripheral circuit section 3 can be formed.

The first metal wiring layer 29, which is an in-layer wiring,
A so-called local wiring can be configured. The first metal wiring layer 29 corresponds to a first metal wiring layer in a normal logic circuit without a semiconductor memory.

Next, another embodiment of the present invention will be described. In this embodiment, the first metal wiring layer is formed integrally with the contact layer.

FIG. 5 is a schematic sectional view of a semiconductor device according to another embodiment of the present invention. The cross-sectional view of FIG. 5 corresponds to the cross-sectional view taken along line AA of the plan view of FIG.

In the semiconductor device 41, the first metal wiring layer 29 serving as an in-layer wiring is formed of the same material as the first contact layer 28 in FIG. 2, that is, the barrier layer 28A and the buried layer 28B, 28C and the first structure
And formed integrally with the contact layer.

The antireflection film 28C may not be formed depending on the material of the buried layer 28B and the second contact layer 31.

The other configuration is the same as that of the semiconductor device 1 shown in FIGS. 1 and 2, and therefore, the same reference numerals are given and the duplicated description will be omitted.

According to the semiconductor device 41 of the present embodiment,
It has the same effect as the semiconductor device 1 of the previous embodiment, and furthermore, by forming the first metal wiring layer 29 integrally with the underlying first contact layer using the same material,
By forming them simultaneously, the number of manufacturing steps can be reduced. Therefore, the manufacturing process is simplified.

A method for manufacturing the semiconductor device 41 will be described. First, the steps shown in FIGS. 3A and 3B of the semiconductor device 1 of the above embodiment are performed. That is, B is added to the interlayer insulating layer 27 and the lower insulating films 15, 16, 18, 20, 21, and 22.
A contact hole 33 corresponding to the pattern of the MD structure is formed.

Next, a Ti film, for example, having a predetermined thickness, for example, about 30 nm, is formed as a barrier layer 28A in a region excluding the memory cell section 2 so as to fill the contact hole 33.
An iN film is sequentially deposited at a predetermined thickness, for example, about 50 nm,
Further, for example, a W film is deposited as a buried layer 28B to a predetermined thickness, for example, about 500 nm, and a TiN film is deposited as an antireflection film 28C to a predetermined thickness, for example, about 70 nm. In addition, it is preferable that the total thickness of these films, for example, about 650 nm, is substantially equal to the height of the step due to the capacitor C.

As described above, the metal layer 28 is formed by integrally forming the first metal wiring layer 29 and the buried metal layer serving as the contact layer.

Next, instead of the etch-back performed in the previous embodiment, a desired wiring shape is formed on the integrated metal layer 28 by using a resist pattern as shown in FIG. To form a first metal wiring layer 29.

Thereafter, the semiconductor device 41 shown in FIG. 5 can be manufactured through the same steps as in the previous embodiment.

The above-mentioned first metal wiring layer 29 can also have a BMD structure. The case is shown below. FIG.
FIG. 13 is a schematic sectional view of a semiconductor device according to still another embodiment of the present invention. The cross-sectional view of FIG. 7 corresponds to the cross-sectional view taken along the line AA of the plan view of FIG. 1, as in FIG.

In the semiconductor device 51, a wide groove is formed in the interlayer insulating layer 35, and the above-described first metal wiring layer 36 composed of the barrier layer 36A and the buried layer 36B formed in the groove is used. It comprises a metal wiring layer.

In the above embodiment, the planarization insulating layer 30 is formed directly on the interlayer insulating layer 27 covering the capacitor C. In the present embodiment, however, the interlayer insulating layer covering the capacitor C is formed. An insulating film (nitride film) 34 is formed on the layer 27, and an interlayer insulating layer 35 is formed thereon. This nitride film 34
This is used as an etching stopper when forming a groove for burying the buried metal wiring layer 36. Therefore, the first
The contact hole in which the contact layer 28 of
This nitride film 34 also penetrates. In FIG. 7, reference numeral 37 denotes a planarizing insulating layer, and a combination of 35 and 37 corresponds to the planarizing insulating layer 30 in the above embodiment.

The other configuration is the same as that of the semiconductor device 1 shown in FIGS. 1 and 2, and therefore, the same reference numerals are given and the duplicated description will be omitted.

According to the present embodiment, the first metal wiring layer is formed thick by the buried metal wiring layer 36.
The step due to the capacitive element C is further eliminated, and the aspect ratio can be reduced by making the second contact layer 31 between the second metal wiring layer 32 shallower.

Thus, a contact hole for the second contact layer 31 can be formed more easily and with a reduced amount of over-etching.

A method for manufacturing the semiconductor device 51 will be described. First, the same steps as those shown in FIGS. 3A to 4C of the semiconductor device 1 of the above embodiment are performed. That is, the insulating film 1
5, 16, 18, 20, 21, 22, 27 are formed.

Next, a nitride film 34 is deposited to a thickness of, for example, about 100 nm by low pressure CVD or plasma CVD so as to cover the surface. Then, the nitride film 34 and the lower insulating film 1 are formed.
Contact holes penetrating these are formed at 5, 16, 18, 20, 21, 22, 27.

Next, a first contact layer 28 having a BMD structure is formed in the contact hole. Then, FIG.
As shown in A, an interlayer insulating layer 35 is formed to cover the surface.

Next, the interlayer insulating layer 35 is etched using the nitride film 34 as a stopper to
A groove having a pattern of 6 is formed.

The etching at this time is performed by using, for example, a magnetron plasma etching apparatus and using C ₄ F ₈ / CO / Ar / O ₂ =
8sccm / 150sccm / 200sccm / 3sc
cm, the etching may be performed under the conditions of a pressure of 5.3 Pa and an RF power of 1700 W.

Next, as the barrier layer 36A, for example, Ti
A film is sequentially deposited to a predetermined thickness, for example, about 30 nm, and a TiN film is sequentially deposited to a predetermined thickness, for example, about 50 nm.
As B, for example, a W film is deposited to a predetermined thickness, for example, 500 nm. Then, by performing etch back, FIG.
As shown in B, a buried metal wiring layer 36 is formed.

The buried metal wiring layer 36 may use another metal layer such as copper formed by a CVD method or a plating method.

Thereafter, the planarizing insulating layer 37, the second contact layer 31, and the second metal wiring layer 32 are formed, respectively, and the semiconductor device 51 shown in FIG. 7 can be formed.

Incidentally, like the semiconductor device 52 shown in FIG.
A buried metal wiring layer 36 having a BMD structure is also formed on the capacitive element C.
Is adopted, it is possible to configure the backing wiring of the word line WL with the metal wiring layer 36. Since the metal wiring layer 36 can be laid out on the memory cell section 2, the power supply lines can be strengthened and the integration degree can be increased.

The present invention is not limited to the above-described embodiment, and may take various other configurations without departing from the gist of the present invention.

[0095]

According to the present invention described above, by forming the metal wiring layer, the step due to the capacitance element can be eliminated and the connection hole from the upper wiring can be made shallower. Thereby, the metal layer can be easily formed in the connection hole.

Further, according to the present invention, at the time of etching for forming a connection hole, over-etching due to a shift in an etching position can be suppressed by using a metal wiring layer as an etching stopper. Therefore, a short circuit due to over-etching does not occur, so that the incidence of defective semiconductor devices can be reduced.

When the first metal wiring layer is formed integrally with the first metal layer composed of the buried metal layer by using the same material, the first metal wiring layer and the first metal layer Can be simultaneously formed to reduce the number of manufacturing steps. Therefore, the manufacturing process can be simplified.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram (plan view) of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic sectional view taken along line AA of FIG.

FIGS. 3A and 3B are process diagrams showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 4 is a process diagram showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 5 is a schematic sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a process chart showing a manufacturing process of the semiconductor device of FIG. 5;

FIG. 7 is a schematic sectional view of a semiconductor device according to still another embodiment of the present invention.

8A and 8B are process diagrams showing the manufacturing process of the semiconductor device of FIG. 7;

FIG. 9 is a schematic sectional view of a semiconductor device in a modified form of the semiconductor device of FIG. 7;

FIG. 10 is a schematic sectional view of a semiconductor device employing a BMD structure.

FIG. 11 is a diagram illustrating a problem when a BMD structure is used for local wiring.

FIG. 12 is a diagram illustrating a problem in manufacturing the semiconductor device of FIG. 10;

[Explanation of symbols]

1, 41, 51, 52 semiconductor devices, 2 memory cell sections, 3 peripheral circuit sections, 4 logic circuits, 5 semiconductor memories,
6 drive circuit, 7 bit line contact, 8, 23 storage node contact, 9, 13A, 13B diffusion layer, 1
Reference Signs List 1 semiconductor substrate, 12 element isolation layer, 14 gate electrode, 15, 18 insulating film, 16, 21, 27, 35 interlayer insulating layer, 17 contact layer, 19 bit line (B
L), 20, 22, 34 insulating film (nitride film), 24 storage node electrode, 25 dielectric film, 26 plate electrode, 2
8 first contact layer, 29 first metal wiring layer, 3
0,37 planarization insulating layer, 31 second contact layer,
32 second metal wiring layer, 33 contact hole, 36
Embedded metal wiring layer, WL word line, BL bit line, C capacitance element

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F064 BB14 CC09 CC23 EE22 EE26 EE27 EE33 EE34 GG03 5F083 AD24 AD48 AD49 GA28 JA36 JA39 JA40 JA56 KA02 KA20 LA10 MA06 MA17 MA20 PR03 PR06 PR38 PR39 PR40 PR45 PR55 ZA01 ZA12

Claims (9)

[Claims] 1. A semiconductor device in which a semiconductor memory comprising a memory cell portion and a peripheral circuit portion and a logic circuit are mixedly mounted on the same semiconductor substrate, wherein in the memory cell portion, a capacitive element is provided above a bit line. In the peripheral circuit portion and the logic circuit portion, a connection hole penetrating an insulating film by connecting to a diffusion layer formed in a semiconductor substrate or to a lower layer wiring on the semiconductor substrate. Forming a first metal layer made of a buried metal layer buried in the first metal layer; forming a first metal wiring layer substantially parallel to a main surface of the semiconductor substrate so as to be connected to the first metal layer; A second metal layer composed of a buried metal layer buried in a connection hole penetrating the insulating film is formed to be connected to the first metal wiring layer, and the second metal layer is formed on an insulating layer above the capacitor. The second metal layer Wherein a metal wiring layer is formed. 2. The semiconductor device according to claim 1, wherein a lower end surface of said first metal wiring layer and a lower end surface of said capacitance element, and an upper end surface of said first metal wiring layer and an upper end surface of said capacitance element are respectively substantially from the surface of said semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor devices have the same height. 3. The semiconductor device according to claim 1, wherein said first metal wiring layer is integrally formed of the same metal material as said first metal layer. 4. The semiconductor device according to claim 1, wherein said first metal wiring layer also comprises a buried metal layer buried in a connection hole penetrating an insulating film. 5. The semiconductor device according to claim 4, wherein said first metal wiring layer comprising said buried metal layer is also formed on a capacitor of a semiconductor memory via an insulating film. . 6. A method for manufacturing a semiconductor device, comprising: a semiconductor memory comprising a memory cell portion and a peripheral circuit portion; and a logic circuit mounted on the same semiconductor substrate, wherein the memory cell portion includes a portion above a bit line. Forming a capacitive element over the capacitive element, forming an insulating film entirely over the capacitive element, in the peripheral circuit portion and the logic circuit, so as to reach a diffusion layer formed in a semiconductor substrate. A step of forming an opening below the insulating film so as to reach a lower wiring on the semiconductor substrate; a step of embedding a metal layer in the opening; and a step of connecting the metal layer on the insulating film. Forming a metal wiring layer. 7. The method according to claim 6, wherein the step of forming the metal wiring layer is performed by forming a metal wiring layer on the entire surface of the insulating film and then patterning the metal wiring layer into a predetermined pattern. A method for manufacturing a semiconductor device. 8. The step of forming the metal wiring layer is performed simultaneously with the step of forming the metal layer, and after forming a metal layer that fills the opening over the entire surface, the metal layer and the metal layer are formed in a predetermined pattern. 7. The method according to claim 6, wherein the metal wiring layer is formed. 9. The step of forming the metal wiring layer includes the step of forming an interlayer insulating layer having a planarized surface covering the insulating film and the metal layer, and defining a wiring pattern in the interlayer insulating layer. 7. The method according to claim 6, wherein the method is performed by forming a groove to be formed and burying the metal wiring layer in the groove.