JP3033742B2 - Semiconductor memory and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory, and more particularly, to a dynamic random access memory (DRAM).
RAM, random read / write memory that requires memory holding operation)
In the memory cell section and the peripheral circuit section.

[0002]

2. Description of the Related Art Conventionally, as a DRAM has a higher density and a larger capacity, a DRAM having a capacitor over bit line (COB) structure having a stacked capacitor for holding data on a bit line has been used. ing. FIG. 3 is a cross-sectional view of an example of such a COB type DRAM. As shown in FIG. 3, in a conventional COB type DRAM, a gate electrode is separated and formed on a silicon substrate on which an element isolation region is formed, a pad polysilicon is formed between the gate electrodes, and a pad polysilicon is formed on the silicon substrate. A first interlayer insulating film 31 is formed on the entire surface. Then, a contact hole row is formed in the first interlayer insulating film 31 and the first interlayer insulating film 31 is formed via the bit contact 32.
A bit line 33 is provided above. Further, a second insulating layer 34 is formed on the entire surface of the bit line 33. Then, another contact hole row is formed, and the capacitor contact 35 is formed.
The capacitor lower electrode 36 is connected via the. On each of the capacitor lower electrodes 36, a capacitor insulating film 37 is formed. A capacitor upper electrode 38 is formed on the entire surface of the capacitor insulating film 37.

That is, in a conventional DRAM having a COB structure, in order to increase the capacity of a stack capacitor, a lower electrode of the stack capacitor is formed in another step after forming a bit line.

[0004]

However, the conventional COB type D
In the RAM, as shown in FIG. 3, a step occurs between a memory cell portion and a peripheral portion other than the memory cell region. For this reason, the focus margin in the lithography step of forming the metal wiring after the formation of the memory capacity thereafter is narrowed, which is a factor that hinders high integration and miniaturization.

Accordingly, it is an object of the present invention to reduce the level difference between the memory cell portion and the peripheral circuit portion, widen the focus margin in a later process, and achieve high integration and miniaturization of the DRAM.

[0006]

The semiconductor memory of the present invention to solve the above problems BRIEF SUMMARY OF THE INVENTION comprises a semiconductor substrate formed with a transistor on the surface, an interlayer insulating film formed on the semiconductor substrate, the interlayer Formed on insulating film,
And the lower electrode each connected bi <br/> Tsu preparative lines and capacitors to said transistor via Tohoru, for this capacitor
An insulating film for a capacitor formed on the lower electrode;
Upper electrode for capacitor formed on insulating film for capacitor
The bit line, the lower electrode for the capacitor,
Are formed of the same material as the same layer .
In addition, the semiconductor memory of the present invention has a memory cell region and a peripheral circuit.
Substrate with transistors formed on the surface of the circuit area
And a first interlayer insulating film formed on the semiconductor substrate;
Formed on the first interlayer insulating film in the memory cell region;
Are each said transistor via a contact hall
The connected bit line and the lower electrode for the capacitor, and
Capacitor insulation formed on lower electrode for capacitor
Film and the capacitor formed on the capacitor insulating film.
Including the upper electrode for the capacitor and the upper electrode for the capacitor
A second interlayer insulating film formed on the surface;
Another contact hole is formed on the second interlayer insulating film.
And an upper wiring connected to the semiconductor substrate via
The bit line and the capacitor lower electrode are the same.
It is formed as the same layer by the material. Also, the present invention
Semiconductor memory manufacturing method, the transistor is formed on the surface
Formed semiconductor substrate and formed on the semiconductor substrate
An interlayer insulating film, and a contact formed on the interlayer insulating film;
Vias connected to the transistors via
And a lower electrode for the capacitor and the lower electrode for the capacitor.
An insulating film for a capacitor formed on the lower electrode;
Upper electrode for capacitor formed on insulating film for capacitor
The bit line, the lower electrode for the capacitor,
Are semiconductors formed as the same layer with the same material
A method for manufacturing a memory, comprising: depositing the interlayer insulating film.
After the planarization, the bit line and the capacitor are
Open contact hole for lower electrode for paster at the same time
And deposit a metal film on the entire surface and pattern
Forming a bit line and a lower electrode for the capacitor,
A capacitor insulating film is deposited on the entire surface, and another metal film is
Is deposited and patterned to form an upper electrode for the capacitor.
The poles are formed.

That is, in the semiconductor memory of the present invention, the bit line and the lower electrode of the stack capacitor are connected to the same
It has a memory cell structure formed of layers and materials.

Further, a method of manufacturing a semiconductor memory according to the present invention
In order to manufacture the above-described semiconductor memory, the interlayer insulating film is deposited and planarized, contact holes for the bit lines and the lower electrode for the capacitor are simultaneously opened, and a metal film is deposited on the entire surface and patterned. Then, a step of depositing and patterning a capacitor insulating film on the entire surface and patterning by depositing another metal film on the entire surface is included.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor memory according to the present invention. As shown in FIG. 1, in the semiconductor memory of the present invention, an element isolation region 9 and diffusion regions 12, 1 are formed on a semiconductor substrate.
3 and 14 are formed to form a transistor, and a word line 8 and an interlayer insulating film 10 are formed. Then the interlayer insulating film 10, a contact hole for connecting the upper wiring 3. Then, a high dielectric constant insulating film 4 for a stack capacitor is formed on the interlayer insulating film 10. Furthermore,
On the high dielectric constant insulating film 4, an upper electrode 5 for a stack capacitor and an interlayer insulating film 11 are laminated. Further, a contact hole is formed in the interlayer insulating film 11 to form the upper wiring 3.

More specifically, as shown in FIG. 1, after forming transistors in the memory cell region 1 and the peripheral circuit region 2, an interlayer insulating film 10 containing phosphorus and boron is deposited, and heat treatment is performed. Alternatively, an oxide film is deposited and CMP (Chemical Mechanical Polishing) is performed to planarize.

Next, contact holes for the bit line 7 of the memory cell transistor and the lower electrode 6 for the stack capacitor are simultaneously opened.

Next, for example, a high melting point metal film is formed and patterned as the bit line 7 and the lower electrode 6 of the stack capacitor. After that, as the high dielectric constant insulating film 4,
For example, a perovskite dielectric film is formed, and a high-melting-point metal film, for example, is deposited and patterned as the upper electrode 5 for the stack capacitor. At the time of dry etching for patterning the upper electrode, the high dielectric constant insulating film 4 is used as an etching stopper.

Next, the interlayer insulating film 11 for the upper wiring 3 is flattened by CMP after depositing an oxide film.

Next, a contact hole for connecting the transistor region of the peripheral circuit 2 and the upper wiring 3 is opened.

Next, an upper wiring 3 is formed by depositing and patterning a high melting point metal or aluminum.

FIG. 2 is a plan view of the semiconductor memory of the present invention. 2, the semiconductor memory of the present invention, a memory cell having a stacked capacitor, is connected to the bit line 20 via the bit line configuration <br/> tact 21. Then, the stacked capacitor has a structure stacked on capacitor <br/> section electrode 22 and the lower electrode 25 for the stack capacitor is sandwiched a high dielectric constant insulating film 4. Further, this stack capacitor is connected to a transistor (not shown) by a lower electrode contact 24 for the stack capacitor. The word line 23 is used for selecting a memory cell.

In the semiconductor memory of the present invention, the step between the memory cell section and the peripheral circuit section is extremely small. Therefore, the stacked capacitors are densely arranged as shown in FIG.

[0019]

According to the present invention described above, the data line
In other words, since the memory cell structure has the bit line and the lower electrode of the stack capacitor formed of the same layer and material, the thickness of the interlayer between the bit line and the lower electrode of the stack capacitor and the thickness of the stack capacitor And the step difference from the area other than the memory cell becomes a step only for the upper electrode (1000 A to 3000 A) of the stack capacitor, and the focus margin in the lithography step of forming the metal wiring after the formation of the memory capacity is increased. High integration and miniaturization can be facilitated.

Further, according to the present invention, since the step is further reduced, the upper wiring and the Si layer are formed in a region other than the memory cell.
The aspect ratio of the contact hole for connecting the substrates can be reduced, and there is an effect of improving the contact property.

Further, according to the present invention, since the data line and the lower electrode of the stack capacitor are formed of the same layer and material, the number of photoresists (PR) can be reduced as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor memory of the present invention.

FIG. 2 is a plan view of a semiconductor memory of the present invention.

FIG. 3 is a plan view of a conventional COB type DRAM.

[Explanation of symbols]

REFERENCE SIGNS LIST 3 upper wiring 4 high dielectric constant insulating film 5 upper electrode for stack capacitor (high melting point metal) 6 lower electrode for stack capacitor (high melting point metal) 7 bit line 8 word line 9 element isolation region 10, 11 interlayer insulating film 12, 13 , 14 diffusion region 20 lower bit line 21 the bit line contact 22 stacked upper electrode 23 word lines 24 stacked capacitor capacitor electrode contact 25 lower electrode stacked capacitor

Claims (3)

(57) [Claims] A semiconductor substrate having a transistor formed on a surface of a memory cell region and a peripheral circuit region; a first interlayer insulating film formed on the semiconductor substrate; and a first interlayer insulating film in the memory cell region A bit line and a lower electrode for a capacitor formed on the lower electrode for the capacitor, the insulating film for the capacitor formed on the lower electrode for the capacitor, and the insulating film for the capacitor formed on the lower electrode for the capacitor. The upper electrode for the capacitor, and the second electrode formed on the front surface including the upper electrode for the capacitor.
A second interlayer insulating film, and an upper wiring formed on the second interlayer insulating film in the peripheral region and connected to the semiconductor substrate via another contact hole, wherein the bit line and the lower electrode for the capacitor are provided. Is a semiconductor memory formed of the same material and as the same layer. Wherein said capacitor insulating film, <br/> semiconductor memory according to claim 1, characterized in that the perovskite dielectric film. 3. A semiconductor substrate having a transistor formed on a surface thereof, an interlayer insulating film formed on the semiconductor substrate,
A bit line and a lower electrode for a capacitor formed on the interlayer insulating film and connected to the transistor via a contact hole; a capacitor insulating film formed on the lower electrode for the capacitor; A method for manufacturing a semiconductor memory including a capacitor upper electrode formed on a film, wherein the bit line and the capacitor lower electrode are formed as the same layer with the same material, wherein the interlayer insulating film A contact hole for the bit line and the lower electrode for the capacitor is simultaneously opened in the interlayer insulating film, and a metal film is deposited and patterned on the entire surface to form the bit line and the capacitor. Forming a lower electrode, depositing the capacitor insulating film over the entire surface, depositing another metal film over the entire surface, and patterning. The method of manufacturing a semiconductor memory, and forming an upper electrode for the capacitor.