JP2000323668A - Ferroelectric capacitor and circuit device equipped therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferromagnetic capacitor for suppressing residual polarization deterioration over aging. SOLUTION: A ferroelectric 6 is provided with a first pair of electrodes constituted of an electrode 2 and an electrode 3 and a second pair of electrodes constituted of an electrode 4 and an electrode 5. Then, opposite voltage are impressed to both pairs of electrodes. The ferroelectric 6 is polarized to opposite directions by a part where an electric field is impressed by the first pair of electrodes and a part where the electric field is impressed by the second pair of electrodes. The different directions of polarization is shown by arrows in the Fig. Thus, the oppositely polarized regions are made adjacent to each other so that the polarized state can be stabilized. In this case, comb-shaped electrodes are adopted as the electrodes, and both pairs of electrodes are arranged in a mutually complementary positional relation (in a state that the teeth of the combs are engaged with each other) so that the adjacent parts of both regions can be increased, and the stabilizing action can be further strengthened.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION

The present invention relates to a ferroelectric capacitor and a circuit device including the same, and more particularly, to a ferroelectric capacitor suitable for use in a semiconductor memory and the like and a circuit device including the same.

[0002]

2. Description of the Related Art In recent years, a semiconductor device using a ferroelectric capacitor, particularly, a ferroelectric memory (FRAM: Ferro-electric
Randam Access Memory) is gaining attention. This ferroelectric memory is called an ultimate memory because it has features such as high speed, large capacity, and low power, and has non-volatility. In a ferroelectric memory, generally, a voltage is applied to a ferroelectric capacitor by a field effect transistor MISF.
ET (Metal-Insulator-Semiconductor Field Effect T
ransistor), and its basic structure is the source of the field effect transistor MISFET,
The drain or gate is connected to one electrode of the ferroelectric capacitor. In this ferroelectric memory, FIG. 28 to FIG.
Various types have been developed as shown in FIG. The examples shown in FIGS. 28 to 31 will be described below.

First, the memory device shown in FIG. 28 will be described. The memory element of FIG.
73 and one ferroelectric capacitor 174 constitute one memory cell. This cell configuration is referred to as “1T1C
Structure ". FIG. 28 shows a total of four memory cells (cells), two vertically and two vertically. The connection relation in each memory cell is as follows. In other words, MISFET
The drain of 173 and one electrode of the ferroelectric capacitor 174 are connected. The other electrode of the ferroelectric capacitor 174 is connected to the plate line PL. MISFET1
The gate of 73 is connected to the word line WL, and the source is connected to the bit line BL.

The ON / OFF of voltage application through each bit line BL is controlled by the bit line control MISFET 176.
Done by This bit line control MISFET 17
6 itself (ON / OFF) is controlled by the bit line control M
Bit control line B connected to the gate of ISFET 176
This is done by the voltage applied through C. MISF
The ON / OFF of the ET 173 is determined by the MISFET 173
This is done by the voltage applied to the word line WL connected to the gate.

A plurality of the same bit lines BL are prepared according to the number of memory cells and the like. Therefore, when it is necessary to distinguish each bit line BL, it will be identified by attaching a number indicating the position of the memory cell in which the bit line is involved. For example, the bit line connected to the leftmost memory cell in the drawing is a bit line BL
(1). The same notation is used for the word lines WL, plate lines PL, and the like. For example, a word line connected to the uppermost memory cell in the drawing will be referred to as a word line WL (1). The same applies to other figures.

Next, writing to this memory element (FIG. 28) will be described. Here, a case where data is written to a cell connected to the word line WL (1) and the bit line BL (1) will be described as an example. Writing is performed on the bit line BL.
With the write voltage applied between (1) and the plate line PL (1), the bit line control MISFET 176 is turned on, and the word line WL (1) is used to turn on the cell to which data is to be written at that time. MISFET
173 is turned on. As a result, a voltage can be applied to the ferroelectric capacitor 174 to polarize the ferroelectric material constituting the capacitor. That is, data can be written. In this case, the direction of polarization can be changed by changing the direction of the applied electric field according to the data to be written. Note that writing can be performed collectively on cells connected to the same word line WL.

Next, reading of data from the memory element (FIG. 28) will be described. Here, the word line W
Description will be made by taking reading from a cell connected to L (1) and the bit line BL (1) as an example. First, by turning off the bit line control MISFET 176, the bit line BL (1) is brought into a floating state. Further, the MISFET 173 is connected through the word line WL (1).
Is turned on. Thereby, the plate line PL
A voltage can be applied to (1). In this case, depending on the direction in which the ferroelectric capacitor 174 is polarized, the bit line B
The amount of charge flowing out to L (1) is different. Therefore, the data written in this cell causes the bit line BL
The potential of (1) has a different value. Therefore, by comparing the potential of the bit line BL (1) with the reference potential given to the terminal REF by the differential sense amplifier 175 (1), data determination, that is, data reading can be performed. Note that reading can be performed collectively on cells connected to the same word line WL.

Next, the memory element shown in FIG. 29 will be described. The memory device of FIG. 29 has two MISFETs 1
77, 178 and two ferroelectric capacitors 179, 180 constitute one memory cell. This cell configuration is called “2T2C structure”. In FIG.
Each shows a total of two memory cells (cells).
The connection relation in each memory cell is as follows. That is, the drain of the MISFET 177 and the ferroelectric capacitor 1
79 is connected to one of the electrodes. Similarly, MIS
The drain of the FET 178 and one electrode of the ferroelectric capacitor 180 are connected. Ferroelectric capacitors 179, 180
Are connected to the same plate line PL. The gates of the MISFETs 177 and 178 are both connected to the same word line WL. MISFE
The source of T177 is connected to the bit line BL.
Similarly, the source of the MISFET 178 is connected to the bit line BL
Connected to inv. The same components as those shown in FIG. 28 are denoted by the same reference numerals.

Next, writing to this memory element (FIG. 29) will be described. Here, a case where data is written to a cell connected to the word line WL (1) and the bit lines BL (1) and BLinv (1) will be described as an example. Writing is
This is performed by applying a voltage corresponding to data to be written to the bit line BL (1), and applying a voltage corresponding to data opposite to the data to be written to the bit line BLinv (1).
At this time, the bit line control MISFET 176 is turned on, and the MISFET is controlled through the word line WL (1).
ET177 and 178 are turned on. As a result, a voltage can be applied to the ferroelectric capacitors 179 and 180 to polarize the ferroelectric material forming the capacitors. In this case, since different data is written in the two ferroelectric capacitors 179 and 180, the polarization states are different from each other.

Next, reading of data from the memory element (FIG. 29) will be described. Here, the word line W
The following describes an example of reading from a cell connected to L (1) and bit lines BL (1) and BLinv (1). By turning off the bit line control MISFET 176, the bit lines BL (1) and BLinv (1) are brought into a floating state. Then, the word line WL (1)
MISFETs 177 and 178 are turned on, and a voltage is applied to plate line PL (1). Then, from the ferroelectric capacitors 179 and 180, the bit line BL
(1), charge flows out to BLinv (1). in this case,
The amount of charge flowing out differs depending on the direction in which the ferroelectric is polarized. Therefore, the ferroelectric capacitors 179, 180
Bit line BL according to the data written to
The potential relationship between (1) and the bit line BLinv (1) is different. Therefore, bit line BL (1)
By determining the magnitude relationship between the potential of the bit line BLinv (1) and the potential of the bit line BLinv (1) by the differential sense amplifier 175 (1), data can be determined, that is, data can be read.

Next, the memory element shown in FIG. 30 will be described. The memory element of FIG.
3 and two ferroelectric capacitors 179 and 180, 1
One memory cell is configured. This cell configuration is referred to as “1
It is called "T2C structure". FIG. 30 shows a total of two memory cells, one at the top and one at the bottom. The connection relation in each memory cell is as follows. That is, the MISFET 17
3 and one electrode of two ferroelectric capacitors 179 and 180 are connected. The other electrode of the ferroelectric capacitor 179 is connected to the plate line PLa. The other electrode of the ferroelectric capacitor 180 is connected to the plate line P
Lb. The gate of the MISFET 173 is connected to the word line WL, and the source is connected to the bit line BL. The same components as those shown in FIG. 28 are denoted by the same reference numerals.

Next, writing to this memory element (FIG. 30) will be described. Here, a case where data is written to a cell connected to the word line WL (1) and the bit line BL (1) will be described as an example. Writing is performed on the bit line BL.
This is performed by setting the potentials of the two plate lines PLa (1) and PLb (1) to 0V at first and then changing to 5V in a state where a potential corresponding to the data to be written in (1) is applied. The details are as follows. That is, first, with the potentials of the two plate lines PLa (1) and PLb (1) set to 0 V, a potential corresponding to data to be written to the bit line BL (1), for example, 5 for data "1"
V, 0V is applied for data "0". Then, the bit line control MISFET 176 is turned on, and the MISFET 176 is turned on.
ET173 is turned on. Then, the ferroelectric capacitor 1
79 and 180 include plate lines PLa (1), PLb
A voltage corresponding to the difference between the potential of (1) and the potential of the bit line BL (1) is applied.

When the data to be written is "1", a voltage of 5V (= 5V-0V) is applied to the two ferroelectric capacitors 179 and 180, so that the polarization is increased. Occurs. On the other hand, if the data to be written is “0”, the two ferroelectric capacitors 1
Since a voltage of 0 V (= 0 V-0 V) is applied to 79 and 180 (that is, no voltage is applied), no polarization occurs.

Thereafter, two plate lines PLa (1),
The potential of PLb (1) is changed to 5V. Bit line BL
In (1), the state where the potential corresponding to the data to be written is kept applied. Then, when the data to be written earlier is “1”, a voltage of 0 V (= 5 V−5 V) is applied to the ferroelectric capacitors 179 and 180 (that is, no voltage is applied). Therefore, the polarization state does not change. Therefore, the polarization state generated when a voltage of 5 V is applied first is maintained. On the other hand, if the data to be written earlier is “0”, the ferroelectric capacitors 179 and 180 have −5 V (= 0 V).
Since a voltage of (−5 V) is applied, the polarization is performed in a direction opposite to that when the data is “1”.

Next, reading of data from the memory element (FIG. 30) will be described. Here, the word line W
Description will be made by taking reading from a cell connected to L (1) and the bit line BL (1) as an example. Initially, plate line P
La (1) and PLb (1) have their potentials set to 0V. After the bit line BL (1) is precharged to 2.5 V, the bit line control MISFET 176 is turned off, and its potential is set to a floating state. In this state, only the potential of the plate line PLa (1) is changed to 5V. The potential of the plate line PLb (1) is 0
Keep at V. Further, the MISFET 173 is turned on through the word line WL (1). Then, depending on the direction in which the ferroelectric is polarized (that is, depending on whether the data held in the ferroelectric capacitors 179 and 180 at this time is “1” or “0”), The potential of the bit line BL (1) changes to a potential higher or lower than 2.5V. Therefore, the potential of the bit line BL (1) and the reference potential applied to the terminal REF (here, 2.5
V) can be compared with the differential sense amplifier 175 (1) to determine data, that is, read data. In addition, such a type (FIG. 30)
Is disclosed, for example, in JP-A-64-66897.

Next, the memory element shown in FIG. 31 will be described. The memory element of FIG.
3 and one ferroelectric capacitor 174 and one sense MIS
One memory cell is constituted by the FET 181. FIG. 31 shows a total of two memory cells, one above and one below. The connection relation in each memory cell is as follows. That is, the gate of the sensing MISFET 181 and one electrode of the ferroelectric capacitor 174 are connected. The other electrode of the ferroelectric capacitor 174 is a MISFET
173 is connected to the drain. MISFET17
The source of No. 3 is connected to the write bit line BLw, and the gate is connected to the word line WL. MISFE for sense
The source of T181 is connected to the source line S, the drain is connected to the read bit line BLr, and the well is connected to the plate line PL. The same components as those shown in FIG. 28 are denoted by the same reference numerals.

Next, writing to this memory element (FIG. 31) will be described. Here, a case where data is written to a cell connected to the word line WL (1) and the bit lines BLw (1) and BLr (1) will be described as an example. Writing is performed by the bit line BLw (1) and the plate line PL (1).
After that, a write voltage is applied, and at this time, the MISFET 173 of the cell to which data is to be written is turned on through the word line WL (1). As a result, a voltage can be applied to the ferroelectric capacitor 174 to polarize the ferroelectric material constituting the ferroelectric capacitor 174. That is, data can be written. In this case, the direction of polarization is changed by changing the direction of the applied electric field according to the data to be written.

Next, reading of data from the memory element (FIG. 31) will be described. Here, the word line W
A description will be given by taking reading from a cell connected to L (1) and bit lines BLw (1), BLr (1) as an example. First, by turning off the bit line control MISFET 176, the bit line BLr (1) is brought into a floating state. Further, the word line WL (1) allows M
The ISFET 173 is turned on. Then, a minute voltage is applied to the bit line BLw (1), and a minute voltage is further applied to the source line S (1). In this case, the charge induced at the connection between the ferroelectric capacitor 174 and the gate of the sensing MISFET 181 differs depending on the direction in which the ferroelectric capacitor 174 is polarized. Therefore, the drain current flowing through the sensing MISFET 181 also differs depending on the polarization direction of the ferroelectric capacitor 174. As a result, the potential of the bit line BLr (1) has a different value according to the data written in the ferroelectric capacitor 174. Therefore, the potential of the bit line BLr (1) and the potential of the terminal
By judging the magnitude relationship between the reference potential given to REF and the differential sense amplifier 175 (1), data can be determined, that is, data can be read. This is the end of the description of the representative memory elements shown in FIGS.

As shown in FIG. 32, the internal structure of the ferroelectric capacitor used in these devices is generally such that a pair of plate-shaped upper and lower electrodes 182a and 183a are opposed to each other. The ferroelectric material 184 is interposed therebetween.

In addition, there is a ferroelectric capacitor having a structure as shown in FIGS. 33 and 34. In the example shown in FIG. 33, the basic structure of disposing a ferroelectric substance between a pair of electrodes is the same as that of FIG.
84b and an upper electrode 182b formed in a comb-like stripe structure. Note that, in contrast to the example of FIG. 33, the plate-shaped upper electrode 182a may be combined with the lower electrode formed in a comb-shaped stripe structure. A ferroelectric capacitor having such a structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 05-82803. In the example shown in FIG. 34, the basic structure of disposing a ferroelectric substance between a pair of electrodes is the same as that of FIG. 32, but the upper electrode 182b and the lower electrode 183b formed in a comb-like stripe structure are formed. Has been adopted. Then, both electrodes 182b,
The 183b is arranged in such a direction that the “comb teeth” intersect. A ferroelectric capacitor having such a structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 05-82802.

[0021]

However, in the structure of the conventional ferroelectric capacitor, a deterioration phenomenon called retention occurs in which the amount of remanent polarization decreases when stored for a long time after polarization. The causes of retention have not yet been fully elucidated, but are thought to be as follows.

That is, when a voltage is applied between the upper electrode and the lower electrode, the ferroelectric tends to polarize in the direction of the applied electric field. However, when adjacent crystals are polarized in the same direction, a repulsive force is generated between both crystal grains. Therefore, when the applied voltage is removed, the polarization direction of each crystal grain changes in a part of the ferroelectric material in an attempt to reduce the repulsive force. As a result, in the ferroelectric, a group of regions called domains having different polarization directions is formed. The generation of such domains having different polarization directions proceeds not only immediately after the applied voltage is removed, but also gradually over a long period of time. As a result, it is considered that a phenomenon (retention) in which the amount of remanent polarization of the entire capacitor continues to decrease over a long period of time occurs.

The present invention has been made in view of the above circumstances, and has as its object to provide a ferroelectric capacitor in which the amount of polarization is suppressed from being deteriorated, and a circuit device such as a semiconductor memory provided with the ferroelectric capacitor.

[0024]

According to a first aspect of the present invention, there is provided a circuit device having a ferroelectric capacitor, comprising: a capacitor made of a ferroelectric; It is characterized in that it comprises a polarizing means for polarizing a part of the region in a predetermined direction and for polarizing another region adjacent to the polarized region in the opposite direction.

According to a second aspect of the present invention, there is provided a circuit device having the ferroelectric capacitor according to the first aspect, wherein the region polarized in the predetermined direction and the other region polarized in the opposite direction. The region is characterized in that at least a part thereof is alternately arranged.

According to a third aspect of the present invention, the ferroelectric capacitor comprises a first electrode comprising a plurality of electrodes arranged to face each other.
, A second electrode pair composed of a plurality of electrodes arranged to face each other, and the second electrode pair is formed from the electrodes facing each other constituting the first electrode pair. And a capacitor member made of a ferroelectric, which is arranged integrally and continuously between the electrodes facing each other.

According to a fourth aspect of the present invention, in the circuit device, a voltage is applied to the ferroelectric capacitor according to the third aspect and the first electrode pair provided in the ferroelectric capacitor, and the second electrode is connected to the second electrode. The pair is characterized by having voltage applying means for applying a voltage that generates an electric field in a direction opposite to that of the first electrode pair.

According to a fifth aspect of the present invention, there is provided a ferroelectric capacitor, comprising: an intermediate electrode; a first electrode part of which is opposed to the intermediate electrode; On the opposite side, at least a part of the portion facing the intermediate electrode and not facing the intermediate electrode is the first electrode.
A second electrode disposed opposite to the electrode; and a ferroelectric capacitor member integrally disposed between the first electrode, the intermediate electrode, and the second electrode. It is characterized by.

According to a sixth aspect of the present invention, there is provided a circuit device for applying a voltage between the ferroelectric capacitor according to the fifth aspect and a first electrode and an intermediate electrode provided in the ferroelectric capacitor. And characterized in that:

According to a seventh aspect of the present invention, there is provided a ferroelectric capacitor, comprising: a common electrode; a first counter electrode disposed to face the common electrode; and the common electrode on the same side as the first counter electrode. A second counter electrode facing the electrode and arranged in parallel with the first counter electrode; and between the first counter electrode and the common electrode, the second counter electrode and the common electrode. And a capacitance member made of a ferroelectric material, which is disposed integrally and continuously between the first and second capacitors.

According to a circuit device according to an eighth aspect of the present invention, a voltage is applied between the ferroelectric capacitor according to the seventh aspect and a first counter electrode and a second counter electrode provided in the ferroelectric capacitor. By applying the electric field, an electric field connecting the first counter electrode and the second counter electrode via the common electrode is formed,
A voltage applying means for polarizing a region sandwiched between the common electrode and the first counter electrode and a region sandwiched between the common electrode and the second electrode in opposite directions; It is characterized by:

(Operation) The operation of the present invention will be described. First, the operation of the present invention will be described. The polarization unit polarizes a partial region of the capacitance member in a predetermined direction. In addition, another region adjacent to the polarized region is polarized in the opposite direction. When adjacent regions are polarized in opposite directions, repulsion is reduced. This stabilizes the polarization state, and as a result,
Deterioration of the polarization amount is suppressed. It is more effective if the regions polarized in the predetermined direction and the other regions polarized in the opposite direction are alternately arranged.

Next, the operation of the present invention will be described. The voltage applying means applies a voltage to the first pair of electrodes included in the ferroelectric capacitor. On the other hand, a voltage is applied to the second electrode pair so as to generate an electric field in a direction opposite to that of the first electrode pair. By forming regions having different polarization directions, the polarization state is stabilized, and deterioration of the polarization amount is suppressed.

The operation of the invention described in claims 5 and 6 will be described. The first electrode is partially disposed to face the intermediate electrode. On the other hand, the second electrode partially faces the intermediate electrode on the side opposite to the first electrode. Further, at least a part of the portion not facing the intermediate electrode faces the first electrode. And, between the first electrode, the intermediate electrode, and the second electrode, a capacitance member is arranged integrally and continuously. In this case, when the voltage applying means applies a voltage between the first electrode and the intermediate electrode, the capacitance member is polarized in a predetermined direction between the two electrodes. At this time, the second
When the potential of the electrode is in a floating state,
The potential of the second electrode is an intermediate potential between the potential of the first electrode and the intermediate electrode. Therefore, the capacitance member is polarized between the first electrode and the second electrode in the same direction as that between the intermediate electrode and the first electrode. On the other hand, between the second electrode and the intermediate electrode, the polarization is reversed. As a result, regions where the directions of polarization are opposite to each other are adjacent to each other, and the polarization state is stabilized. By positively controlling the potential of the second electrode,
A similar state may be created. The control in this case is such that the potential of the intermediate electrode becomes the highest or the lowest.

The operation of the present invention will be described. The voltage applying means applies a voltage between the first counter electrode and the second counter electrode provided in the ferroelectric capacitor, thereby connecting the first counter electrode and the second counter electrode via the common electrode.
An electric field is formed between the electrodes. Then, a region sandwiched between the common electrode and the first counter electrode and a region sandwiched between the common electrode and the second electrode polarize in opposite directions. As a result, the polarization state is stabilized.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. First Embodiment FIG. 1 is a diagram showing an outline of a ferroelectric capacitor according to a first embodiment of the present invention. FIG. 1A is a schematic plan view, and FIG. FIG. 2B is a schematic cross-sectional view taken along line AA in FIG. 2A, FIG. 2C is a schematic cross-sectional view taken along line DD, and FIG. FIG. 2 (e) is a schematic cross-sectional view along the line BB, FIG. 2 (a) is a schematic cross-sectional view along the line BB, and FIG. FIG. 9 is a schematic cross-sectional view showing a polarization state when a usage method A described later is applied, and FIG.
FIG. 9 is a schematic cross-sectional view showing a polarization state when (a) is applied.

The ferroelectric capacitor 1 of the first embodiment
As shown in FIGS. 1A to 1E, the first lower electrode 2, the first upper electrode 3, the second lower electrode 4, and the second
, And a ferroelectric material 6. The ferroelectric 6 is made of a material having ferroelectricity, and the whole is integrally connected. Therefore, the portion sandwiched between the first upper electrode 3 and the first lower electrode 2 and the second upper electrode 5 and the second lower electrode 4
The part sandwiched between and is connected to each other and to other parts.

The first upper electrode 3 and the first lower electrode 2 are formed as a pair, and are positioned between the two electrodes of the ferroelectric 6 by a voltage applied between the two electrodes. The polarization region is configured to be polarized. The first upper electrode 3 is disposed so as to be buried near the upper side surface in the figure inside the ferroelectric 6. As can be seen from FIG. 1A and the like, the shape of the first upper electrode 3 is such that slits are formed at various places and the whole is in a comb shape. Hereinafter, the elongated portion between the slits may be referred to as “teeth” of the comb. The same applies to the comb-shaped electrodes in other embodiments and examples. The first lower electrode 2 is embedded at a position directly below the first upper electrode 3 on the lower side surface of the ferroelectric 6 in the figure. The first lower electrode 2 has a comb shape that matches the shape of the first upper electrode 3. However, from the viewpoint of wiring, the back portion of the comb (FIGS. 1A, 1B, and 1C)
Of the first upper electrode 3 is protruded outside (left side in the figure) of the first upper electrode 3. Hereinafter, an electrode pair including the first upper electrode 3 and the first lower electrode 2 may be referred to as a “first electrode pair”.

The second upper electrode 5 and the second lower electrode 4 are formed as a pair, and a region located between the two electrodes of the ferroelectric 6 is formed by a voltage applied between the two electrodes. Is configured to be polarized. Second upper electrode 5
Are arranged on the upper side surface of the ferroelectric body 6 in the figure. As can be seen from FIG. 1A, the shape of the second upper electrode 5 is such that slits are formed at various places and the whole is in a comb shape. It has a comb shape. On the other hand, the second lower electrode 4 is embedded in the ferroelectric 6 at a position directly below the second upper electrode 5 in the drawing. This second lower electrode 4
Is shaped like a comb that matches the shape of the second upper electrode 5. However, for convenience in wiring, the back portion of the comb (the right end portion in FIGS. 1A, 1B, and 1C) is widened, and is located outside the second upper electrode 5 (in the drawing). (Right side). Hereinafter, the second upper electrode 5 and the second lower electrode 4
Is also referred to as a “second electrode pair”.

The first electrode pair and the second electrode pair, when viewed from the upper surface side of the ferroelectric 6, have a complementary positional relationship between the teeth of the comb, in other words, the teeth are engaged. They are arranged in a positional relationship (FIG. 1A). However, a predetermined interval is provided between the two electrode pairs, and they are not connected. Therefore, the potential of each of the electrodes can be independently set through a wiring not shown in this drawing.

A region where the first upper electrode 3 and the first lower electrode 2 face each other (that is, a region polarized by the first electrode pair), the second upper electrode 5 and the second lower electrode 2 Electrode 4
Are opposed to each other (that is, the region polarized by the second electrode pair), and are partially adjacent to each other. In the drawing, this adjacent region (hereinafter referred to as “adjacent portion”) r is surrounded by a dotted line.

Although FIG. 1 shows only a portion constituting a ferroelectric capacitor, the ferroelectric capacitor is actually formed on a substrate by forming an insulating protective film,
Often formed with wiring and the like.

Next, with reference to FIGS. 2A and 2B, a method of using the ferroelectric capacitor of this embodiment and its operation will be described. In FIGS. 2A and 2B, the direction of the electric field, that is, the polarization direction in each part of the ferroelectric 6 is represented by an arrow. Here, a method of using both the first electrode pair and the second electrode pair (method A) and a method of using only one electrode pair (method B) will be described.

(1) Method of use A First electrode pair (first upper electrode 3, first lower electrode 2)
Voltage. Then, polarization in a predetermined direction is generated in a portion of the ferroelectric material 6 sandwiched between the first electrode pairs. On the other hand, at this time, a voltage is applied to the second electrode pair (the second upper electrode 5 and the second lower electrode 4) such that an electric field is generated in the ferroelectric material 6 in a direction opposite to that of the first electrode pair. Apply.

In this state, as shown in FIG.
In the adjacent portion r, the directions of polarization are opposite to each other on both sides of the boundary corresponding to the gap corresponding to the gap between the electrode pair. That is, regions having different polarization directions are alternately arranged. Therefore, the polarization state generated by the first electrode pair (the first lower electrode 2 and the first upper electrode 3) and the second electrode pair (the second lower electrode 4,
The polarization state caused by the second upper electrode 5)
They can stably exist without repelling each other. Furthermore, they act so as to prevent the polarization states of the other party from being inverted, thereby stabilizing the polarization state of the other party. As a result, it is possible to reduce the deterioration of the polarization amount due to the repulsion of the polarization. In the present invention, the term “alternate” is not limited to a case in which a plurality of polarized regions in a certain direction are always present. As in the example of FIG. 17 described later, the concept includes a case where there is one region polarized in a certain direction and one region polarized in the opposite direction.

The interaction between regions having different polarization directions is larger as the distance between the regions is smaller. Therefore,
The size of the gap between the regions having different polarization directions (in the example of FIG. 2A, the first upper electrode 3 and the second upper electrode 5
(The size of the gap in the left-right direction in the figure) is smaller, the effect of stabilizing the polarization state is greater.

(2) Method of Use B A predetermined voltage is applied between the first upper electrode 3 and the first lower electrode 2. On the other hand, the second upper electrode 5 and the second lower electrode 4 are set to the same potential. Alternatively, the second upper electrode 5
At least one of the first and second lower electrodes 4 is set to a floating state. That is, an electric field forcing polarization is not generated from the second electrode pair.

In this state, as shown in FIG.
First electrode pair (first upper electrode 3 and first lower electrode 2)
In the region (slit) between adjacent teeth of the comb in FIG. 1, no electric field forcing polarization is generated. For this reason, although not shown in the figure, the polarization direction in the region where no electric field is generated naturally changes (adjusts) so as to maintain the polarization state generated in each region corresponding to each tooth. . Therefore, there is little repulsion between the polarization state occurring in the region corresponding to a certain tooth and the polarization state occurring in the region corresponding to the adjacent tooth. As a result, it is possible to reduce the deterioration of the polarization amount due to the repulsion of the polarization.
Hereinafter, between regions polarized in the same direction,
A region where no polarization has occurred may be referred to as a “relaxed region”. The effect of suppressing the amount of polarization degradation by such a relaxation region is greater as the relaxation region is wider.

Second Embodiment FIG. 3 is a diagram showing an outline of a ferroelectric capacitor according to a second embodiment of the present invention. FIG. 3A is a schematic plan view. 4B is a schematic cross-sectional view taken along the line AA in FIG. 4A, FIG. 4C is a schematic cross-sectional view taken along the line BB in FIG. It is a figure which shows the mode of polarization, and the figure (a) is a schematic cross section which shows the polarization state in case the later-described use method a or use method c is applied, and FIG. FIG. 9 is a schematic cross-sectional view showing a polarization state when a usage method b is applied.

The ferroelectric capacitor 10 according to the second embodiment
Are the first electrodes 11 as shown in FIGS.
, The second electrode 12, the third electrode 13, and the ferroelectric 1
4 is provided.

The first electrode 11 is disposed so as to be embedded in the ferroelectric 14. This first electrode 1
As can be seen from FIGS. 3 (a), 3 (b) and 3 (c), the shape of 1 has slits formed at various points, and is formed in a comb shape as a whole. The second electrode 12 is the first electrode 11
Is provided on the lower side surface of the ferroelectric body 14 in the drawing. The third electrode 13 is provided on the upper surface of the ferroelectric 14 in the figure in a state facing the first electrode 11.

The ferroelectric 14 is made of a material having ferroelectricity, and is integrally connected as a whole.
Therefore, the portion sandwiched between the first electrode 11 and the second electrode 12 and the first electrode 11 and the second electrode 12
Are connected to each other through the slit of the first electrode 11.

In FIGS. 3A, 3B and 3C, only the portion constituting the ferroelectric capacitor is drawn and drawn, but such a ferroelectric capacitor is actually Often, on a substrate, it is formed together with a protective film for insulation, wiring and the like.

Next, a method of using the ferroelectric capacitor according to the second embodiment and its operation will be described with reference to FIG. In FIG. 4, the difference in the direction of the electric field, that is, the direction of the polarization in each part of the ferroelectric 14 is represented by an arrow. Here, three different usage methods a, b, and c will be described.

(1) Method of Use a A voltage is applied between the first electrode 11 and the second electrode 12. Then, the first electrode 11 of the ferroelectric 14 is
Polarization (indicated by a downward arrow in FIG. 4A) occurs in a portion sandwiched between the first electrode 12 and the second electrode 12. On the other hand, at this time, polarization between the third electrode 13 and the second electrode 12 is opposite to that between the first electrode 11 and the second electrode 12 (in FIG. 4A, (Indicated by an upward arrow).

In this state, the polarization state generated between the first electrode 11 and the second electrode 12 and the third electrode 13
The polarization states generated between the second electrode 12 and the second electrode 12 are opposite to each other in the direction of polarization. Moreover, the gap between the regions polarized in opposite directions is extremely small. For this reason, the effect of stabilizing the polarization state is higher than in the first embodiment. Therefore, it is possible to more effectively suppress the polarization amount deterioration due to the repulsion generated between the regions polarized in the same direction. The stabilization of the polarization state in the case where the regions polarized in the opposite directions are alternately arranged adjacent (or close to each other) will be described in detail in the first embodiment with reference to FIG. It is as stated.

(2) Method of Use b A predetermined voltage is applied between the first electrode 11 and the second electrode 12. On the other hand, the third electrode 13 is set to the same potential as the second electrode 12. That is, the third electrode 13 and the second electrode 1
2 (that is, the first electrode 11)
(Corresponding to the gap between the teeth of the comb in FIG. 1), an electric field forcing polarization is not generated.

In this state, as shown in FIG. 4B, no electric field for forcing polarization is generated in a portion where the third electrode 13 and the second electrode 12 are directly opposed, and the relaxation region It has become. Therefore, although not shown in the drawing, the polarization direction in the relaxation region naturally changes (adjusts) so as to maintain the polarization state generated in each region corresponding to each tooth. Therefore, there is little repulsion between the polarization state occurring in the region corresponding to a certain tooth and the polarization state occurring in the region corresponding to the adjacent tooth. As a result, it is possible to reduce the deterioration of the polarization amount due to the repulsion of the polarization. The operation of the relaxation region is as described in detail in the first embodiment with reference to FIG.

(3) Method of Use c A predetermined voltage is applied between the first electrode 11 and the second electrode 12. The third electrode 13 is set in a floating state. Then, the third electrode 13 is kept at an intermediate potential between the first electrode 11 and the second electrode 12.
As a result, the state shown in FIG. 4A, that is, the electric field generated in the portion where the first electrode 11 and the second electrode 12 face each other and the third electrode 13 and the second electrode 12 The direction is opposite to that of the electric field generated in the opposing portion. For this reason, the polarization state of the part where the first electrode 11 and the second electrode 12 face each other, and the third electrode 13 and the second electrode 1
The polarization state of the portion where 2 is opposed can be stably present without repulsion from each other. Moreover, the gap between the oppositely polarized regions is extremely small (in principle, 0). Therefore, the action of stabilizing the polarization state is the first action.
Even higher than in the embodiment. Therefore, it is possible to more effectively suppress the polarization amount deterioration due to the repulsion generated between the regions polarized in the same direction. It should be noted that the stabilization of the polarization state when the regions polarized in opposite directions are alternately arranged adjacent to each other (or close to each other) is described in the first section.
This is as described in detail in the embodiment with reference to FIG.

Third Embodiment FIG. 5 is a diagram showing an outline of a ferroelectric capacitor according to a third embodiment of the present invention. FIG. 5A is a schematic plan view. FIG. 2B is a schematic cross-sectional view taken along line AA of FIG. The ferroelectric capacitor 15 according to the third embodiment has a lower electrode 1 as shown in FIGS.
6, an upper electrode 17, and a ferroelectric 18.

The lower electrode 16 is disposed so as to extend over the entire lower surface of the ferroelectric material 18 in the figure. On the other hand, the upper electrode 17
Are disposed on the upper side surface of the ferroelectric material 18 just above the lower electrode 16. As can be seen from FIGS. 5 (a) and 5 (b), the shape of the upper electrode 17 is provided with slits at various locations, and is formed in a comb shape as a whole. The upper electrode 17 and the lower electrode 16 are configured as a pair, and when a voltage is applied between the two electrodes, the applied voltage polarizes the region of the ferroelectric 18 located between the two electrodes. It is configured as follows.

The thickness of the ferroelectric material 18 varies depending on its location. That is, the region of the upper electrode 17 corresponding to the space between the teeth of the comb (slit) is thinner than the region immediately below the teeth. Specifically, the thickness is set to ３ or less of the thickness in a region immediately below the teeth of the comb.

In FIGS. 5 (a) and 5 (b), only the portion constituting the ferroelectric capacitor is drawn and drawn. However, such a ferroelectric capacitor is actually placed on the substrate. ,
It is formed together with a protective film for insulation, wiring, and the like.

In the ferroelectric capacitor according to the third embodiment, the portion corresponding to the gap (slit) between the teeth of the comb is partially thinned by removing the ferroelectric material 18. . For this reason, in this portion, the electric field for forcing polarization is very small as compared with the case where the ferroelectric 18 is not thinned, and this portion functions as a relaxation region. Therefore, there is little repulsion between the polarization state occurring in the region corresponding to a certain tooth and the polarization state occurring in the region corresponding to the adjacent tooth. As a result, it is possible to reduce the deterioration of the polarization amount due to the repulsion of the polarization. The operation of the relaxation region is as described in detail in the first embodiment with reference to FIG.

Fourth Embodiment FIG. 6 is a diagram showing an outline of a ferroelectric capacitor according to a fourth embodiment of the present invention. FIG. 6A is a schematic plan view. FIG. 2B is a schematic cross-sectional view taken along the line AA of FIG. 2A, and FIG. 2C is a schematic cross-sectional view taken along the line BB. The ferroelectric capacitor 20 of the fourth embodiment
Are the lower electrodes 21 as shown in FIGS.
, An upper electrode 22, and a ferroelectric 23. The lower electrode 21 and the upper electrode 22 are configured as a pair, and are arranged with the ferroelectric substance 23 interposed therebetween. The lower electrode 21 is embedded in the lower surface. On the other hand, the upper electrode 22 is arranged on the upper side surface in the figure.

The shapes of the upper electrode 22 and the lower electrode 21 are as follows.
In both cases, slits are formed at various places, and the whole is comb-shaped. In both cases, the dimensions of each part, particularly the width and length of the portion corresponding to the teeth of the comb, and the width of the gap (slit) between the teeth are the same. The upper electrode 22 and the lower electrode 21 are arranged such that the positions and directions of the “teeth” of the comb are aligned, and when viewed from the top in the figure, these “teeth” can be seen to overlap each other. (See FIG. 6A). However, the directions are exactly 180 opposite to each other. That is, two combs are arranged with their teeth facing each other.

In FIGS. 6A, 6B, and 6C, only the portion constituting the ferroelectric capacitor is extracted and drawn. However, such a ferroelectric capacitor is actually Formed on a substrate together with a protective film for insulation, wiring, and the like.

In the ferroelectric capacitor of this embodiment, when a voltage is applied between the upper electrode 22 and the lower electrode 21,
Polarization occurs in the ferroelectric substance 23 in a portion where the two oppose each other. However, since the electric field forcing the polarization is very small immediately below the gap (slit) between the teeth of the comb, no polarization occurs here. Therefore, the unpolarized portion functions as a relaxation region, and the polarization state is stabilized.
The operation of the relaxation region is as described in detail in the first embodiment with reference to FIG.

[0069]

Next, the present invention will be described more specifically with reference to examples. FIG. 7 shows the structure of a ferroelectric capacitor according to a first embodiment of the present invention. FIG. 7A is a schematic plan view, and FIG. FIG. 2A is a schematic cross-sectional view taken along line AA, FIG. 2C is a schematic cross-sectional view taken along line DD, and FIG. 2D is a cross-sectional view taken along line CC. FIG. 8 (e) is a schematic cross-sectional view along the line BB, and FIG.
FIGS. 4A to 4C are diagrams showing a process of forming a ferroelectric capacitor according to the first embodiment. FIGS. 4A to 4C are schematic cross-sectional views showing main processes, and FIGS. 9) is a schematic plan view showing a main step, and FIG. 9 is a view showing a step of forming a ferroelectric capacitor according to the first embodiment. FIGS. 9D and 9E are main views. It is a typical sectional view in a process.

The ferroelectric capacitor of the first embodiment is shown in FIG.
As shown in (a) to (e), the first platinum lower electrode 31
And a second platinum lower electrode 33 and a first platinum upper electrode 3
2, a second platinum upper electrode 34, and a ferroelectric Pb
(Zr, Ti) O ₃ (hereinafter, also simply referred to as PZT) film 35.

The first platinum upper electrode 32 and the first platinum lower electrode 31 are configured as a pair, and are positioned between the two electrodes of the PZT film 35 by a voltage applied between the two electrodes. Is configured to polarize the region to be polarized. The first platinum upper electrode 32 is disposed on the upper side surface of the PZT film 35 in the drawing. As can be seen from FIG. 7A, the shape of the first platinum upper electrode 32 is such that slits are formed at various places and the whole is in a comb shape. The first platinum lower electrode 31 is embedded below the PZT film 35 in the figure. The first platinum lower electrode 31 has a comb shape that matches the shape of the first platinum upper electrode 32. However, for the sake of wiring, the back of the comb (FIG. 7)
The left ends of (a), (b), and (c) are widened and protrude outside the first platinum upper electrode 32 (left side in the figure). Hereinafter, the first platinum upper electrode 32 and the first
Is also referred to as a “first electrode pair”.

The second platinum upper electrode 34 and the second platinum lower electrode 33 are configured as a pair, and are applied between the two electrodes of the PZT film 35 by a voltage applied between the two electrodes. It is configured to polarize the region where it is located.
The second platinum upper electrode 34 is arranged on the upper side surface of the PZT film 35 in the drawing. As can be seen from FIG. 7A, the shape of the second platinum upper electrode 34 is such that slits are formed at various places and the whole is in a comb shape. on the other hand,
The second platinum lower electrode 33 is embedded below the PZT film 35 in the figure. The second platinum lower electrode 33 has a comb shape matching the shape of the second platinum upper electrode 34. However, for convenience in wiring, the back portion of the comb (the right end in FIGS. 7A, 7B, and 7C) is widened, and is located outside the second platinum upper electrode 34 (see FIG. 7A). (Right side in the middle). Hereinafter, the second platinum upper electrode 34 and the second platinum
May be referred to as a “second electrode pair”.

The first electrode pair and the second electrode pair are PZT
On the film 35, the comb teeth are in a complementary positional relationship,
In other words, they are arranged in such a positional relationship that the teeth are engaged. However, a predetermined interval is provided between the two electrode pairs, and they are not connected. Therefore, the potential of each of the electrodes can be independently set through a wiring not shown in this drawing.

The distances h1, h2, and h3 between the two electrode pairs (that is, the distance between the first platinum lower electrode 31 and the second platinum lower electrode 33, and the distance between the first platinum upper electrode 32 and the second platinum upper electrode) The optimum value of the distance from the electrode 34) differs depending on the properties of the PZT film 35. In the case where the PZT film 35 is polycrystalline, it is desirable that this interval be equal to or smaller than the crystal grain size. This is because they are polarized in the same direction and repel each other mainly in the same crystal grain . P mentioned above
Since the particle size of ZT generally ranges from several tens nm to several thousand nm, the interval is preferably set to 1000 nm or less.

In FIGS. 7A to 7E, only the portion constituting the ferroelectric capacitor is drawn and drawn. However, such a ferroelectric capacitor is actually placed on the substrate. ,
It is formed together with a protective film for insulation, wiring, and the like.

Next, referring to FIG. 8 and FIG.
The procedure for forming the ferroelectric capacitor according to the example will be described.
First, a silicon oxide film 37 is formed on a silicon substrate 36. Next, a first platinum lower electrode 31 and a second platinum lower electrode 33 are formed on the silicon oxide film 37 (FIGS. 8A and 8A). These platinum lower electrodes 31, 3
3 is specifically formed as follows. That is, first, titanium is formed to a thickness of 50 nm on the silicon oxide film 37 by a sputtering method. The titanium film formed here becomes an adhesion layer for the platinum lower electrode. Further, platinum is deposited on this titanium film by sputtering.
Deposit only 0 nm. Subsequently, the platinum film and the titanium film are patterned into the shapes shown in FIGS. 8A and 8A. This patterning is performed by applying a resist to a platinum film, exposing and developing, and then performing reactive ion etching using an etching gas composed of argon, chlorine, and oxygen. Thus, the first platinum lower electrode 31 and the second platinum lower electrode 33 are formed.

Next, PZT is deposited so as to cover the silicon oxide film 37, the first platinum lower electrode 31, and the second platinum lower electrode 33, thereby forming a PZT film 35. Here, MOCVD (metal organic chemical v
The film is formed at a processing temperature of 450 ° C. using the apor deposition method.

Next, a first platinum upper electrode 32 and a second platinum upper electrode 34 are formed on the PZT film 35 (FIG. 8B). Specifically, first, platinum is formed to a predetermined thickness on the entire surface of the PZT film 35 by a sputtering method. Then, this platinum film is connected to the platinum lower electrode 31,
The first platinum upper electrode 32 and the second platinum upper electrode 34 are completed by patterning in the same manner as in the case of forming 33.

Subsequently, the PZT film 35 is patterned to remove unnecessary portions thereof (FIG. 8C,
(C ')). Specifically, it is performed as follows. First, P
By applying a resist on the ZT film 35 and the like, exposing and developing, a mask covering only a necessary portion is formed. Then, reactive ion etching is performed through this mask. A gas composed of argon, chlorine and oxygen was used as an etching gas. By the above processing, the PZT film 35
Can be patterned in the state shown in FIGS. 8C and 8C.

Next, TEOSCVD (Tetraethylorthos
Silicon oxide film 3 is formed by ilicate (SiOC ₂ H ₅ ) ₄ chemical vapor deposition) so as to cover the entire upper surface.
8 is formed (FIG. 9D).

Next, a contact hole for wiring connection is formed. This contact hole is formed in the silicon oxide film 38.
And the PZT film 35 by etching. Naturally, by forming a mask by applying, exposing, and developing a resist prior to etching, only a desired portion is removed by etching. In the portions where the contact holes are formed, the platinum lower electrodes 31, 33 or the platinum upper electrodes 32, 34 are exposed. After the contact holes are formed, 450 is used to recover the deterioration of the PZT film 35 due to the various processes performed so far.
Heat treatment is performed at about ° C.

Next, a wiring is formed (FIG. 9E). Here, a wiring layer having a stacked structure of a titanium nitride (TiN) layer 39 and an aluminum (Al) layer 40 is formed by using a sputtering method. Then, the wiring is completed by patterning the wiring layer. Each wiring is also formed in the previously formed contact hole, and is connected to the electrodes 31, 32, 33, and 34 here. Thus, the ferroelectric capacitor of the first embodiment is completed.

Next, an example in which the ferroelectric capacitor according to the first embodiment is applied to an actual circuit device will be described. Here, this ferroelectric capacitor (FIGS. 7, 8, and 9) is referred to as 1T2
A case where the present invention is applied to a memory having a C structure (FIG. 30) and a memory having a 2T2C structure (FIG. 29) will be described.

(1) Application of 1T2C Structure to Memory (FIG. 30) The first platinum upper electrode 32 is connected to the terminal T1 in FIG. Further, the first platinum lower electrode 31 is connected to the terminal T2.
Then, the second platinum lower electrode 34 is connected to the terminal T3, and the second platinum lower electrode 33 is connected to the terminal T1. Thereby, the first
Electrode pair (first platinum lower electrode 31, first platinum upper electrode 32) and second electrode pair (second platinum lower electrode 33,
Electric fields of opposite directions are applied to the PZT film 35 with the second platinum upper electrode 34). That is, of the ferroelectric capacitors, the first electrode pair (the first platinum lower electrode 3
1. A portion polarized by the first platinum upper electrode 32) is defined as a first ferroelectric capacitor 179, while a second electrode pair (a second platinum lower electrode 33 and a second platinum upper electrode 3) is used.
The portion polarized by 4) is changed to the second ferroelectric capacitor 18.
Used as 0.

In the 1T2C memory, the ferroelectric capacitor 179 and the ferroelectric capacitor 180 are polarized in the same direction during a write operation. However, as described above, if the connection of the two electrode pairs is reversed,
The directions of the adjacent portions of the two ferroelectric capacitors, that is, the polarization by the first electrode pair and the polarization by the second electrode pair are reversed. Therefore, the polarization state is stabilized.
The stabilization of the polarization state in the case where the regions polarized in the opposite directions are alternately arranged adjacent (or close to each other) will be described in detail in the first embodiment with reference to FIG. It is as stated.

(2) Application of 2T2C Structure to Memory (FIG. 29) The first platinum upper electrode 32 is connected to the terminal T1 in FIG. Further, the first platinum lower electrode 31 is connected to the terminal T2.
Next, the second platinum lower electrode 34 is connected to the terminal T3, and the second platinum lower electrode 33 is connected to the terminal T4. Thereby, the first
Electrode pair (first platinum lower electrode 31, first platinum upper electrode 32) and second electrode pair (second platinum lower electrode 33,
The second platinum upper electrode 34) applies an electric field in the opposite direction to the PZT film 35. That is, of the ferroelectric capacitors, the first electrode pair (the first platinum lower electrode 3
1. A portion polarized by the first platinum upper electrode 32) is defined as a first ferroelectric capacitor 179, while a second electrode pair (a second platinum lower electrode 33 and a second platinum upper electrode 3) is used.
The portion polarized by 4) is changed to the second ferroelectric capacitor 18.
Used as 0.

In a memory having a 2T2C structure, the ferroelectric capacitor 179 and the ferroelectric capacitor 180 are polarized in opposite directions during a write operation. Therefore, if the connection of the first electrode pair and the connection of the second electrode pair are made in the same direction as described above, the adjacent portions of the two ferroelectric capacitors, that is,
As a result, the directions of the polarization by the first electrode pair and the polarization by the second polarization are reversed. Therefore, the polarization state is stabilized in this portion. The stabilization of the polarization state in the case where the regions polarized in the opposite directions are alternately arranged adjacent (or close to each other) will be described in detail in the first embodiment with reference to FIG. It is as stated.

"Polarizing means" in the claims
Represents not only an electrode (here, the first platinum upper electrode 32 and the like) and a circuit (here, the MISFET 173 and the like) that applies a voltage to the capacitance member through this electrode, but also this electrode and a circuit that applies the voltage. Connection relationship (that is, 2
(A method of applying a voltage such that two electrode pairs generate electric fields opposite to each other). Regarding this point, in a circuit device configured to stabilize the polarization state by alternately arranging regions polarized in opposite directions,
The same applies to the case where the ferroelectric capacitors of other examples and other embodiments are applied.

Second Embodiment FIG. 10 shows the structure of a ferroelectric capacitor according to a second embodiment of the present invention. FIG. 10A is a schematic plan view and FIG. FIG. 11B is a schematic cross-sectional view taken along the line AA of FIG. 10A, and FIG. 11 is a view showing a process of forming a ferroelectric capacitor according to the second embodiment. , (B) is a schematic cross-sectional view in a main step, FIG. (A ′) is a schematic plan view in a main step, and FIG. 12 is a ferroelectric capacitor according to the second embodiment. FIG. 3C is a view showing a forming process, and FIGS.
(E) is a schematic cross-sectional view in the main step, and (c ′) and (e ′) are schematic plan views in the main step.

The ferroelectric capacitor of the second embodiment is shown in FIG.
0 (a) and (b), an Ir / IrO ₂ lower electrode 41, a first platinum upper electrode 42, a second platinum upper electrode 43, and a ferroelectric Pb (La, Zr, Ti)
And a film 44 of O ₃ (hereinafter, also simply referred to as PLZT).

The first platinum upper electrode 42 is formed of the PLZT film 4
4 is disposed on the upper side surface in the drawing. As can be seen from FIG. 10A, the shape of the first platinum upper electrode 42 is U
It is shaped. On the other hand, the second platinum upper electrode 43
It is arranged on the upper side surface of the PLZT film 44 in the figure. The shape of the second platinum upper electrode 43 is T-shaped, as can be seen from FIG. First platinum upper electrode 4
The shape patterns of the second and second platinum upper electrodes 43 can be viewed as a comb having only one tooth and a comb having only two teeth.

The second platinum upper electrode 43 has a T-shaped foot portion inserted into the U-shape formed by the first platinum upper electrode 42, in other words, the "teeth" of the comb are engaged. Are arranged in a proper positional relationship. However, a predetermined interval is provided between the first platinum upper electrode 42 and the second platinum upper electrode 43 and they are not connected. Therefore, the potentials of the two electrodes can be independently set through wirings not shown in FIG.

The Ir / IrO ₂ lower electrode 41 is formed by laminating iridium oxide (IrO ₂ ) and iridium (Ir), and is arranged below the PLZT film 44 in the drawing. The Ir / IrO ₂ lower electrode 41 is a first electrode.
Irrespective of the shapes of the platinum upper electrode 42 and the second platinum upper electrode 43, they are provided over the entire lower surface of the PLZT film 44. Therefore, the Ir / IrO ₂ lower electrode 41 faces both the first platinum upper electrode 42 and the second platinum upper electrode 43. That is, Ir / Ir
The O ₂ lower electrode 41 includes a first platinum upper electrode 42 and a second platinum upper electrode 42.
And a pair of the platinum upper electrodes 43. Therefore, by applying a voltage between the first platinum upper electrode 42 and the second platinum upper electrode 43 and the Ir / IrO ₂ lower electrode 41, the region of the PLZT film 44 sandwiched between these electrodes Is configured to be polarized.

In FIGS. 10 (a) and 10 (b), only the portion constituting the ferroelectric capacitor is drawn and drawn. However, such a ferroelectric capacitor is actually placed on the substrate. ,
It is formed together with a protective film for insulation, wiring, and the like.

Next, with reference to FIGS. 11 and 12, a description will be given of a procedure for forming the ferroelectric capacitor according to the second embodiment. Here, the element isolation region 46, the source diffusion region 47, the drain diffusion region 48, the gate insulating film 4
A case in which a ferroelectric capacitor is formed on a silicon substrate 45 on which a transistor, a resistor, and a capacitor including a transistor 9 and a gate electrode 50 are formed. Note that this gate electrode 5
0 is made of polysilicon, and the gate insulating film 49 and the element isolation region 46 are made of a silicon oxide film.

First, a silicon oxide film 51 is formed on the entire upper surface of the prepared silicon substrate 45 (FIG. 11).
(A)). Next, Ir / I is formed on the silicon oxide film 51.
An rO ₂ lower electrode 41 is formed. More specifically, first, only the portion of the silicon oxide film 51 located above the source diffusion region 47 is etched to expose the source diffusion region 47 of some transistors. Subsequently, iridium oxide is deposited on the entire surface by sputtering to a thickness of 10 mm.
A film is formed with a thickness of 0 nm. Further, iridium is formed to a thickness of 100 nm by a sputtering method.

Next, a PLZT film 44 is formed on the entire upper surface (FIG. 11B). Specifically, a sol-gel solution of PLZT is applied by a spin coating method, and thereafter,
PLZ by firing in oxygen at 600 ° C for 30 minutes.
A T film 44 is formed.

Next, a first platinum upper electrode 42 and a second platinum upper electrode 43 are formed on the PLZT film 44. Specifically, first, platinum is formed to a predetermined thickness on the entire surface of the PLZT film 44 by a sputtering method. Then, by patterning this platinum film by the same method as that for forming the Ir / IrO ₂ lower electrode 41,
The first platinum upper electrode 42 and the second platinum upper electrode 43 are completed.

Next, the PLZT film 44 and the Ir / IrO ₂ lower electrode 41 are patterned to remove unnecessary portions thereof (FIGS. 12C and 12C '). The specific processing is as follows. That is, a resist having a desired pattern is formed by applying a resist and exposing and developing the resist.
Thereafter, the PLZT film 44 and Ir
/ IrO ₂ lower electrode 41 is etched. Here, this etching is performed by reactive ion etching using an etching gas composed of argon, chlorine and oxygen. By the above processing, the PLZT films 44 and I
The r / IrO ₂ lower electrode 41 is shown in FIGS.
Is patterned as shown in FIG. Next, a silicon oxide film 53 is formed so as to cover the entire upper side surface.
(D)).

Next, contact holes 54 for wiring connection
Is formed (FIGS. 12E and 12E). The contact hole 54 is formed between the silicon oxide film 53 and the PLZT film 4.
4 is formed by etching. Naturally, by forming a mask by applying, exposing, and developing a resist prior to etching, only a desired portion is removed by etching. In the portion where the contact hole is formed, the Ir / IrO ₂ lower electrode 41, the first platinum upper electrode 42, or the second platinum upper electrode 43 is exposed. After forming the contact holes, a heat treatment is performed at about 600 ° C. in order to recover the deterioration of the PLZT film 44 due to the various processings performed so far.

Next, a wiring is formed. Here, a stacked structure of titanium nitride and aluminum, which are wiring layers, is formed by a sputtering method. Then, the wiring is completed by patterning the wiring layer. Each wiring is also formed in the previously formed contact hole, where the Ir / IrO ₂ lower electrode 41 and the first platinum upper electrode 4
It is connected to the second or second platinum upper electrode 43.
Thus, the ferroelectric capacitor of the second embodiment is completed.

Next, an example in which the ferroelectric capacitor according to the second embodiment is applied to an actual circuit device will be described. Here, this ferroelectric capacitor (FIGS. 10, 11, and 12) is set to 1T.
A case where the present invention is applied to a memory having a 1C structure (FIG. 28) will be described. The first platinum upper electrode 42 is connected to the terminal T1 of FIG.
Next, the Ir / IrO ₂ lower electrode 41 is connected to the terminal T2. The second platinum upper electrode 43 is connected to the terminal T2.

In this case, the first platinum upper electrode 42 and Ir
/ IrO ₂ in the region sandwiched by the lower electrode 41,
The PLZT film 44 is polarized. However, since the second platinum upper electrode 43 and the Ir / IrO ₂ lower electrode 41 have the same potential, in a region sandwiched between the electrodes 41 and 43,
The PLZT film 44 is not polarized. Further, the PLZT film 4 is also provided in a region below a portion where no electrode is provided between the first platinum upper electrode 42 and the second platinum upper electrode 43.
4 is not polarized. Therefore, since such a non-polarized portion functions as a relaxation region, the polarization generated by the first platinum upper electrode 42 and the Ir / IrO ₂ lower electrode 41 is stabilized. In addition, regarding the action of the relaxation region,
This is as described in detail in the first embodiment with reference to FIG.

In the example described with reference to FIGS. 11 and 12, the ferroelectric capacitors (particularly, the upper electrodes 42 and 43) are formed immediately above the source diffusion region 47 of the transistor. The position where the ferroelectric capacitor is formed is not limited to just above the source diffusion region 47. It may be formed at another position according to the convenience of wiring with other elements formed on the substrate. For example, as shown in FIG. 13, a ferroelectric capacitor (particularly,
2, 43) can also be formed. Further, a ferroelectric capacitor may be formed on the gate electrode 50. In the configuration in which the ferroelectric capacitor is arranged above the gate electrode 50, the gate electrode 50 and the ferroelectric capacitor are directly connected.
This structure is suitable for the memory element having the structure shown in FIG.

Third Embodiment FIG. 14 shows a structure of a ferroelectric capacitor according to a third embodiment of the present invention. FIG. 14A is a schematic plan view and FIG. FIG. 15B is a schematic cross-sectional view taken along the line AA in FIG. 15A, and FIG. 15 is a view showing a process of forming a ferroelectric capacitor according to the third embodiment. (B) is a schematic cross-sectional view in a main step, FIGS. (A ′) and (b ′) are schematic plan views in a main step, and FIG. 16 is a third embodiment. FIGS. 3C and 3D are schematic cross-sectional views of main steps, and FIGS. 3D and 3D are schematic cross-sectional views of main steps. It is a top view. Third
FIGS. 14A and 14B show the ferroelectric capacitor 60 of the embodiment of FIG.
As shown in FIG. 5, the first electrode comprises a first platinum lower electrode 61, a second platinum lower electrode 62, an Ir / IrO ₂ upper electrode 63, and a PZT film 64 which is a ferroelectric.
First platinum lower electrode 61 and second platinum lower electrode 62
Are arranged at predetermined intervals on the lower side surface of the PZT film 64 in the figure. Therefore, the potentials of the two electrodes can be independently set through wirings not shown in FIG.

The Ir / IrO ₂ upper electrode 63 is formed by laminating iridium oxide and iridium.
It is arranged above the PZT film 64 in the figure. This Ir /
The IrO ₂ upper electrode 63 extends over the entire upper surface of the PZT film 64 irrespective of the shapes of the first platinum lower electrode 61 and the second platinum lower electrode 62. Therefore, the Ir / IrO ₂ upper electrode 63 faces both the first platinum lower electrode 61 and the second platinum lower electrode 62. For the sake of drawing convenience, in this figure, the distance between the first platinum lower electrode 61 and the second platinum lower electrode 62 is I
The size of the r / IrO ₂ upper electrode 63 is approximately equal to the distance between the first platinum lower electrode 61 and the second platinum lower electrode 62. However, in practice, Ir / IrO ₂
The distance between the upper electrode 63 and the first platinum lower electrode 61 and the second platinum lower electrode 62 is made shorter.

In FIGS. 14 (a) and 14 (b), only the portion constituting the ferroelectric capacitor is drawn and drawn. However, such a ferroelectric capacitor is actually placed on the substrate. ,
It is formed together with a protective film for insulation, wiring, and the like.

Next, with reference to FIGS. 15 and 16, a description will be given of a procedure for forming a ferroelectric capacitor according to the third embodiment. Here, the element isolation region 66, the source diffusion region 67, the drain diffusion region 68, the gate insulating film 6
A case in which a ferroelectric capacitor is formed on a silicon substrate 65 on which a transistor including a transistor 9 and a gate electrode 70, a resistor, a capacitor, an interlayer insulating film 71, a wiring, a plug 72 connecting the wiring layers, and the like are formed. The gate electrode 70 is made of polysilicon, and the gate insulating film 69 and the element isolation region 66 are made of a silicon oxide film. The interlayer insulating film 71 is made of a silicon oxide film. The plug 72 is a laminated structure of tungsten / titanium nitride (W / TiN). The wiring is made of titanium nitride / titanium (TiN / Ti) layer 73 and titanium nitride / aluminum (T
(iN / Al) layer 74.

First, a silicon oxide film 75 is formed on a silicon substrate 65 prepared in advance.
(A), (a ')). Next, a contact hole for wiring connection is formed. This contact hole is formed by etching the silicon oxide film 75. Naturally, by forming a mask by applying, exposing, and developing a resist prior to etching, only a desired portion is removed by etching. The wiring layer (TiN / Al layer 74) is exposed at the portion where the contact hole is formed as described above.

Next, a second plug 76 is formed in the contact hole. More specifically, first, titanium nitride and tungsten (W) are formed over the entire upper surface by a CVD method to bury the contact holes. Thereafter, the entire upper surface is etched until the silicon oxide film 75 is exposed. Thereby, the stacked structure of tungsten / titanium nitride (W / TiN) formed earlier remains only in the contact hole. Then, the remaining tungsten / titanium nitride becomes the second plug 76.

Next, a first platinum lower electrode 61 and a second platinum lower electrode 62 are formed on the second plug 76 (FIGS. 15B and 15B). Specifically, on the entire surface,
Titanium is formed to a thickness of 30 nm by sputtering. Further, by sputtering, platinum was deposited to a thickness of 200 n.
m is formed. Subsequently, a resist having a desired pattern is formed by applying a resist, exposing and developing the resist. Thereafter, the platinum film and the titanium film are etched into a desired shape through the mask, whereby the first platinum lower electrode 61 and the second platinum lower electrode 62 are formed.

Next, the silicon oxide film 75, the first platinum lower electrode 61 and the second platinum lower electrode 62 are
The PZT film 64 is formed by depositing PZT.
Here, the film is formed at a processing temperature of 450 ° C. by using the MOCVD method.

Next, on the PZT film 64, Ir /
An IrO ₂ upper electrode 63 is formed (FIG. 16C). Specifically, first, iridium oxide and iridium having a thickness of 10 are formed on the entire upper surface of the PZT film 64 by a sputtering method.
Films are formed at 0 nm each. Thereby, Ir / IrO ₂ upper electrode 6 having a laminated structure of iridium oxide and iridium
You can do 3.

Next, the PZT film 64 and the Ir / IrO ₂ upper electrode 63 are patterned to remove unnecessary portions. The specific processing is as follows. That is, a resist having a desired pattern is formed by applying a resist and exposing and developing the resist. Thereafter, the PZT film 64 and the Ir / IrO ₂ upper electrode 63 are etched through this mask. Here, this etching is performed with argon,
It is performed by reactive ion etching using an etching gas composed of chlorine and oxygen. By the above processing, the PZT film 64 and the Ir / IrO ₂ upper electrode 63 become
It is patterned into a desired shape. Next, an SiON film 77 is formed so as to cover the entire upper surface.
(D), (d ')). Thus, the ferroelectric capacitor of the third embodiment is completed.

Next, referring to FIG. 17, the third embodiment will be described.
Of application of ferroelectric capacitors to actual circuit devices
I will tell. Here, this ferroelectric capacitor (FIGS. 14, 15,
16) is applied to a memory having a 1T1C structure (FIG. 28).
Will be described. This ferroelectric capacitor is shown in FIG.
Used as a ferroelectric capacitor 174 in the semiconductor device. Contact with each part
The continuation is performed as follows. That is, the first platinum lower electrode
The second platinum lower electrode 62 is connected to the terminal T1 of FIG.
To the terminal T2. Ir / IrO ₂Upper electrode 63
Is in a floating state.

In this case, as shown in FIG. 17, between the first platinum lower electrode 61 and the second platinum lower electrode 62,
An electric field is first formed through the Ir / IrO ₂ upper electrode 63 and then to the other party. And a region between the first platinum lower electrode 61 and the Ir / IrO ₂ upper electrode 63;
Second platinum lower electrode 62 and Ir / IrO ₂ upper electrode 63
The direction of the formed electric field (that is, the direction in which the ferroelectric 64 is polarized) is opposite to the direction between the two.
As a result, mutually polarized portions are formed in the ferroelectric material, so that the polarization state is stabilized. It should be noted that the stabilization of the polarization state in the case where the regions polarized in the opposite directions are alternately arranged adjacent (or close to each other) will be described in detail in the first embodiment with reference to FIG. As described above.

In addition, in the example described with reference to FIGS. 15 and 16, since the first platinum lower electrode 61 and the second platinum lower electrode 62 are in contact with the second plug 76, The lower wiring and the ferroelectric capacitor are electrically connected. This structure has an advantage that it is not necessary to perform a wiring process after the capacitance forming process.

Fourth Embodiment FIG. 18 shows an outline of a ferroelectric capacitor according to a fourth embodiment of the present invention. FIG. 18A is a schematic plan view and FIG. (B) is a schematic cross-sectional view taken along the line AA of (a) of FIG. 19, and FIG. 19 is a view showing a process of forming a ferroelectric capacitor according to the fourth embodiment. ) And (b) are schematic cross-sectional views in a main step, FIG. (B ′) is a schematic plan view in a main step, and FIG. 20 is a ferroelectric substance according to a fourth embodiment. FIG. 3C is a view showing a step of forming a capacitor, and FIGS.
(D) is a schematic cross-sectional view of the main process, and FIG.
FIG. 3 is a schematic plan view in a main step.

The ferroelectric capacitor of the fourth embodiment is shown in FIG.
8 (a) and 8 (b), a platinum lower electrode 81,
Platinum upper electrode 82 and SrBi ₂ Ta ₂ which is a ferroelectric substance
An O ₉ (hereinafter, also simply referred to as SBT) film 83 is provided.

The platinum lower electrode 81 is disposed so as to extend over the entire lower surface of the SBT film 83 in the figure. On the other hand, the platinum upper electrode 82 is arranged on the upper side surface of the SBT film 83 in the figure. The shape of the platinum upper electrode 82 is shown in FIG.
As can be seen from (b), slits are formed at various points, and the slits are formed as a whole. Platinum upper electrode 82
And the platinum lower electrode 81 are configured as a pair,
When a voltage is applied between both electrodes, the applied voltage polarizes the region of the SBT film 83 located between both electrodes.

The SBT film 83 is configured to have a different thickness depending on its location. That is, the platinum upper electrode 82
The area (slit) between the teeth of the comb is thinner than the area immediately below the teeth. Specifically, the thickness is set to ／ of the thickness immediately below the teeth of the comb.

In FIGS. 18A and 18B, only the portion constituting the ferroelectric capacitor is drawn and drawn. However, such a ferroelectric capacitor is actually placed on the substrate. ,
It is formed together with a protective film for insulation, wiring, and the like.

Next, with reference to FIGS. 19 and 20, a description will be given of a procedure for forming a ferroelectric capacitor according to the fourth embodiment. First, a silicon oxide film 85 is formed on the surface of the silicon substrate 84.
To form Next, a platinum lower electrode 81 is formed on the silicon oxide film 85. Specifically, first, titanium (not shown) for electrode adhesion is formed on the entire upper surface to a thickness of 30 nm by a sputtering method. Then, a platinum lower electrode 81 is formed thereon by depositing platinum to a thickness of 200 nm by sputtering.

Next, an SBT film 83 is formed on the entire upper surface of the platinum lower electrode 81. Specifically, an SBT sol-gel solution is applied to the entire surface and baked at 800 ° C. in oxygen to form an SBT film 83.

Next, a platinum upper electrode 82 is formed on the SBT film 83, and a part of the SBT film 83 is removed. Specifically, first, platinum is deposited to a thickness of 200 nm on the entire surface of the SBT film 83 by sputtering (FIG. 19A). A resist is applied on the platinum film (82), and is exposed and developed to form a mask having a desired pattern. And through this mask,
The platinum upper electrode 82 is completed by etching the platinum film. Thereafter, the etching is further continued, so that a portion of the SBT film 83 where the platinum upper electrode 82 is not provided is provided.
For a predetermined thickness (here, 1/4 or more of the original thickness)
(FIG. 19 (b), (b ')).

Next, the SBT film 83 and the platinum lower electrode 81
Is patterned to remove unnecessary portions thereof (FIG. 20).
(C), (c ′)). The specific processing is as follows. That is, a resist having a desired pattern is formed by applying a resist and exposing and developing the resist. After this,
Through this mask, the SBT film 83 and the platinum lower electrode 8 are formed.
1 and a titanium layer (not shown) for electrode adhesion are etched. Here, this etching is performed by reactive ion etching using an etching gas composed of argon, chlorine and oxygen. By the above processing, SB
The T film 83 and the platinum lower electrode 81 are formed as shown in FIG.
Patterning is performed as shown in FIG.

Next, a silicon oxide film 86 is formed so as to cover the entire upper surface. Next, a contact hole for wiring connection is formed. This contact hole is formed by etching the silicon oxide film 86 and the SBT film 83. Naturally, by forming a mask by applying resist, exposing and developing before etching,
Only desired portions are etched away. In the portion where the contact hole is formed as described above, the platinum upper electrode 82
Alternatively, the platinum lower electrode 81 is exposed. After the contact holes are formed, 800 to recover the deterioration of the SBT film 83 due to the various processes performed so far.
Heat treatment is performed at about ° C.

Next, a wiring is formed (FIG. 20D).
Here, a wiring layer having a stacked structure of a titanium nitride (TiN) layer 87 and an aluminum (Al) layer 88 is formed by a sputtering method. Then, the wiring is completed by patterning the wiring layer. Each wiring is also formed in the previously formed contact hole, where it is connected to the platinum lower electrode 81 or the platinum upper electrode 82 (FIG. 20 (d)). Thus, the ferroelectric capacitor of the fourth embodiment is completed.

In the ferroelectric capacitor of this embodiment, in the gap (slit) between the teeth of the comb, the SBT film 83 is partially removed to make it thinner. This portion functions as a relaxation region because the electric field forcing the polarization is very small as compared with the case where the SBT film 83 is not thinned. Therefore, there is little repulsion between the polarization state occurring in the region corresponding to a certain tooth and the polarization state occurring in the region corresponding to the adjacent tooth. As a result, it is possible to reduce the deterioration of the polarization amount due to the repulsion of the polarization. In addition, about the effect | action of a relaxation area | region, in 1st Embodiment,
This is as described in detail with reference to FIG.

Fifth Embodiment FIG. 21 shows an outline of a ferroelectric capacitor according to a fifth embodiment of the present invention. FIG. 21A is a schematic plan view, and FIG. ) Is a schematic cross-sectional view along the line AA in FIG. 2A, FIG. 2C is a schematic cross-sectional view along the line BB in FIG. 2A, and FIG. FIGS. 7A and 7B are diagrams showing a process of forming a dielectric capacitor, in which FIGS. 7A and 7B are schematic cross-sectional views in a main process, and FIGS. FIGS. 23A and 23B are schematic plan views and FIGS. 23A and 23B are views showing a ferroelectric capacitor forming process of the embodiment, and FIGS.
Is a schematic cross-sectional view in a main process, and FIG. (C ′) is a schematic plan view in a main process.

The ferroelectric capacitor of the fifth embodiment is shown in FIG.
As shown in FIGS. 1 (a) to 1 (c), it is configured to include an Ir / IrO ₂ lower electrode 91, an Ir / IrO ₂ upper electrode 92, and a PLZT film 93 that is a ferroelectric.

Ir / IrO ₂ lower electrode 91 and Ir / Ir
The O ₂ upper electrode 92 is configured as a pair. I
The r / IrO ₂ lower electrode 91 is embedded in the lower surface of the PLZT film 93. On the other hand, Ir / IrO ₂ upper electrode 92
Are arranged on the upper side surface of the PLZT film 93 in the figure.

Ir / IrO ₂ lower electrode 91 and Ir / I
The rO ₂ upper electrode 92 has slits formed at various places, and both have a comb shape as a whole. The dimensions of each part, particularly the width and length of the portion corresponding to the teeth of the comb, and the width of the gap (slit) between the teeth are the same. The Ir / IrO ₂ upper electrode 92 and the Ir / IrO ₂ lower electrode 91 are arranged in the same position and in the direction of the “teeth” of the comb, and when viewed from the top in the figure, these teeth just overlap each other. It is visible (Fig. 21
(See (a)). However, the directions are exactly 1
It is turned upside down by 80 degrees. That is, two combs are arranged with their teeth facing each other.

Ir / IrO ₂ lower electrode 91 and Ir / I
Each of the rO ₂ upper electrodes 92 is formed of a laminated structure of iridium oxide and iridium. In addition,
In FIGS. 21 (a) to 21 (c), only the portion constituting the ferroelectric capacitor is drawn and drawn. However, in actuality, such a ferroelectric capacitor is provided on the substrate by an insulating protection capacitor. It is formed together with a film, wiring and the like.

Next, with reference to FIGS. 22 and 23, a description will be given of a procedure for forming a ferroelectric capacitor according to the fifth embodiment. First, a silicon oxide film 95 is formed on a silicon substrate 94. Next, on this silicon oxide film 59, Ir
/ IrO ₂ lower electrode 91 is formed (FIG. 22A,
(A ')). The Ir / IrO ₂ lower electrode 91 is specifically formed as follows. That is, first,
On the silicon oxide film 95, iridium oxide and iridium are formed in a thickness of 100 nm by a sputtering method.
Subsequently, this film is patterned into the shape shown in FIG. This patterning is performed by applying a resist, exposing and developing, and performing reactive ion etching using an etching gas composed of argon, chlorine, and oxygen. Thus, an Ir / IrO ₂ lower electrode 91 is formed.

Next, a PLZT film 93 is formed on the entire upper surface (FIG. 22B). Specifically, a PLZT film 93 is formed by applying a sol-gel solution of PLZT and thereafter baking it in oxygen at 600 ° C. for a predetermined time.

Next, the PLZT film 93 is patterned to remove unnecessary portions thereof (FIG. 228 (b),
(B ')). The specific processing is as follows. In other words, by applying a resist and exposing and developing it,
A mask having a desired pattern is formed. Thereafter, the PLZT film 93 is etched through this mask. Here, this etching is performed by reactive ion etching using an etching gas composed of argon, chlorine and oxygen. By the above processing, the PLZT film 93 becomes
Patterning is performed as shown in FIGS.

Next, on the PLZT film 93 or the like, Ir /
An IrO ₂ upper electrode 92 is formed (FIG. 23C,
(C ')). The Ir / IrO ₂ upper electrode 92 is specifically formed as follows. That is, first,
Iridium oxide and iridium are each formed to a thickness of 100 nm on the entire upper side by a sputtering method. Subsequently, this film is patterned into the shape shown in FIGS. This patterning is performed by applying a resist, exposing and developing, and performing reactive ion etching using an etching gas composed of argon, chlorine, and oxygen.
Thus, an Ir / IrO ₂ upper electrode 92 is formed.

Next, silicon is covered so as to cover the entire upper side.
An oxide film 96 is formed. Next, contact for wiring connection
Form a hole. This contact hole is made of silicon
By etching the oxide film 96 and the PLZT film 93
Form. Of course, prior to etching,
By forming a mask with cloth, exposure and development,
Only desired portions are etched away. Like this
In the portion where the contact hole is formed, Ir / IrO₂under
Part electrode 91 or Ir / IrO ₂Upper electrode 92 is exposed
It will be in the state of having done. After forming the contact hole,
The deterioration of the PLZT film 93 due to the various processes performed up to
In order to recover, a heat treatment is performed at about 400 ° C.

Next, a wiring is formed (FIG. 23D).
Here, titanium nitride / tungsten is formed by using a sputtering method.
Tensilicide (TiN / WSi) layer 97 and aluminum layer 9
8 is formed. And this
Wiring is completed by patterning this wiring layer.
To achieve. Each wiring is placed in the previously formed contact hole.
Are also formed, where Ir / IrO₂Lower electrode 91
Or Ir / IrO ₂Connected to upper electrode 92
You. Thus, the ferroelectric capacitor of the fifth embodiment
Is completed.

In the ferroelectric capacitor of this embodiment, Ir / I
rO₂Lower electrode 91 and Ir / IrO ₂With the upper electrode 92
When voltage is applied between them, it is sandwiched by the teeth of the comb
In the portion, the PLZT film 93 is polarized. But for the comb
The PLZT film 9 is located just below the tooth gap (slit).
No polarization occurs in 3. Therefore, such a polarization
The part that does not function as a relaxation region,
Stabilize. Note that the effect of the relaxation region is described in the first practical example.
The embodiment has been described in detail with reference to FIG.
It is a cage.

Sixth Embodiment FIG. 24 shows an outline of a ferroelectric capacitor according to a sixth embodiment of the present invention. FIG. 24A is a schematic plan view and FIG. FIG. 24B is a schematic cross-sectional view taken along line AA of FIG. 24A, FIG. 24C is a schematic cross-sectional view taken along line BB, and FIG. 3A to 3C are schematic cross-sectional views showing main steps, and FIGS. 3A to 3C are schematic cross-sectional views showing main steps. FIG. 26 is a diagram showing a step of forming a ferroelectric capacitor of the embodiment, and FIGS. 26 (d) and (e) are schematic cross-sectional views showing main steps. d ′) is a schematic plan view of the main process.

The ferroelectric capacitance of the sixth embodiment is
As shown in FIGS. 24 (a), (b) and (c), the lower part of platinum
An electrode 101, a first platinum upper electrode 102, and a second white
A gold upper electrode 103 and a PZT film 104 which is a ferroelectric substance
And ferroelectric PbTiO ₃(Below, simply, PT
) Film 105.

A platinum lower electrode 101, a first platinum upper electrode 102, and a third platinum upper electrode 103
The ZT film 104 or the PT film 105 is disposed so as to overlap with the ZT film 104 or the PT film 105 therebetween. Platinum lower electrode 1
Reference numeral 01 denotes a plate-like shape, which is embedded in the lower surface of the PZT film 104 in the figure. First platinum upper electrode 1
As can be seen from FIGS. 24 (a), (b), and (c), No. 02 has slits formed at various points, and is formed in a comb shape as a whole. This first platinum upper electrode 102 is
At the bonding surface position between the ZT film 104 and the PT film 105,
It is embedded in the PT film 105 side. The second platinum upper electrode 103 has a plate shape, and is provided on the upper side surface of the PT film 105 in a state facing the first platinum upper electrode 102 in the drawing.

Both the PZT film 104 and the PT film 105 have ferroelectricity. As described above, since the first platinum upper electrode 102 is formed in a comb shape, both films are integrated with each other through the gap (slit) between the teeth of the comb of the first platinum upper electrode 102. Are connected.

Note that FIGS. 24 (a), (b) and (c)
In FIG. 1, only the portion constituting the ferroelectric capacitor is drawn and drawn. However, in practice, such a ferroelectric capacitor is formed on a substrate together with a protective film for insulation, wiring, and the like.

Next, with reference to FIG. 25 and FIG. 26, a procedure for forming the ferroelectric capacitor of the sixth embodiment will be described. First, a silicon oxide film 107 is formed on the surface of a silicon substrate 106. Next, this silicon oxide film 107
A platinum lower electrode 101 is formed thereon (FIG. 25A,
(A ')). The platinum lower electrode 101 is specifically formed as follows. That is, first, a 30 nm-thick titanium film is formed on the silicon oxide film 107 by a sputtering method. The titanium film formed here is
It becomes an adhesion layer of the platinum lower electrode. Further, platinum is deposited to a thickness of 200 nm on the titanium film by a sputtering method. Subsequently, the platinum film and the titanium film are formed as shown in FIG.
It is patterned into the shape shown in FIG. This patterning is performed by applying a resist to a platinum film, exposing and developing, and then performing reactive ion etching using an etching gas composed of argon, chlorine, and oxygen. Thus, the platinum lower electrode 101 is formed.

Next, a PZT film 104 is formed so as to cover the entire silicon oxide film 107 and the platinum lower electrode 101. Specifically, PZ is applied over the entire surface by using a sputtering method.
A PZT film 104 is formed by forming T and sintering it in oxygen at 600 ° C. for 30 minutes.

Next, a first platinum upper electrode 102 is formed on the PZT film 104 (FIG. 25B,
(B ')). Specifically, first, platinum is formed to a predetermined thickness on the entire surface of the PZT film 104 by a sputtering method. Then, this platinum film is patterned in the same manner as in the case of forming the platinum lower electrode 101, so that the first film is formed.
Is completed.

Next, a PT film 105 is formed so as to entirely cover the PZT film 104 and the first platinum upper electrode 102. Specifically, the PT film 105 is formed by forming a PT film using a sputtering method and baking it at 600 ° C. for 30 minutes in oxygen.

Next, a second platinum upper electrode 103 is formed on the PT film 105 (FIG. 25C). Specifically, first, platinum is formed to a predetermined thickness on the entire surface of the PT film 105 by a sputtering method. Then, this platinum film is patterned in the same manner as in the case of forming the platinum lower electrode 101, so that the second platinum upper electrode 10 is formed.
3 is completed.

Subsequently, the PZT film 104 and the PT film 105
Is patterned to remove unnecessary portions thereof. Specifically, it is performed as follows. First, on the PT film 105 and the like,
A resist is applied, exposed and developed to form a mask covering only necessary portions. Then, reactive ion etching is performed through this mask. A gas composed of argon, chlorine and oxygen was used as an etching gas. Through the above processing, the PZT film 104 and the PT film 105 can be patterned into the state shown in FIGS.

Next, a silicon oxide film 108 is formed so as to cover the entire upper surface (FIG. 26D,
(D ')). Next, a contact hole for wiring connection is formed. This contact hole is formed in the silicon oxide film 10
8, formed by etching the PZT film 104 and the PT film 105. Naturally, by forming a mask by applying, exposing, and developing a resist prior to etching, only a desired portion is removed by etching. In the portion where the contact hole is formed, the first platinum upper electrode 102, the second platinum upper electrode 103 or the platinum lower electrode 101 is exposed. After forming the contact hole, P
In order to recover the deterioration of the ZT film 104 and the PT film 105, a heat treatment is performed at about 500 ° C.

Next, a wiring is formed (FIG. 26E).
Here, a tungsten silicide (WSi) layer 109 to be a wiring layer is formed by a sputtering method. The wiring is completed by patterning the tungsten silicide layer 109. Each wiring is also formed in the previously formed contact hole, where it is connected to the platinum lower electrode 101, the first platinum upper electrode 102, or the second platinum upper electrode 103. Thus, the ferroelectric capacitor of the sixth embodiment is completed.

Next, an example in which the ferroelectric capacitor according to the sixth embodiment is applied to an actual circuit device will be described. Here, this ferroelectric capacitor (FIGS. 24, 25, and 26) is referred to as 1T
A case where the present invention is applied to a memory having a 1C structure (FIG. 28) will be described. This ferroelectric capacitor is used as the ferroelectric capacitor 174 in FIG. That is, the first platinum upper electrode 102 is connected to the terminal T1 in FIG. 28, and the platinum lower electrode 101 is connected to the terminal T2. The second platinum upper electrode 103 is connected to the terminal T2. In this case, the first platinum upper electrode 102
In the region between the electrode and the platinum lower electrode 101, P
The ZT film 104 is polarized. In a region sandwiched between the first platinum upper electrode 102 and the second platinum upper electrode 103, the PT film 105 is polarized. However, the directions of the polarization are opposite to each other.

Since the first platinum upper electrode 102 is comb-shaped, the platinum lower electrode 101 and the second platinum upper electrode 10 are formed in the gaps (slits) between the teeth of the comb.
3 are sandwiched. But the second
Since the platinum upper electrode 103 and the platinum lower electrode 101 have the same potential, the PZT film 104 and the PT film 1
05 is not polarized. Since the unpolarized portion functions as a relaxation region, the polarization state is stabilized. The operation of the relaxation region is as described in detail in the first embodiment with reference to FIG.

Although the embodiments and examples of the present invention have been described in detail with reference to the drawings, the specific configuration is not limited to these embodiments and examples, and does not depart from the gist of the present invention. Even if there is a change in design, the invention is included in the present invention. For example, in the first embodiment, in the height direction of two electrode pairs (FIGS. 1B and 1C and FIG.
(A), (b) in the vertical direction, FIG. 1 (d), (e)
In the right-left direction). However, the positions in the height direction of both electrode pairs need not necessarily be shifted. They may match as in the example shown in FIGS. 27 (a) and 27 (b).

In the first embodiment, the width of each electrode constituting the two electrode pairs is the same. However, as in the example shown in FIGS. 27A and 27B, the width of the first electrode pair may be different from that of the second electrode pair. As described above, the effect in the method of use B of the first embodiment differs depending on the size of the relaxation region. Therefore, if the widths of the electrodes are different between the first electrode pair and the second electrode pair, it is determined which electrode pair is to be applied with a voltage (that is, the region in which the electrode pair is provided). Depending on whether it is used as a relaxation region), the magnitude of the polarization capacity and the effect of suppressing the decrease in the polarization amount differ. Which electrode pair is to be applied with a voltage is determined in consideration of the required magnitude of the polarization capacity and the magnitude of the effect of suppressing the decrease in the amount of polarization. For example, if a very large polarization capacity is not required, but a reduction in the amount of polarization is to be minimized,
A voltage is applied to an electrode pair composed of a narrow electrode, and the wide electrode (the region where the electrode is provided) is used as a part of the relaxation region. Conversely, a decrease in the polarization amount may occur to some extent, but when a large polarization capacity is required, a voltage is applied to an electrode pair composed of a wide electrode and a narrow electrode is provided. Area) is used as a part of the relaxation area. That way,
One capacity can be used properly according to the required specifications when actually used.

In the third embodiment and the fourth embodiment,
The part between the teeth (electrode part) of the comb-shaped electrode (teeth) (slit)
The thickness of the ferroelectric material in was set to 3/4 or less of the portion immediately below the teeth. However, the specific numerical value is not limited to this, and a certain effect can be expected as long as it is slightly thinner than the portion immediately below the tooth.

In the first embodiment, the upper electrodes 32, 34,
Each of the lower electrodes 31 and 33 was constituted by one. However, it is not always necessary to cover a region having the same potential with one electrode. A plurality of electrodes that are kept at the same potential may be formed, and these may be connected by wiring. The same applies to other embodiments. In the first embodiment, a silicon substrate is used as a substrate. However, a semiconductor substrate on which a semiconductor element such as a transistor is formed, a glass substrate, or the like can also be used.
Further, the ferroelectric does not need to be composed only of a ferroelectric. As long as the member as a whole exhibits ferroelectricity, a ferroelectric material and a paraelectric material may be laminated or arranged.

In the above description, an example of a semiconductor memory in which the life until data can no longer be determined by applying the ferroelectric capacitor of the present invention has been described. However, the application range of the ferroelectric capacitor of the present invention is not limited to this, and can be used for various circuit devices.

[0162]

As described above, according to the structure of the present invention, a ferroelectric capacitor having excellent holding characteristics and little deterioration of polarization over time and a circuit device having the same (for example, a semiconductor circuit device such as a memory) ) Can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of a ferroelectric capacitor according to a first embodiment of the present invention, wherein FIG. 1 (a) is a schematic plan view and FIG. 1 (b) is FIG. (C) is a schematic cross-sectional view along the line A-D, and FIG.
FIG. 1D is a schematic cross-sectional view along the line CC, and FIG. 1E is a schematic cross-sectional view along the line BB.

FIGS. 2A and 2B are diagrams showing a state of polarization in the ferroelectric capacitor according to the first embodiment. FIG. 2A shows a case where regions having different polarization directions are formed alternately, and FIG. This shows a case where an area is provided.

3A and 3B are diagrams schematically showing a ferroelectric capacitor according to a second embodiment of the present invention, wherein FIG. 3A is a schematic plan view, and FIG. Is a schematic cross-sectional view along the line AA, and FIG. 3C is a schematic cross-sectional view along the line BB.

4A and 4B are diagrams showing a state of polarization in a ferroelectric capacitor according to the second embodiment. FIG. 4A shows a case where regions having different polarization directions are formed alternately, and FIG. This shows a case where an area is provided.

FIGS. 5A and 5B are diagrams showing an outline of a ferroelectric capacitor according to a third embodiment of the present invention, wherein FIG. 5A is a schematic plan view, and FIG. FIG. 2 is a schematic cross-sectional view taken along line AA of FIG.

FIG. 6 is a diagram showing an outline of a ferroelectric capacitor according to a fourth embodiment of the present invention, wherein FIG. 6A is a schematic plan view, and FIG. Is a schematic cross-sectional view along the line AA, and FIG. 3C is a schematic cross-sectional view along the line BB.

FIGS. 7A and 7B show the structure of the ferroelectric capacitor according to the first embodiment of the present invention. FIG. 7A is a schematic plan view, and FIG. FIG. 1C is a schematic cross-sectional view along the line A, FIG. 2C is a schematic cross-sectional view along the DD line,
FIG. 1D is a schematic cross-sectional view along the line CC, and FIG. 1E is a schematic cross-sectional view along the line BB.

FIGS. 8A to 8C are diagrams showing a process of forming a ferroelectric capacitor according to the first embodiment. FIGS. 8A to 8C are schematic cross-sectional views showing main processes, and FIGS. , (C ′) are schematic plan views of the main steps.

FIG. 9 is a view showing a step of forming a ferroelectric capacitor according to the first embodiment, and FIGS. 9 (d) and 9 (e) are schematic cross-sectional views showing main steps.

FIGS. 10A and 10B show a structure of a ferroelectric capacitor according to a second embodiment of the present invention. FIG. 10A is a schematic plan view, and FIG. FIG. 2 is a schematic cross-sectional view taken along line AA of FIG.

FIGS. 11A and 11B are diagrams showing a step of forming a ferroelectric capacitor according to the second embodiment, wherein FIGS. 11A and 11B are schematic cross-sectional views showing main steps, and FIG. FIG. 3 is a schematic plan view in a main step.

FIG. 12 is a view showing a step of forming a ferroelectric capacitor according to the second embodiment. FIGS. 12 (c) to 12 (e) are schematic sectional views showing main steps, and FIG. 12 (c ′). , (E ′) are schematic plan views in main steps.

FIG. 13 is a schematic sectional view showing a modification of the second embodiment of the present invention.

14A and 14B show the structure of a ferroelectric capacitor according to a third embodiment of the present invention. FIG. 14A is a schematic plan view, and FIG. FIG. 4 is a schematic cross-sectional view taken along line -A.

FIGS. 15A and 15B are diagrams showing a step of forming a ferroelectric capacitor according to the third embodiment. FIGS. 15A and 15B are schematic cross-sectional views showing main steps, and FIG. (B ′) is a schematic plan view of the main process.

FIGS. 16A and 16B are diagrams showing a step of forming a ferroelectric capacitor according to the third embodiment. FIGS. 16C and 16D are schematic cross-sectional views showing main steps, and FIG. FIG. 3 is a schematic plan view in a main step.

FIG. 17 is a schematic view showing a state of polarization of a ferroelectric capacitor according to the third embodiment.

FIGS. 18A and 18B show an outline of a ferroelectric capacitor according to a fourth embodiment of the present invention. FIG. 18A is a schematic plan view, and FIG. FIG. 2 is a schematic cross-sectional view taken along line AA of FIG.

FIGS. 19A and 19B are diagrams showing a step of forming a ferroelectric capacitor according to a fourth embodiment, wherein FIGS. 19A and 19B are schematic cross-sectional views showing main steps, and FIG. FIG. 3 is a schematic plan view in a main step.

FIG. 20 is a view showing a step of forming a ferroelectric capacitor according to the fourth embodiment. FIGS. 20 (c) and 20 (d) are schematic sectional views showing main steps, and FIG. 20 (c ′). FIG. 3 is a schematic plan view in a main step.

FIGS. 21A and 21B schematically show a ferroelectric capacitor according to a fifth embodiment of the present invention. FIG. 21A is a schematic plan view, and FIG. FIG. 2C is a schematic cross-sectional view along the line A, and FIG. 2C is a schematic cross-sectional view along the line BB.

FIGS. 22A and 22B are diagrams showing a step of forming a ferroelectric capacitor according to a fifth embodiment of the present invention. FIGS. 22A and 22B are schematic cross-sectional views showing main steps. ') And (b') are schematic plan views in main steps.

FIGS. 23 (a) and 23 (b) are diagrams showing a step of forming a ferroelectric capacitor according to a fifth embodiment of the present invention. FIGS. 23 (c) and 23 (d) are schematic cross-sectional views showing main steps. ') Is a schematic plan view of the main process.

24 (a) and 24 (b) schematically show a ferroelectric capacitor according to a sixth embodiment of the present invention. FIG. 24 (a) is a schematic plan view, and FIG. FIG. 2C is a schematic cross-sectional view along the line A, and FIG. 2C is a schematic cross-sectional view along the line BB.

FIGS. 25A to 25C are diagrams showing a process of forming a ferroelectric capacitor according to a sixth embodiment, wherein FIGS. 25A to 25C are schematic cross-sectional views showing main processes, and FIGS. (B ′) is a schematic plan view of a main step.

FIGS. 26 (a) and 26 (b) are diagrams showing a step of forming a ferroelectric capacitor according to a sixth embodiment. FIGS. 26 (d) and 26 (e) are schematic cross-sectional views showing main steps, and FIG. It is a schematic plan view in a main process.

FIGS. 27A and 27B are diagrams showing a state of polarization in a modification of the first embodiment. FIG. 27A shows a case where regions polarized in opposite directions are formed alternately, and FIG. Is provided.

FIG. 28 is a circuit diagram showing a memory element having a 1T1C structure including a ferroelectric capacitor.

FIG. 29 is a circuit diagram showing a memory element having a 2T2C structure including a ferroelectric capacitor.

FIG. 30 is a circuit diagram showing a memory element having a 1T2C structure including a ferroelectric capacitor.

FIG. 31 is a circuit diagram showing another memory element including a ferroelectric capacitor.

FIG. 32 is a diagram showing an outline of a conventional ferroelectric capacitor;
FIG. 3A is a schematic plan view, and FIG.
FIG. 2 is a schematic cross-sectional view taken along line AA of FIG.

FIG. 33 is a diagram showing an outline of a conventional ferroelectric capacitor having another structure. FIG. 33 (a) is a schematic plan view, and FIG. 33 (b) is a diagram of FIG. It is a typical sectional view which follows an AA line.

34 (a) is a schematic plan view, and FIG. 34 (b) is a view taken along line AA of FIG. 34 (a). FIG. 3C is a schematic cross-sectional view along the line BB.

[Explanation of symbols]

Reference Signs List 1 ferroelectric capacitor 2 first lower electrode (part of polarization means, part of first electrode pair) 3 first upper electrode (part of polarization means, part of first electrode pair) 4 Second lower electrode (part of polarization means, part of second electrode pair) 5 Second upper electrode (part of polarization means, part of second electrode pair) 6 Ferroelectric (capacitance member) 10) Ferroelectric capacitor 11 First electrode (part of polarization means, intermediate electrode) 12 Second electrode (part of polarization means, second electrode) 13 Third electrode (part of polarization means, 3 electrodes) 14 ferroelectric (capacitive member) 15 ferroelectric capacitor 16 lower electrode (second electrode) 17 upper electrode (first electrode) 18 ferroelectric (capacitor) 20 ferroelectric capacitor 21 Lower electrode 22 Upper electrode 23 Ferroelectric 31 First platinum lower electrode (part of polarization means, part of first electrode pair) 32 First Platinum upper electrode (part of polarization means, part of first electrode pair) 33 Second platinum lower electrode (part of polarization means, part of second electrode pair) 34 Second platinum upper electrode (part of second electrode pair) 35 PZT film (capacitance member) 41 Ir / IrO ₂ lower electrode 42 First platinum upper electrode 43 Second platinum upper electrode 44 PLZT film 61 First Platinum lower electrode (part of polarization means, first counter electrode) 62 Second platinum lower electrode (part of polarization means, second counter electrode) 63 Ir / IrO ₂ upper electrode (part of polarization means, Common electrode) 64 PZT film (capacitance member) 81 Platinum lower electrode (second electrode) 82 Platinum upper electrode (first electrode) 83 SBT film (capacity member) 91 Ir / IrO ₂ Lower electrode 92 Ir / IrO ₂ the upper electrode 93 PLZT film 101 platinum under Electrode (part of polarization means, first electrode) 102 First platinum upper electrode (part of polarization means, intermediate electrode) 103 Second platinum upper electrode (part of polarization means, second electrode) 104 PZT film (Part of capacitance member) 105 PT film (Part of capacitance member) 173 MISFET (Part of polarization means, Part of voltage application means) 174 Ferroelectric capacitance 175 Differential sense amplifier 176 Bit line control MISFET (Polarization Part of the means,
177 First MISFET (part of polarization means, part of voltage application means) 178 Second MISFET (part of polarization means, part of voltage application means) 179 First strength Dielectric capacitance 180 Second ferroelectric capacitance 181 MISFET for sensing r Adjacent portion h spacing

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8247 29/788 29/792 F term (Reference) 5B024 AA15 BA02 CA21 CA27 5F001 AA17 AD12 5F083 AD21 AD49 AD54 FR01 FR03 GA21 JA15 JA17 JA35 JA36 JA38 JA39 JA40 JA43 LA01 MA06 MA17 MA18 MA20 PR21 PR22 PR23 PR33

Claims (8)

[Claims] 1. A capacitance member made of a ferroelectric material, and a part of the capacitance member is polarized in a predetermined direction, and another region adjacent to the polarized region is polarized in the opposite direction. A circuit device having a ferroelectric capacitor, characterized by comprising a polarization means for causing a polarization. 2. The device according to claim 1, wherein at least a part of the region polarized in the predetermined direction and the other region polarized in the opposite direction are alternately arranged. A circuit device comprising the ferroelectric capacitor according to any one of the preceding claims. 3. A first electrode pair consisting of a plurality of electrodes arranged opposite to each other, a second electrode pair consisting of a plurality of electrodes arranged opposite each other, and the first electrode pair. And a capacitor member made of a ferroelectric material, which is arranged integrally and continuously from the electrodes facing each other constituting the second electrode pair to the electrodes facing each other constituting the second electrode pair. Characteristic ferroelectric capacitor. 4. A voltage is applied to the ferroelectric capacitor according to claim 3, and a first electrode pair provided in the ferroelectric capacitor, and the first electrode pair is applied to the second electrode pair. And a voltage applying means for applying a voltage generating an electric field in the opposite direction. 5. An intermediate electrode, a first electrode part of which is arranged to face the intermediate electrode, and a part of which faces the intermediate electrode on a side opposite to the first electrode, At least a part of a portion not facing the intermediate electrode is disposed so as to face the first electrode, and a second electrode is integrally connected between the first electrode, the intermediate electrode, and the second electrode. A ferroelectric capacitor comprising: a ferroelectric capacitor member. 6. A ferroelectric capacitor according to claim 5, further comprising voltage applying means for applying a voltage between a first electrode and an intermediate electrode of the ferroelectric capacitor. Circuit device provided with a ferroelectric capacitor. 7. A common electrode, a first counter electrode disposed to face the common electrode, and a counter electrode to the common electrode on the same side as the first counter electrode, and the first counter electrode The second arranged alongside
And a capacitance member made of a ferroelectric material, which is arranged integrally and continuously from between the first counter electrode and the common electrode to between the second counter electrode and the common electrode. A ferroelectric capacitor comprising: 8. A voltage is applied between the ferroelectric capacitor according to claim 7 and a first counter electrode and a second counter electrode included in the ferroelectric capacitor, so as to pass through the common electrode. Forming an electric field connecting the first counter electrode and the second counter electrode, and forming an electric field between the common electrode and the first counter electrode; and forming an electric field between the common electrode and the second counter electrode. A voltage application means for polarizing a region sandwiched between the ferroelectric capacitor and the electrode in a direction opposite to each other.