JP2000322281A - Emulation probe board and debugging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an emulation probe board in an on-chip debugging system and a debugging system which eliminate a need of mounting an emulation memory on a target system. SOLUTION: A probe 20 connected to a receptacle 52 of a target system 50, an interface 24 which communicates debugging information with an ICE main body in serial, a microcomputer 22, and an emulation memory 30 are provided. The board is separated into a probe-side board and a memory-size board, and connector terminals of the memory-side board are standardized. The emulation memory for internal ROM is mounted on the probe-side board and is packaged on both sides in a sandwich structure. A second signal required for the emulation memory is separated from a first signal from the microcomputer and is transmitted to the memory-side board. An FPGA which can be operated by the second signal is mounted on the memory-side board, and an interface between the FPGA and the ICE main body as well as the target system is provided. A memory read signal of the emulation memory for internal memory is made active at an early timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation probe board (substrate) for supporting development of a target system, and a debugging system using the same.

[0002]

2. Description of the Related Art In recent years, there has been developed a microcomputer which can be incorporated in electronic equipment such as a game device for home use, a car navigation system, a printer, a portable information terminal, a portable telephone, etc., and which can realize advanced information processing. Demand is growing. Such a built-in microcomputer is usually mounted on a user board called a target system. In order to support the development of this target system, I
A development support tool called CE (In-Circuit Emulator) is widely used.

[0003] Conventionally, such ICE has been
I called a CPU replacement type as shown in FIG.
CE was dominant.

In this CPU replacement type ICE, the microcomputer 302 is removed from the socket of the target system 300 at the time of evaluation (debugging). Next, a probe 306 provided at the tip of a flat cable 308 extending from the ICE body (debug tool) 304 is connected to the socket. And this ICE body 30
4 emulates the operation of the detached microcomputer 302. Also, this ICE body 304
Various processes required for debugging are performed.

However, this CPU replacement type IC
In E, due to the existence of the flat cable 308, etc.,
There is a disadvantage that emulation at a high clock frequency is difficult (for example, about 33 MHZ is a limit). For this reason, the system operating environment (signal timing) differs between an evaluation in which the probe 306 is connected to the target system 300 to perform emulation and a product in which the microcomputer 302 is mounted on the target system 300 and operated (actual operation). , Load conditions). Therefore, the target system 30 that was operating at the time of evaluation was
However, a problem arises in that 0 does not operate at the time of a product.

Further, this CPU replacement type ICE has a problem that if the microcomputer 302 is different, even if it is a derivative, the ICE body 304 must be newly designed.

On the other hand, such a CPU replacement type ICE
In recent years, an ICE called an on-chip debug type has been spotlighted as a solution to the above disadvantage.

In the on-chip debug type ICE, an on-chip debug circuit 318 is built in a microcomputer 314 as shown in FIG. And
Using this on-chip debug circuit 318, debug information (CPU status information, program counter information, etc.) is serially communicated with the ICE main body 324 at high speed.

According to the on-chip debug type ICE, evaluation (debugging) of the target system 312 can be performed with the microcomputer 314 mounted on the target system 312. Therefore, it is possible to make the operating environment of the target system 312 the same at the time of evaluation and at the time of product, and it is possible to eliminate the drawback of the CPU replacement ICE.

However, it has been found that the conventional on-chip debug type ICE has the following problems regarding the emulation memory 320.

The emulation memory 320 is a memory necessary for evaluation (program debugging) of the target system 312 as a substitute memory for the internal ROM 316 and the external ROM 322 from which programs cannot be downloaded as appropriate. That is, at the time of evaluation, the user
Emulation memory 320 composed of M, etc.
Then, the program is developed while downloading the program under development as needed. When the program is completed, the completed program and data used for the program are stored in the internal ROM 316 or the external ROM 322 including a mask ROM or the like. Thus, the target system 312 for the product is completed.

Therefore, the emulation memory 320
Is necessary at the time of evaluation of the target system 312, but at the time of product, the internal ROM 316 and the external ROM 322 are required.
, The emulation memory 320 is not required.

However, as shown in FIG. 1B, in the conventional on-chip debug type ICE, the emulation memory 320 is mounted on the target system 312 instead of the ICE main body 324. On-chip debug type IC
In E, the target system 312 and the ICE body 324
This is because serial communication is not possible between the ICE main unit 324 and the ICE main unit 324 because the serial communication cannot be used to communicate the address and data of the emulation memory.

When the emulation memory 320 is mounted on the target system 312, the following problems occur. (1) It is necessary for the user to mount the emulation memory in the target system, design a control circuit for the emulation memory, and the like, thereby increasing the user's labor. This causes a problem such as a prolonged development period of the target system. In particular, when the debugging method is changed and the access method to the emulation memory is changed, the wiring pattern of the target system must be changed, which further increases the burden on the user. (2) A target system for a product must be equipped with an emulation memory that should not be necessary, which leads to an increase in cost of the target system. (3) In order to avoid the problem (2), a user designs a target system for a product without an emulation memory, separately from an evaluation target system with an emulation memory. There is a need. However, this causes problems such as a longer development period of the target system and an increase in product cost. In addition, since the target system for evaluation and the target system for product are designed separately, the target system for product does not operate normally even though the target system for evaluation operates normally. And other problems also occur.

The present invention has been made in view of the above technical problems, and it is an object of the present invention to provide an on-chip debugging system and eliminate the need to mount an emulation memory in a target system. Another object of the present invention is to provide an emulation probe board capable of improving user convenience and a debugging system using the same.

[0016]

According to the present invention, there is provided an emulation probe board for supporting development of a target system in which a microcomputer having an on-chip debug circuit is incorporated.
A probe for connecting to the first mounting means of the target system, which is mounting means for mounting the microcomputer, a second mounting means for mounting the microcomputer, and the second mounting means A first interface for serially communicating debug information for the on-chip debug circuit between the microcomputer mounted on the microcomputer and an external device, and an emulation for emulating a memory used in the target system And third mounting means for mounting the memory.

According to the present invention, at the time of evaluation (debugging) of the target system or the like, the probe is connected to the first mounting means (for example, a socket) of the target system. Thus, the target system can be operated using the microcomputer mounted on the emulation probe board. And
At this time, debug information used for the on-chip debug circuit built in the microcomputer is serially communicated with the outside (for example, the ICE main unit or the host system) using the first interface. Therefore, the evaluation (debugging) work by the on-chip debugging method can be performed in a state where it can be considered that the microcomputer is substantially mounted on the target system.

According to the present invention, the emulation memory is mounted on the emulation probe board,
Eliminating emulation memory in the target system becomes unnecessary. Therefore, the burden on the user can be reduced, and the need to prepare a target system for evaluation separately from the target system for products can be eliminated. As a result, the development period of the target system can be shortened, cost can be reduced, and reliability can be improved.

According to the present invention, there is provided a probe-side board provided with at least the probe, the second mounting means for mounting the microcomputer, a first connector, and the emulation memory. The third mounting means and a memory-side board provided with at least one at least a second connector connected to the first connector are separated from each other. By doing so, even when the model of the microcomputer is changed, only the probe-side board can be changed and the same board can be used as the memory-side board. The first interface for communicating debug information is desirably provided on a probe-side board on which a microcomputer is mounted in order to realize high-speed communication.

Further, the present invention is characterized in that the form of the terminals of the probe on the probe-side board is customizable and the form of the terminals of the second connector on the memory-side board is standardized. . In this way, even if the model of the microcomputer is changed and the form of the probe terminals (number of terminals, terminal arrangement, signals assigned to each terminal, etc.) is changed, the same one is used as the memory side board. it can. Therefore, the development period of the emulation probe board can be shortened and the cost can be reduced.

The present invention also provides a third connector for directly connecting to the first connector of the probe-side board, and a third connector for connecting to the first connector of the probe-side board via a cable. A fourth connector is provided on the memory-side board as the second connector. In this way, the emulation probe board can be easily connected to a target system that is difficult to connect to the emulation probe board because there is no space.

Further, according to the present invention, the emulation memory includes an emulation memory for an internal memory for emulating an internal memory of the microcomputer, and an emulation memory for an external memory for emulating an external memory of the microcomputer. A fourth mounting means for mounting the emulation memory for the internal memory is provided on the probe-side board. This makes it possible to speed up access to the internal memory emulation memory by the microcomputer. Thus, for example, when an instruction (program) is stored in the internal memory emulation memory,
The microcomputer can complete the fetch and decode of the instruction within one clock cycle.
As a result, the microcomputer can be operated at the same high clock frequency as in the product, and the target system can be evaluated.

The present invention also provides a first connection line for connecting the microcomputer to the emulation memory for the internal memory and transmitting a control signal for controlling the emulation memory for the internal memory; A second connection line for connecting the connection line to the first connector and transmitting the control signal is provided, and a first disconnection unit for disconnecting the connection by the second connection line is provided. It is characterized by the following. With this configuration, the parasitic capacitance of the first connection line can be reduced, and the access speed of the microcomputer to the internal memory emulation memory can be further increased.

Further, in the present invention, the emulation memory for an internal memory includes first and second emulation memories for an internal memory, and the fifth mounting means for mounting the first emulation memory for an internal memory may include: A sixth mounting means provided on a first surface of the probe-side board for mounting the second emulation memory for an internal memory is provided on a second surface of the probe-side board. I do. With this configuration, the wiring pattern length between the microcomputer and the first internal memory emulation memory and the wiring pattern length between the microcomputer and the second internal memory emulation memory are made the same or almost the same. Becomes possible. This makes it possible to operate the internal memory emulation memory properly even during high-speed access to the internal memory emulation memory.

Further, according to the present invention, a third connection line for connecting the microcomputer and the first interface and transmitting the debug information is provided, and a connection is provided between the third connection line and the probe. A fourth connection line and second disconnection means for disconnecting the connection by the fourth connection line are provided. By doing so, the parasitic capacitance parasitic on the third connection line can be reduced,
High-speed serial communication of debug information via the first interface can be realized.

According to the present invention, a second signal including a signal necessary for the operation of the emulation memory among the first signals from the microcomputer is transmitted between the microcomputer and the emulation memory. Features. This makes it possible to standardize the form of the second signal (the number of signals, the type of signal, etc.). When the emulation probe board is separated into the probe side board and the memory side board, the second
Is transmitted between the probe board (microcomputer) and the memory board (emulation memory) via the first connector of the probe board and the second connector of the memory board.

The present invention is characterized in that a seventh mounting means is provided for mounting a custom chip operable by the second signal. In this way, the second
It is possible to operate the custom chip under the control of the microcomputer by using the signal of (1). After the evaluation of the custom chip, the user can design the ASIC microcomputer by integrating the circuit of the custom chip and the circuit of the microcomputer into one chip.

According to the present invention, at least one of a second interface serving as an interface between the custom chip and the outside and a third interface serving as an interface between the custom chip and the target system are provided. It is characterized by being. In this way, it becomes possible to download data of a circuit constituting the custom chip, operate a target system or a device mounted on the target system using input / output signals from the custom chip, etc. Convenience can be improved.

Further, in the present invention, the emulation memory includes an emulation memory for an internal memory for emulating an internal memory of the microcomputer, and an emulation memory for an external memory for emulating an external memory of the microcomputer. The second signal is transmitted between the microcomputer and the emulation memory for external memory via a given buffer, and the second signal is transmitted between the microcomputer and the emulation memory for internal memory without passing through the buffer. Is transmitted. This makes it possible to speed up access to the internal memory emulation memory by the microcomputer.

Further, in the present invention, the emulation memory includes an emulation memory for an internal memory for emulating an internal memory of the microcomputer, and an emulation memory for an external memory for emulating an external memory of the microcomputer. A second control signal separate from the first control signal for controlling the emulation memory for the external memory.
Is supplied to the emulation memory for internal memory. With this configuration, the internal memory emulation memory can be controlled by the second control signal of a different system from the first control signal for controlling the external memory emulation memory. This makes it possible to realize proper access to the internal memory emulation memory.

Also, the present invention is characterized in that the second memory read signal included in the second control signal becomes active earlier than the first memory read signal included in the first control signal. I do. This makes it possible to easily cope with such a restriction, for example, when there is a restriction that the microcomputer must fetch and decode an instruction stored in the internal memory emulation memory in one clock cycle. Become like

Further, the debugging system according to the present invention includes any one of the above-described emulation probe boards, the microcomputer mounted on the emulation probe board, the emulation memory mounted on the emulation probe board, A debug tool through which debug information is communicated via the first interface.

According to the present invention, the convenience of the user can be improved, and the development period of the target system can be shortened.
It becomes possible to provide a user with a debugging system capable of reducing costs.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

1. 2. Basic Configuration FIG. 2 shows a basic configuration of an emulation probe board (emulation POD (Probe Of Device)) of the present embodiment and an overall configuration of a debugging system using the emulation probe board.

The emulation probe board 10 is provided with a probe 20, a high-speed serial interface (I / F) 24, and a microcomputer 22 and an emulation memory 30. That is, a means for mounting the microcomputer 22 and the emulation memory 30 (a means realized by, but not limited to, a socket, a terminal (pin) hole, a wiring drawn from the terminal, or the like) is provided.

Here, the probe 20 is for connecting to the socket 52 of the target system 50.
The socket (mounting means in a broad sense) 52 is for mounting the microcomputer 22 when the target system 50 is manufactured. That is, the probe 20 of the emulation probe board 10 is connected to the socket 52 when the target system 50 is evaluated, and the microcomputer 22 is mounted on the socket 52 when the product is manufactured.

The microcomputer 22 includes a CPU and its peripheral circuits. In the present embodiment, the microcomputer 22 has a built-in on-chip debug circuit. Thus, an on-chip debug type ICE can be realized.

The emulation memory 30 emulates (replaces) an internal ROM (an internal memory in a broad sense) or an external ROM (an external memory in a broad sense) used in the target system 50. As the emulation memory 30, a high-speed RAM, a normal R
AM, flash memory, and the like can be used.

Serial interface (I / F) 24
Is an interface (high-speed serial communication interface) for high-speed serial communication of debug information for an on-chip debug circuit built in the microcomputer 22 between the microcomputer 22 and the ICE main body 54 (a debugging tool in a broad sense). It is. Such interfaces include so-called JTAG and B
A DM (Background Debug Model) standard interface may be employed, or a unique interface similar to JTAG or BDM may be employed.

As shown in FIG. 2, according to the present embodiment, unlike the conventional example of FIG. 1B, it is not necessary to mount an emulation memory in the target system. Therefore, the user does not have to take the trouble of mounting the emulation memory in the target system and designing the control circuit of the emulation memory. Further, even if the debugging method is changed, it is not necessary to change the design of the target system. In addition, there is no need to mount an emulation memory, which is originally unnecessary, on a target system for a product. Further, it is not necessary to separately design a target system for evaluation and a target system for products. Therefore, according to this embodiment, the development period of the target system can be shortened, the cost can be reduced, and the convenience for the user can be improved.

Further, according to this embodiment, the microcomputer 22 and the emulation memory 30 store
Instead of the CE main body 54, they are collectively mounted on the small-area emulation probe board 10 on which the probe 20 is provided. Therefore, the wiring pattern length between the probe 20 and the microcomputer 22, the wiring pattern length between the probe 20 and the emulation memory 30, and the wiring pattern length between the microcomputer 22 and the emulation memory 30 can be sufficiently reduced. Therefore, even if the microcomputer 22 is operated at a high clock frequency, the target system 50 operates normally without any problem. As a result, the operating environment at the time of evaluation and the operating environment at the time of a product (actual operation) can be made the same, and the reliability of the debug system 50 can be improved.

When the emulation memory 30 is used for emulating the internal ROM, the microcomputer 22 must fetch and decode the instruction from the emulation memory 30 within one clock cycle. According to the present embodiment, since the wiring pattern length between the microcomputer 22 and the emulation memory 30 can be sufficiently reduced, the microcomputer 22 can access the emulation memory 30 at high speed. Therefore, the fetch and decode of the instruction can be completed within one clock cycle, and the emulation of the internal ROM can be properly realized.

Further, according to the present embodiment, the serial interface 24 for communicating debug information is provided on the emulation probe board 10. Therefore, an efficient debugging operation can be realized by effectively using the on-chip debugging circuit built in the microcomputer 22.

That is, in the CPU replacement type ICE shown in FIG. 1A, it is not necessary to mount an emulation memory in the target system, but it is not possible to realize an efficient debugging operation using an on-chip debugging circuit.

On the other hand, in the conventional on-chip debug type ICE shown in FIG. 1B, although an efficient debug operation using an on-chip debug circuit can be realized, it is necessary to mount an emulation memory in a target system. This hinders user convenience.

On the other hand, according to the present embodiment, although an efficient debugging operation using the on-chip debugging circuit can be realized, the emulation memory need not be mounted on the target system. 1
Specific effects that cannot be realized by the combination of (A) and (B) are exhibited.

2. Separation into probe side board and memory side board As shown in FIG.
0 is desirably separable into the probe-side board 12 and the memory-side board 14.

The probe board 12 is provided with a probe 20, a microcomputer 22, a serial interface 24, and a connector 26. on the other hand,
The memory-side board 14 is provided with a connector 28 and an emulation memory 30. And connector 2
By directly connecting 6 and 28, a signal is transmitted between the probe-side board 12 and the memory-side board 14.

In FIG. 3, the emulation memory 3
0 includes an IROM emulation memory 32 (emulation memory for internal memory) and an EROM emulation memory 34 (emulation memory for external memory). The IROM emulation memory 32 is
This is a memory for emulating an internal ROM (in a broad sense, an internal memory) of the microcomputer. As such a memory, a high-speed SRAM or the like can be used. Also, the EROM emulation memory 34
Is a memory for emulating an external ROM (an external memory in a broad sense) of a microcomputer.
As such a memory, a standard speed RAM (S
RAM, DRAM), flash memory, and the like.

As shown in FIG. 3, by dividing the emulation probe board 10 into the probe side board 12 and the memory side board 14, the following advantages can be obtained.

That is, generally, the microcomputer 2
The form of the two terminals (pins) (the number of terminals, terminal arrangement, signals assigned to each terminal, etc.) is various and various. For this reason, the form of the terminal of the probe 20 also becomes various. Therefore, when the model of the microcomputer 22 used in the target system is changed, a different model of the emulation probe board must be provided accordingly.

In this case, the emulation probe board 10 is connected to the probe side board 12 and the memory side board 14.
4, the form of the terminal of the probe 20 of the probe-side board 12 can be customized and the terminal of the connector 28 (connector 26) of the memory-side board 14 can be customized as shown in FIG. The form can be standardized. For this reason, the model of the microcomputer 22 to be used is changed, and the probe 2
Even if the form of the 0 terminal changes, the same (or almost the same) memory board 14 can be used. Therefore, even if the type of the microcomputer 22 is changed, only the probe-side board 12 needs to be newly created, and the memory-side board 14 does not need to be newly created. As a result, the cost of the emulation probe board can be reduced, and the design work can be made more efficient.

3. Attaching a Flat Cable Connector Since the microcomputer and the emulation memory are mounted on the emulation probe board of the present embodiment, the board area is larger than that of a normal probe (probe board) in ICE. Therefore, depending on the type of the target system, it may be difficult to connect the emulation probe board.

Therefore, in order to solve such a problem, as shown in FIG. 5, a connector 29 for a flat cable 27 is provided on the memory-side board 14 in addition to a connector 28 for a direct connection. Is desirable. That is, the connector 29 connected to the connector 26 via the flat cable 27 is provided on the memory-side board 14.

By doing so, the emulation probe board can be easily connected even to a target system in which it is difficult to connect the emulation probe board due to lack of space or the like. Can be improved.

In this embodiment, the probe-side board 12 and the memory-side board 14 can be directly connected by using the connector 28. Therefore, it is possible to meet the demand of the user who does not want the signal delay by the flat cable 27. As described above, by using the method of FIG. 5, it is possible to meet the needs of a wide range of users.

4. Mounting of IROM emulation memory on probe-side board As described above, emulation memory includes an IROM emulation memory acting as an internal ROM,
An EROM emulation memory acting as an external ROM can be considered. For the IROM emulation memory, the fetch and decode of the instruction read from the IROM emulation memory is performed by one.
Since it must complete within a clock cycle, I
Access to ROM emulation is desired to be faster. In particular, if the clock frequency of the microcomputer is high, this demand becomes even stronger.

In order to respond to such a demand, as shown in FIG.
May be provided on the probe-side board 12. That is, means for mounting the IROM emulation memory 32 is provided on the probe side board 12.

In this manner, the length of the wiring pattern between the microcomputer 22 and the IROM emulation memory 32 can be shortened, and the speed of access to the IROM emulation memory 32 by the microcomputer 22 can be increased. That is, IROM
Compared to the case where the emulation memory 32 is provided on the memory-side board 14, the speed of memory access can be remarkably increased. Thus, the microcomputer 22 can easily complete the fetch and decode of the instruction within one clock cycle. As a result, at the time of evaluation,
The microcomputer 22 can be operated at the same high clock frequency as in the case of a product,
The operating environment at the time of evaluation and the operating environment at the time of product can be made the same.

Now, the IROM emulation memory 3
In order to further increase the speed of access to No. 2, it is more desirable to employ the two methods described below.

For example, in FIG. 7, connection lines 60 and 61
Are connection lines between the microcomputer 22 and the IROM emulation memory 32, and control signals CE2 and RD2 are transmitted to the IROM emulation memory 32 through these connection lines 60 and 61. Here CE
2 and RD2 are a chip enable signal and a memory read signal for the IROM emulation memory 32, respectively.
2 is a signal for controlling.

The connection lines 62 and 63 are connected to the connection line 60,
These are connection lines between the connector 61 and the connector 26, and control signals CE2 and RD2 are transmitted to the memory-side board via the connector 26 by these connection lines 62 and 63. That is, in the present embodiment, as described with reference to FIG.
The form of 28 terminals (number of terminals, terminal arrangement, signals assigned to each terminal, etc.) is standardized. Therefore, even when the IROM emulation memory 32 is mounted on the probe-side board and not mounted on the memory-side board,
The connection lines 62 and 63 will be present. This is because, when the IROM emulation memory 32 is provided on the memory-side board, connection lines 62 and 63 are required to operate the IROM emulation memory 32.

Now, the IROM emulation memory 3
2 to realize high-speed access to the control signal CE
2. It is necessary to reduce the signal delay of RD2. The signal delays of CE2 and RD2 are caused by buffers 68 and 6 in microcomputer 22 that output CE2 and RD2.
9 and the parasitic capacitance of the output terminals of the buffers 68 and 69.

However, the connection lines 60 and 61 and the connection line 6
2 and 63 are connected, the output terminals of the buffers 68 and 69 are connected not only to the parasitic capacitance of the connection lines 60 and 61 but also to the connection line 6.
Since the parasitic capacitances 2 and 63 are also added, the parasitic capacitances of the output terminals of the buffers 68 and 69 increase. In particular, since the connection lines 62 and 63 are connected to the memory-side board via the connector 26, the connection lines 62 and 6
The parasitic capacitance of No. 3 is very large.

Therefore, in FIG. 7, jumpers 64 and 65 (cutting means) are provided between the connection lines 60 and 61 and the connection lines 62 and 63. When the IROM emulation memory 32 is provided on the probe-side board, the jumpers 64 and 65 are cut off. On the other hand, when the IROM emulation memory 32 is provided on the memory-side board, the jumpers 64 and 65 are made conductive.

In this way, when the IROM emulation memory 32 is provided on the probe side board, the connection lines 60 and 61 and the connection lines 62 and 63 are disconnected, so that the output terminals of the buffers 68 and 69 are disconnected. Is only the parasitic capacitance of the connection lines 60 and 61. Therefore,
The signal delay of the control signals CE2 and RD2 can be minimized, and IR
High-speed access to the OM emulation memory 32 can be realized.

On the other hand, the IROM emulation memory 3
When 2 is provided on the memory-side board, the connection lines 60 and 61 are connected to the connection lines 62 and 63, and the control signals CE2 and RD2 can be appropriately transmitted to the IROM emulation memory 32 of the memory-side board. This is IRO
This means that the connectors 26 and 28 can be standardized regardless of whether the M emulation memory 32 is provided on the probe-side board or the memory-side board.

When the jumpers 64 and 65 are cut off, the jumpers 66 and 67 are turned on.
By doing so, the connection lines 62 and 63 can be pulled up to the H level, and a malfunction of the memory on the memory-side board can be prevented.

In FIG. 8, the IROM emulation memory 32 stores IROs for lower 8 bits (D0 to D7).
M emulation memory 32-1 and upper 8 bits (D
8 to D15) IROM emulation memory 32
-2. In order to realize a high-speed access, a high-speed S
RAM must be used, and most of high-speed SRAMs have 8
Because it is a bit product.

In FIG. 8, the IROM emulation memory 32-1 is mounted on, for example, the surface of the probe-side board 12, and the IROM emulation memory 3-1 is mounted.
2-2 is mounted on the back (the back almost at the same location as the location where the IROM emulation memory 32-1 is provided). That is, the IROM emulation memory 32-1
Is provided on the front side of the probe side board 12, and the mounting means of the IROM emulation memory 32-2 is provided on the back side.

That is, the IROM emulation memory 3
The SRAM constituting 2-1 and 32-2 is very fast,
The access time is about 6 nsec. Accordingly, the wiring pattern length between the microcomputer 22 and the IROM emulation memory 32-1 is different from the length of the wiring pattern between the microcomputer 22 and the IROM emulation memory 32-1.
-2, the wiring pattern lengths are different, and if the parasitic capacitances parasitic on these wiring patterns are different from each other, a difference occurs in the signal delay, and the IROM emulation memory 32-
1, 32-2 may malfunction.

In FIG. 8, the IROM emulation memories 32-1 and 32-2 are mounted on both sides in a sandwich structure, and the wiring pattern length between the microcomputer 22 and the IROM emulation memory 32-1, the microcomputer 22, and the IROM emulation memory 32-2
The wiring pattern length between them is the same (or almost the same). As a result, the parasitic capacitances parasitic on these wiring patterns can be made the same or almost the same.
High-speed S as M emulation memories 32-1 and 32-2
Even if a RAM is used, the malfunction can be prevented.

5. High-Speed Serial Interface As shown in FIG. 9, in the present embodiment, DST2, DST1, DST0, DPC are communicated with the ICE main unit (or a host system) via the serial interface 24.
Signals (information) such as O, DSIO, and DCLK are serially communicated.

Here, DST2 to DST0 are 3-bit signals for notifying the status of the instruction execution of the CPU 22. The DPCO is a signal indicating a PC (program counter) value at the branch destination. The DSIO transmits various instructions to be executed for debugging from the ICE body to the microcomputer 22,
2 is a signal for transmitting the response 2 from the microcomputer 22 to the ICE main body. DCLK is a clock signal for a debug mode.

When the microcomputer 22 is mounted on the emulation probe board,
As shown in FIG. 9, DST2 to DCLK are communicated between the microcomputer 22 and the ICE main unit via the connection lines 70 to 75 and the serial interface 24.

Further, even when the microcomputer 22 is mounted on the target system, DST2
It is desirable to be able to communicate DCLK with the ICE body. Therefore, as shown in FIG. 9, it is desirable to provide a serial interface 25 for communicating DST2 to DCLK with the ICE main body also on the target system side. Therefore, in this case, the connection lines 76 to 81 for connecting the microcomputer 22 and the serial interface 25 are also provided on the target system side. As a result, the connection lines 70 to 75 on the emulation probe board side are connected to the connection lines 76 to 81 via the connection lines 88 to 93 and the probe 20.

By the way, in order to realize an appropriate debugging environment even when the clock frequency of the microcomputer 22 is high, it is desired to further speed up the communication of DST2 to DCLK. For this purpose, connection lines 70 to 7
5 must be minimized. And
This signal delay is determined by the capacity of the buffers 82 to 87 for outputting DST2 to DCLK and the parasitic capacitance parasitic on the connection lines 70 to 75.

However, in FIG. 9, since the connection lines 70 to 75 and the connection lines 76 to 81 are connected, the parasitic capacitance of the connection lines 76 to 81 is added to the parasitic capacitance of the connection lines 70 to 75. It will be. For this reason, the signal delay on the connection lines 70 to 75 increases, and DST2 to DCT
This hinders the speeding up of LK communication.

Therefore, in FIG. 9, jumpers 94 to 99 (cutting means) for cutting the connection at the connection lines 88 to 93 are provided.

In this way, the connection lines 70 to 75 and the connection lines 76
To 81 are not connected. Accordingly, the parasitic capacitance of the connection lines 76 to 81 is not added to the parasitic capacitance of the connection lines 70 to 75, and the parasitic capacitance of the output terminals of the buffers 82 to 87 can be greatly reduced. Thereby, DST2
To DCLK, and the microcomputer 22 operates at a high clock frequency.
An appropriate debugging environment can be provided.

6. Separation of the second signal from the first signal In the present embodiment, as shown in FIG. 10, the second signal including the signal necessary for the operation of the emulation memory 30 among the first signals from the microcomputer 22 is used. Signal 1
02 is separated and transmitted between the microcomputer 22 and the emulation memory 30 (between the probe-side board 12 and the memory-side board 14).

That is, almost all signals input and output from the microcomputer 22 are transmitted as the first signal 100 to and from the probe 20. At the time of evaluation, as shown in FIG.
This is because the probe 20 must be connected to the target system 2 and the target system 50 must be operated using the microcomputer 22 on the emulation probe board 10.

However, the microcomputer 22
From the first signal 100 includes a variety of different signals,
The form of the first signal (the number of signals and the type of signal) differs depending on the type of the microcomputer 22. For example, the first signal 100 includes various signals such as a signal from a timer, a signal from an input / output port, a signal from an A / D converter, and the like in addition to general signals such as an address, data, and memory control signal. Is included. If the microcomputer 22 does not have an A / D converter, for example, the first signal does not include the signal from the A / D converter. Thus, it is difficult to standardize the form of the first signal 100.

Therefore, in the present embodiment, as shown in FIG.
The second signal 102 including the signal necessary for the operation of the signal 0 is separated and transmitted to the memory-side board 14 via the connectors 26 and 28. That is, the emulation memory 30 includes control signals for controlling addresses, data, memories, and the like.
Is included in the second signal 102 and transmitted to the memory-side board 14.

In this way, the form (the number of signals and the type of signal) of the second signal 102 is changed by the microcomputer 2
Therefore, it is possible to make the form independent of the two models, and to standardize the form of the terminals of the connectors 26 and 28. Therefore, as described with reference to FIG. 4, even if the type of the microcomputer 22 is changed, the same (or almost the same) memory board 14 can be used. As a result, even if the type of the microcomputer 22 is changed, only the probe-side board 12 needs to be newly recreated, so that the cost of the emulation probe board can be reduced and the design period can be shortened.

7. Mounting of Custom Chip As described above, in the present embodiment, the second signal 10 including a signal necessary for the operation of the emulation memory 30 is used.
2 from the first signal 100 and the memory side board 1
4 Such a second signal 102 includes:
Basic signals such as addresses, data, and various control signals input and output by the microcomputer 22 are included. Therefore, by using the second signal 102, various devices operable under the control of the microcomputer 22 can be operated in addition to the emulation memory 30.

Therefore, in FIG. 11A, the second signal 10
Custom chip 40 operable on the memory side board 1
4 That is, means for mounting the custom chip 40 is provided on the memory-side board 14.

That is, in recent years, an A in which a microcomputer serving as a core and a circuit designed by a user himself are incorporated.
What is called an SIC microcomputer is in the spotlight. According to such an ASIC microcomputer, it is possible to incorporate a microcomputer that is optimal for the user's application into the target system, and it is possible to improve the marketability of the target system, reduce costs, and the like.

If the user's custom chip 40 can be mounted on the memory side board 14 as shown in FIG. 11A, the user operates the custom chip 40 designed by himself under the control of the microcomputer 22. Thus, whether the operation is normal or not can be evaluated. Then, as shown in FIG. 11B, the user who has confirmed that the operation is normal is performed by the AS including the circuit 105 of the microcomputer 22 and the circuit 106 of the custom chip 40.
The IC microcomputer 104 is custom designed and incorporated into the user's target system.

In FIG. 11A, since the microcomputer 22 and the custom chip 40 are connected by the second signal 102, the operation is normal while the microcomputer 22 and the custom chip 40 are operated in cooperation with each other. Can be evaluated. Therefore, the ASIC microcomputer 104 incorporating the circuit 106 of the custom chip 40 whose normal operation has been confirmed by this evaluation can be expected to operate normally even in the user's target system. As a result, the user can custom design the ASIC microcomputer 104 in a short development period, so that the development period of the target system can be shortened and the cost can be reduced.

The custom chip 40 mounted on the memory side board 14 is an FPGA (Field Programmable).
Gate Array) can be adopted. When an FPGA is used as the custom chip 40, the FPGA
It is desirable that the configuration ROM 42 for storing the data of the logic circuit to be downloaded to the (custom chip) 40 be also mounted on the memory-side board 14. If such a configuration ROM 42 is mounted, the trouble of downloading the data of the logic circuit to the FPGA 40 when the power is turned on can be omitted.

In FIG. 11A, the FPGA 40 and the I
An interface 44 between the CE main unit (or host system) and an interface 46 between the FPGA 40 and the target system are provided on the memory-side board 14.

Here, the interface 44 is a JTA
It is a high-speed serial interface conforming to G or the like, and is for communicating data of a logic circuit to be downloaded to the FPGA 40 and the like. By providing such an interface 44, the user can freely rewrite the data of the logic circuit that he / she wants to test, and the user's convenience can be improved.

The interface 46 is an FPGA
This is for transmitting 40 input / output signals to the target system. For example, consider a case where an LCD is provided in the target system and the circuit of the FPGA 40 is a display control circuit of the LCD. In this case, LC
The display control signal of D is transmitted to the target system via the interface 46. By providing such an interface 46, it becomes possible to evaluate and verify the cooperation operation between the ASIC microcomputer 104 and peripheral devices when the ASIC microcomputer 104 is incorporated in the target system before the integration. Thereby, the ASIC microcomputer 1
04 can be designed more efficiently and the design period can be shortened.

8. Acceleration of access to IROM emulation memory As described above, the internal R
Fetching and decoding instructions from an IROM emulation memory that emulates an OM must be completed within one clock cycle. Therefore, I
There is a problem that it is necessary to speed up the memory access to the ROM emulation memory.

Therefore, in order to achieve such a problem, in FIG. 12, buffers 108, 10 are connected between the microcomputer 22 and the EROM emulation memory 34.
9, the address and data (second signal) are transmitted, while the microcomputer 22 and the IROM emulation memory 32 transmit the address and data directly without using a buffer.

By doing so, in the signal transmission between the microcomputer 22 and the IROM emulation memory 32, the signal delay by the buffers 108 and 109 does not occur. Therefore, access to the IROM emulation memory 32 can be speeded up.

Note that the microcomputer 22 is an IRO
When accessing the M emulation memory 32, the buffers 108 and 109 are controlled using the control signal CNTB.
Is turned off. On the other hand, the microcomputer 22
Is accessing the EROM emulation memory 34 by using the control signal CNTB.
8 and 109 are turned on, and the control signal CNT2
To suppress the operation of the IROM emulation memory 32.

The method shown in FIG. 12 can be applied to a case where the IROM emulation memory 32 is mounted on the probe board 12 as shown in FIG.

9. Configuration of microcomputer Now, in a microcomputer, usually, FIG.
In addition to the product chip 700 for mass production as shown in FIG. 13A, an evaluation chip 710 for program and system development as shown in FIG. In the evaluation chip 710, a dedicated address bus 712 and a data bus 714 are provided in the emulation memory 716 in addition to the normal external address bus 702 and the external data bus 704 to which the external memory 706 is connected.

However, when the dedicated address bus 712 and data bus 714 are provided in the emulation memory 716 as described above, the terminals (pins) of the evaluation chip 710 are provided.
The number is much larger than the number of terminals of the product chip 700. Therefore, it becomes difficult to obtain a package on which the evaluation chip 710 can be mounted, or the product chip 700
The problem is that it becomes complicated to match the terminals with the evaluation chip 710. In addition, there is a problem that a program that normally operates on the evaluation chip 710 does not operate on the product chip 700.

To solve such a problem, FIG.
In the microcomputer 22, the device as described below is devised.

The microcomputer 22 shown in FIG.
PU (processor in a broad sense) 112, bus control unit (BC
U) 114, internal ROM (internally, internal memory) 11
6. Emulation instruction unit 118, memory control unit 12
Contains 0. An external bus (external bus terminal) 128 of the microcomputer 22 has an EROM emulation memory 34 (external memory in the case of a product), an IR
The OM emulation memory 32 can be connected. Note that another external device such as a gate array may be connected to the external bus 128.

Here, the CPU 112 performs an instruction execution process, and the CPU bus 122 of the CPU 112 is connected to the bus control unit 114. The status signal ST from the CPU 112 is also output to the bus control unit 114.

The internal ROM 116 stores information such as programs and data. The internal ROM bus 126 of the internal ROM 116 is connected to the bus control unit 114. At the time of evaluation or the like, the internal ROM 116 may not be built in the microcomputer 22.

The emulation instructing section 118 activates the emulation instructing signal EM when the emulation mode is ON, and issues an emulation instruction to the bus control section 114. in this case,
The on / off state of the emulation mode may be switched by providing a mode selection terminal in the microcomputer 22 and controlling the mode selection terminal, or by providing a mode selection register in the microcomputer 22 and storing in the mode selection register. Switching may be performed by controlling information.

The memory control section 120 controls various control signals (chip enable signal, memory read signal, etc.) CN for controlling the EROM emulation memory 34, the IROM emulation memory 32, and the internal ROM 116.
T1, CNT2, and CNT3 are output. In particular, in FIG. 14, control signals CNT1 and CN of different systems are supplied to the EROM emulation memory 34 and the IROM emulation memory 32 connected to the same external bus 128.
The feature is that T2 is output.

The bus control unit 114 includes a CPU bus 122,
This is for controlling the internal ROM bus 126, the external bus 128, and the like. The bus control unit 114 includes the CPU 11
2, the internal ROM bus 126 of the internal ROM 116 is connected to the CPU bus 122, and the external bus 128 to which the EROM emulation memory 34 and the IROM emulation memory 32 are connected is connected to the CPU bus 122 based on the address and the status signal ST. Bus control such as connection to

When the emulation mode (mode for emulating the internal ROM 116 with the IROM emulation memory 32) is instructed by the signal EM from the emulation instructing unit 118, the bus control unit 114 RO
Access to the M116 via the external bus 128
The access is switched to the access to the OM emulation memory 32. That is, the CPU bus 122 is connected to the internal ROM bus 12
6 instead of connecting to the external bus 128 and the CPU bus 12
2 and internal ROM 116 via internal ROM bus 126
Of the CPU 112 to the IROM emulation memory 32 via the CPU bus 122 and the external bus 128.

By doing so, the CPU 112
The operation is performed based on the program stored in the IROM emulation memory 32 instead of the program (or data) stored in the internal ROM 116.
Therefore, the user can store the program under development until the program is completed in the IROM emulation memory 32.
Can be downloaded at any time for program development. Then, after the development is completed, the completed program is stored in the internal ROM 116 so that a final product chip can be obtained.

Then, the microcomputer 2 shown in FIG.
In No. 2, the IROM emulation memory 32 is accessed by using an external bus 128 used for accessing an external memory in a product (see FIG. 13A). Therefore, there is no need to provide a dedicated address bus 712 and data bus 714 in the emulation memory 716 as shown in FIG. Therefore, the number of terminals (pins) of the product chip and the evaluation chip can be the same. Therefore, the product chip can be used as it is as an evaluation chip, and the cost of the product can be reduced.

Further, according to the microcomputer 22 shown in FIG. 14, it is possible to save trouble such as preparing a separate package for the evaluation chip and maintaining the matching between the product chip and the terminals of the evaluation chip.

According to the microcomputer 22 shown in FIG. 14, since the product chip can be used as it is as the evaluation chip, the program can be developed in the same environment and signal timing as in the actual operation. As a result, the reliability of the product chip can be improved, the development period can be shortened, and the product cost can be reduced.

When the access to the internal ROM 116 of the CPU 112 is switched to the access to the IROM emulation memory 32, the access to the internal ROM 116 is sufficient if the access to the area of the memory space to which the internal ROM 116 is allocated. . For example, consider a case where the internal ROM 116 is not built in the microcomputer 22 at the time of evaluation or the like. In this case, since the internal ROM 116 does not physically exist, the CPU 1
Even if the 12 accesses the internal ROM 116, the access is limited to the access to the area of the memory space to which the internal ROM 116 is allocated.

When the IROM emulation memory 32 is accessed using the external bus 128 as shown in FIG. 14, the following problem occurs.

That is, the fetch and decode of the instruction (program) stored in the internal ROM 116 must be completed within one clock cycle. Therefore, in the emulation mode, the instructions in the IROM emulation memory 32 must be fetched and decoded within one clock cycle.

However, the external bus 128 is
Unlike (B), the IROM emulation memory 32
Not a dedicated bus. Therefore, external memory (at the time of product)
Attempting to control the IROM emulation memory 32 in exactly the same way as the EROM emulation memory 34 (at the time of evaluation) causes a problem that fetching and decoding of instructions within one clock cycle cannot be realized. In particular, this problem becomes more serious as the clock frequency increases.

Therefore, in FIG. 14, a control signal CNT2 of a different system from the control signal CNT1 for controlling the EROM emulation memory 34 is prepared. I have to. More specifically,
The signal is controlled so that the memory read signal included in CNT2 becomes active earlier than the memory read signal included in CNT1. In this way, even when the IROM emulation memory 32 is accessed using the external bus 128, the fetch and decode of the instruction can be completed within one clock cycle. This facilitates program development using the IROM emulation memory 32 at the clock frequency during actual operation.

FIG. 15 shows a detailed configuration example of the microcomputer 22.

Here, the CPU 112 employs a Harvard architecture bus configuration. Instruction address bus 150 and data address bus 15 of CPU 112
2 is input to the multiplexer 140. The multiplexer 140 selects one of an address from the instruction address bus 150 and an address from the data address bus 152 based on an instruction / data switching signal DIS (one of status signals) from the CPU 112.
Output to the external address bus 154.

The data output bus 158 of the CPU 112
External data bus 156 via input / output pad cell 148
Connected to. The data input bus 1 of the CPU 112
Reference numeral 60 denotes an instruction / data switching unit 142, a data bus 1
62, connected to the external data bus 156 via the input / output pad cell 148.

Instruction fetch bus 164 of CPU 112
Are connected to the internal ROM 116 and to the external data bus 156 via the command / data switching unit 142, the data bus 162, and the input / output pad cell 148.

The memory control unit 20 outputs the first chip enable signal CE1 and the first memory read signal RD1 to ER
Output to the OM emulation memory 34. Also, C
A second chip enable signal CE2 and a second memory read RD2 of a different system from E1 and RD1 are output to the IROM emulation memory 32. Further, it outputs the third chip enable signal CE3 and the third memory read signal RD3 to the internal ROM 116. That is, the memory control unit 120
Are those CE1, RD1, CE2, RD2, CE
3, RD3, EROM emulation memory 34, IROM emulation memory 32, internal RO
The read operation from M116 is controlled.

The mode selection terminal MT, the mode selection register 144, and the OR circuit 146 correspond to the emulation instruction unit 118 in FIG. That is, the terminal MT is at H
Level or the mode selection register 144
When the level is stored, the emulation mode instruction signal EM becomes H level, and the bus switching control for the emulation mode is performed.

Next, the microcomputer 22 shown in FIG.
Will be briefly described.

In the case of instruction fetch, the instruction / data switching signal DIS indicates an instruction, and the multiplexer 140 selects the instruction address bus 150. Thereby, the external address bus 154 and the internal RO
An instruction address is output to the M address bus 155. That is, an instruction address is input to both the IROM emulation memory 32 and the internal ROM 116.

At this time, if the L level is stored in the mode selection register 144 and the terminal MT is also set to the L level, the emulation mode is turned off and the signal E
M becomes L level. In addition, since it is an instruction fetch, C
The signal READ from the PU 112 (status signal 1
Also become active. Thereby, the memory control unit 1
20 decodes the address from the address bus 155, and if the address is in the internal ROM area, the internal ROM
Activate the third chip enable signal CE3 and the third memory read signal RD3. Thus, an instruction from the internal ROM 116 is read out to the CPU 112 via the instruction fetch bus 164. That is, the CPU 112 fetches and executes the instruction stored in the internal ROM 116.

On the other hand, when the H level is stored in the mode selection register 144 or the terminal MT is set to the H level, the emulation mode is turned on and the signal EM is turned on.
Becomes H level. Then, the memory control unit 120 outputs the second chip enable signal CE to the IROM emulation memory 32 instead of the CE3 and RD3.
2. Activate the second memory read signal RD2. Since the instruction is an instruction fetch, the signal DIS indicates the instruction and the signal READ becomes active, and the instruction / data switching unit 142 selects the instruction fetch bus 164 instead of the data input bus 160. become. As described above, the instruction from the IROM emulation memory 32 is read out to the CPU 112 via the external data bus 156, the input / output pad cell 148, the data bus 162, the instruction / data switching unit 142, and the instruction fetch bus 164. That is, CP
The U112 fetches and executes instructions stored in the IROM emulation memory 32 instead of the internal ROM.

While the instructions in the IROM emulation memory 32 are being read, the internal RO
The output of the tri-state buffer 117 incorporated in M116 enters the tri-state state. This prevents data collision on the instruction fetch bus 164.

As described above, in the microcomputer 22 shown in FIG. 15, when the emulation mode is off (the signal EM is at the L level) when the CPU 112 fetches an instruction, the instruction from the internal ROM 116 is sent to the instruction fetch bus 164 as usual. Is fetched and executed by the CPU 112 via the. On the other hand, when the CPU 112 fetches an instruction, the emulation mode is turned on (the signal EM is at H level).
In this case, the instruction from the IROM emulation memory 32 instead of the internal ROM 116
6 and is fetched and executed by the CPU 112.

Therefore, before completion of the program, the user turns on the emulation mode using the terminal MT or the mode selection register 144, and develops the program while downloading the program under development to the IROM emulation memory 32 as needed. When the development of the program is completed, the user stores the completed program in the internal ROM 116 (creates a mask pattern). Then, the emulation mode is turned off using the terminal MT or the mode selection register 144. Thus, a product chip in which the CPU 112 operates based on the instruction from the internal ROM 116 is completed.

The microcomputer 22 shown in FIG.
In this case, the IROM emulation memory 32 is not provided with a dedicated address bus and data bus. Therefore, IR
An evaluation chip on which the CPU 112 operates according to an instruction (program) from the OM emulation memory 32;
The product chip that operates on the CPU 112 according to the instruction from M116 is the same chip that does not differ in the number of terminals, the layout of pads, the layout of signal lines, and the like. Therefore, the program can be developed using the product chip itself. As a result, due to the difference in the operating environment and the timing of signals between the evaluation and the product (actual operation), problems such as normal operation at the time of evaluation but cessation of operation at the time of product are effectively prevented. Be able to solve.

Now, as described above, the external address bus 15
4. By adopting the method of accessing the IROM emulation memory 32 using the external data bus 156, the advantage that the product chip and the evaluation chip can be the same chip can be obtained. However, on the other hand, according to this method, there is a problem that reading of instructions from the IROM emulation memory 32 cannot be performed in time.

That is, the EROM emulation memory 3
4 (at the time of evaluation) and reading of information from the external memory (at the time of product), there is usually sufficient time margin. On the other hand, since the fetch and decode of the instruction by the CPU 112 must be completed within one clock cycle, there is not enough time for reading the instruction from the IROM emulation memory 32.

Therefore, in FIG. 15, a chip enable signal CE2 and a memory read signal RD2 of a different system from the CE1 and RD1 for the EROM emulation memory 34 (or a system different from the chip enable signal for the external memory and the memory read signal). The data is output to the memory control unit 120. Thereby, the external address bus 154 and the external data bus 156 are connected to the EROM emulation memory 34 and the I
While sharing the ROM emulation memory 32,
Fetching and decoding of instructions from the IROM emulation memory 32 can be completed within one clock cycle. The above is described in detail with reference to the signal waveform diagram of FIG.

In FIG. 16, the CPU 112 executes the following command. Instruction (1) ld% r2, 0x00 Instruction (2) ld% r1, [% r9] Instruction (3) add% r4,% r1 Instruction (4) sub% r5,% r1 In the above, the instruction ( 1) is an instruction to load data 0x00 into the general-purpose register r2 of the CPU 112. The instruction (2) is an instruction to load data from the address of the EROM emulation memory 34, which is the address stored in the general-purpose register r9, into the general-purpose register r1. That is, the EROM emulation memory 3
4 is an instruction to load the data from the general-purpose register r1. Instruction (3) is composed of the data of general-purpose register r4 and r1
Is an instruction to add the data of The instruction (4) is an instruction for subtracting the data of r1 from the data of the general-purpose register r5.

These instructions (1), (2), (3),
(4) is executed by pipeline processing as indicated by B1 in FIG. In B1, F indicates instruction fetch, D indicates instruction decode, R indicates register read, A indicates address calculation, E indicates instruction execution, and W indicates write to register.

BCLK shown at B2 in FIG. 16 is a bus clock for determining a bus cycle.
Is also the operation clock of the CPU 112.

In FIG. 16, as indicated by B3, first, IRO
An instruction is read from the M emulation memory 32, then data is read from the EROM emulation memory 34, and then an instruction is read from the IROM emulation memory 32.

That is, as shown by B4, B5, and B6 in FIG. 16, an address for reading the instructions (1), (2), and (3) from the IROM emulation memory 32 is output to the external address bus 154. These addresses are output from the CPU 112 to the external address bus 154 via the instruction address bus 150 and the multiplexer 140. As a result, as shown in B7, B8 and B9, the instruction (instruction data) corresponding to each address is
The data is read from the M emulation memory 32 and output to the external data bus 156. These instructions are sent from the external data bus 156 to the input / output pad cell 14.
8, data bus 162, instruction / data switching unit 14
2. CPU 112 via instruction fetch bus 164
Fetched and decoded.

In B10 of FIG. 16, the read address to the EROM emulation memory 34 is CP
The data is output from U112 to the external address bus 154 via the data address bus 152 and the multiplexer 140. This address is the address [% r9] specified by the instruction (2). As a result, as shown in B11, the data from the EROM emulation memory 34 is output to the external data bus 156, and the CPU 112
Is read out.

At B12 in FIG. 16, an address for reading the instruction (4) from the IROM emulation memory 32 is output to the external address bus 154. As a result, the instruction corresponding to this address is output from the IROM emulation memory 32 to the external data bus 156, as indicated by B13.

When reading data from the EROM emulation memory 34, the first chip enable signal CE1 and the first memory read signal RD1 are activated (set to L level) as shown by B14 and B15 in FIG. . On the other hand, the IROM emulation memory 32
When the instruction is read out from the memory, the second chip enable signal CE2 and the second memory read signal RD2 are activated as shown in B16 to B21.

At this time, as shown in B15, RD1
It becomes active in synchronization with the fall of CLK. On the other hand, as shown in B18 to B21, RD2 is BCLK
It becomes active in synchronization with the rising edge of. More specifically, it becomes active after a lapse of a given delay time (delay time in the delay element) TD from the rise of BCLK. That is, RD2 is controlled to become active earlier than RD1.

By activating RD2 at an earlier timing as described above, the fetch (F) and decode (D) of the instruction by the CPU 112 can be completed within one clock cycle.

That is, the EROM emulation memory 3
When the instruction is read from the IROM emulation memory 32 using RD1 used for
Since it becomes active in synchronization with the falling edge of CLK,
There is a problem that the fetch and decode of the instruction by the CPU 112 cannot be completed within one clock cycle. In particular, when the clock frequency of BCLK increases,
The probability that this problem will occur is even higher.

In this case, for example, at the time of evaluation,
When reading the instruction from the emulation memory 32, the above problem can be solved by lowering the clock frequency of BCLK. However, this causes a difference between the clock frequency at the time of actual operation and the clock frequency at the time of program development, which causes a problem that a program that normally operates at the time of program development does not operate normally at the time of actual operation. Therefore, the advantage that the product chip and the evaluation chip can be the same chip is substantially lost.

On the other hand, in FIG. 16, RD2 different from RD1 is prepared, and RD2 is set as shown in B18 to B21.
2 is activated early so that IR
Fetching and decoding of instructions from the OM emulation memory 32 can be properly completed within one clock cycle. Therefore, the program can be developed at the same clock frequency as that in the actual operation. Even when the program development is completed and the completed program is stored in the internal ROM 116, the program can operate normally without any problem. . Therefore, the microcomputer 22 that the product chip and the evaluation chip can be the same chip by sharing the external address bus 154 and the external data bus 156.
You will be able to take advantage of the benefits.

At B22 in FIG. 16, since a wait is inserted in reading data from the EROM emulation memory 34, the pipeline processing of the CPU 112 is stalled. That is, the external address bus 1
There is a possibility that various EROM emulation memories 34 (RAM, flash memory, etc.) having different reading and writing speeds are connected to the external data bus 156. Therefore, it is possible to insert a wait into a period in which the signals CE1 and RD1 are active, and various EROs having different reading and writing speeds are provided.
It can correspond to the M emulation memory 34.

On the other hand, I at which signals CE2 and RD2 are output
As described above, it is necessary to read an instruction from the ROM emulation memory 32 in one clock cycle. Therefore, unlike CE1 and RD1, no wait is inserted during the period when CE2 and RD2 are active.

Note that the present invention is not limited to this embodiment,
Various modifications can be made within the scope of the present invention.

For example, in the invention according to the dependent claims of the present invention, a configuration in which some of the constituent elements of the dependent claims are omitted may be adopted. In addition, a main part of the invention according to one independent claim of the present invention may be made dependent on another independent claim.

In the present invention, it is particularly preferable that the probe-side board and the memory-side board be configured to be separable, as shown in FIG.

The debug information communicated with the debug tool via the high-speed serial interface is not limited to the information described in the present embodiment.

The connectors provided on the probe-side board and the memory-side board are also preferably those described with reference to FIG. 5, but are not limited thereto.

The mounting method and wiring connection when the emulation memory for the internal memory is provided on the probe-side board are particularly desirably those described in the present embodiment, but are not limited thereto.

An FPGA is particularly desirable as a custom chip mounted on the memory-side board, but is not limited to this.

The first control signal for controlling the emulation memory for the external memory and the second control signal for controlling the emulation memory for the internal memory are also the signals described with reference to FIGS. Is particularly desirable, but is not limited to this.

[Brief description of the drawings]

FIG. 1A and FIG. 1B are CPU replacement ICs.
FIG. 9E is a diagram for explaining a problem of the conventional on-chip debug type ICE.

FIG. 2 is a diagram for describing a basic configuration of the present embodiment.

FIG. 3 is a diagram for explaining a method of enabling an emulation probe board to be separated into a probe-side board and a memory-side board.

FIG. 4 is a diagram for explaining a method of standardizing the form of the terminal of the connector of the memory-side board while allowing the form of the terminal of the probe of the probe-side board to be customized.

FIG. 5 is a diagram for explaining a method of providing a connector connectable to a flat cable on a memory-side board;

FIG. 6 is a diagram for explaining a method of providing an IROM emulation memory on a probe-side board.

FIG. 7 is a diagram for explaining a method of providing a jumper on a connection line for transmitting a control signal of an IROM emulation memory.

FIG. 8 is a diagram for explaining a method of mounting two IROM emulation memories on both sides in a sandwich structure.

FIG. 9 is a diagram for explaining a method of providing a jumper on a connection line transmitting debug information to be serially communicated.

FIG. 10 is a diagram for explaining a method of separating a second signal from among the first signals from the microcomputer and transmitting the separated second signal to the memory-side board;

FIGS. 11A and 11B are diagrams for explaining a method of mounting a custom chip on a memory-side board.

FIG. 12 shows an example of IR and address without interposing a buffer.
FIG. 4 is a diagram for explaining a method of transmitting data to an OM emulation memory.

FIGS. 13A and 13B are diagrams for explaining a conventional method in which a product chip and an evaluation chip are separated from each other.

FIG. 14 is a block diagram illustrating a configuration example of a microcomputer.

FIG. 15 is a block diagram illustrating a more detailed configuration example of a microcomputer.

FIG. 16 is a signal waveform diagram for explaining the operation of the microcomputer.

[Explanation of symbols]

10 Emulation Probe Board 12 Probe Side Board 14 Memory Side Board 20 Probe 22 Microcomputer 24 Serial Interface 26 Connector 27 Flat Cable 28 Connector 29 Connector 30 Emulation Memory 32, 32-1, 32-2 IROM Emulation Memory 34 EROM Emulation Memory 40 Custom Chip (FPGA) 42 Config ROM 44 Interface 46 Interface 50 Target system 52 Socket 54 ICE main body 56 Host system 60 to 63 Connection line 64 to 67 Jumper 68, 69 Buffer 70 to 81 Connection line 82 to 87 Buffer 88 to 93 Connection line 94 To 99 jumper 100 first signal 102 second signal 104 ASIC Black circuit computer 105 microcomputer circuit 106 custom chips 108, 108 buffer

Claims (15)

[Claims] 1. An emulation probe board for supporting development of a target system in which a microcomputer having an on-chip debug circuit is incorporated, wherein the emulation probe board is a mounting means for mounting the microcomputer. A probe for connecting to the mounting means; a second mounting means for mounting the microcomputer; and the on-chip debug circuit between the microcomputer mounted on the second mounting means and the outside. A first interface for serially communicating debug information for the target device, and third mounting means for mounting an emulation memory for emulating a memory used in the target system. Emulation pro Bubodo. 2. The probe according to claim 1, wherein the probe, the second mounting means for mounting the microcomputer, a probe-side board provided with at least a first connector, and the emulation memory are mounted. The third for
An emulation probe board, wherein the mounting means is separated from a memory-side board provided with at least one second connector connected to the first connector. 3. The terminal according to claim 2, wherein the form of the terminal of the probe on the probe-side board is customizable, and the form of the terminal of the second connector of the memory-side board is standardized. And emulation probe board. 4. The probe according to claim 2, wherein a third connector for directly connecting to the first connector of the probe-side board, and a first connector of the probe-side board via a cable. An emulation probe board, wherein a fourth connector for connection is provided on the memory-side board as the second connector. 5. The emulation memory according to claim 2, wherein the emulation memory is an emulation memory for an internal memory for emulating an internal memory of the microcomputer, and an emulation memory for emulating an external memory of the microcomputer. An emulation probe board comprising: a memory emulation memory; and a fourth mounting means for mounting the internal memory emulation memory on the probe-side board. 6. The first connection line according to claim 5, wherein the first connection line connects the microcomputer to the emulation memory for the internal memory and receives a control signal for controlling the emulation memory for the internal memory. A second connection line connecting the first connection line to the first connector and transmitting the control signal;
An emulation probe board, comprising: first disconnection means for disconnecting the connection by the second connection line. 7. The emulation memory according to claim 5, wherein the emulation memory for the internal memory is a first or a second emulation memory.
Wherein the fifth mounting means for mounting the first internal memory emulation memory is provided on a first surface of the probe-side board, and wherein the second internal memory emulation is provided. An emulation probe board, wherein sixth mounting means for mounting a memory is provided on a second surface of the probe-side board. 8. The third connection line according to claim 1, wherein the third connection line connects the microcomputer to the first interface and transmits the debug information. An emulation probe board, comprising: a fourth connection line connecting between the probe and a probe; and a second disconnecting unit for disconnecting the connection by the fourth connection line. 9. The second signal including a signal necessary for operation of the emulation memory among the first signals from the microcomputer.
An emulation probe board characterized in that the signal of (1) is transmitted between the microcomputer and the emulation memory. 10. The emulation probe board according to claim 9, wherein a seventh mounting means is provided for mounting a custom chip operable with the second signal. 11. The device according to claim 10, wherein at least one of a second interface serving as an interface between the custom chip and the outside and a third interface serving as an interface between the custom chip and the target system are provided. An emulation probe board characterized in that: 12. The microcomputer according to claim 9, wherein the emulation memory includes an emulation memory for an internal memory for emulating an internal memory of the microcomputer, and an emulation memory for emulating an external memory of the microcomputer. A memory emulation memory, wherein the microcomputer and the external memory emulation memory include a second buffer via a given buffer.
Wherein the second signal is transmitted between the microcomputer and the emulation memory for the internal memory without passing through the buffer. 13. The emulation memory according to claim 1, wherein the emulation memory is an emulation memory for an internal memory for emulating an internal memory of the microcomputer, and an emulation memory for emulating an external memory of the microcomputer. An emulation memory for a memory, wherein a second control signal of a different system from the first control signal for controlling the emulation memory for the external memory is provided to the emulation memory for the internal memory. Probe board. 14. The method according to claim 13, wherein the second memory read signal included in the second control signal is:
An emulation probe board which is activated at an earlier timing than a first memory read signal included in the first control signal. 15. The emulation probe board according to claim 1, the microcomputer mounted on the emulation probe board, the emulation memory mounted on the emulation probe board, and the first interface And a debug tool through which debug information is communicated.