JP2000315803A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent drift of heavy metal ion and electrostatic breakdown of a gate electrode by composing a gate insulation film of a specified material using a material gas of nitrogen monoxide, or the like. SOLUTION: A silicon oxide film added with chlorine is formed as an underlying film 102 on a glass substrate 101 in order to suppress the effect movable ions of Na or heavy metal. An amorphous silicon film 103 is then deposited by PCVD. The silicon film 103 serves as an active layer forming a source, a channel region and a drain. A gate insulation film is then formed on the silicon film 103 and a protective layer 104 for preventing contamination of the silicon oxide film, and the like, during crystallization is provided. Using chlorsilane or dichlorsilane as a material gas, an SiOxNy film 107 serving as a gate insulation film is formed on the silicon film 103 serving as an active layer. This film satisfied the conditions of energy gap band 5.31-7.0 eV, dielectric constant 4-6, and 0<x<2.0, 0<y<4/3 and the conditions can be altered depending on the fabrication conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an insulated gate type field effect semiconductor device (generally called a thin film transistor or TFT) using a thin film semiconductor formed on an insulating substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, insulating substrates (especially glass substrates)
2. Description of the Related Art An insulated gate field effect semiconductor device (hereinafter, referred to as TFT) using a thin film semiconductor formed thereon is known. TFTs formed on these insulating substrates are used in devices such as liquid crystal displays and image sensors.

[0003] In the above TFT,
Usually, silicon oxide (SiO ₂ ) is used as the gate insulating film.

[0004]

SUMMARY OF THE INVENTION The above conventional T
If the FT is formed on a glass substrate, the entire device is likely to be charged with static electricity, so that there is a problem that the gate insulating film is broken down by the static electricity. That is, there is a problem that a high voltage is applied across the gate insulating film due to electrostatic charging, and the gate insulating film cannot withstand the voltage.

The above problem is considered to be caused by the fact that the energy band gap (Eg) of the silicon oxide (SiO ₂ ) film is as large as about 8 eV and its relative dielectric constant is as relatively small as about 3.8.

In place of the silicon oxide film, a silicon nitride (Si ₃ N ₄ ) film having an Eg of about 5 eV and a relative permittivity of about 7 may be used as a gate insulating film. When is used as a gate insulating film, since the Si cluster becomes a charge trapping center, hysteresis appears in the CV characteristics. In the BT process, ΔV _th is about 10 V
There is an inconvenience of moving to the extent. That is, when silicon nitride is used as the gate insulating film, the charge trapping center is present in the insulating film, which is not preferable as the insulating film.

[0007]

According to the present invention, there is provided an insulated gate type field effect semiconductor device, wherein the gate insulating film is made of SiO.
wherein a being composed of a material represented by _x N _y, it is an gist. In particular, forming a TFT having the above structure over an insulating substrate is useful for preventing electrostatic breakdown due to static electricity.

Further, the present invention is characterized in that chlorine (Cl) is added to the gate insulating film made of the material represented by SiO _x N _y .

Further, the chlorine-added SiO
In forming the material represented by _x N _y, in order to add chlorine to the film, is characterized in using a vapor phase method using a chlorosilane or dichlorosilane, as a material gas.

The material represented by SiO _x N _y has an energy band gap of 5.3 to 7.0 eV, a relative permittivity of 4 to 6, and x and y satisfy 0 <x <.
2, 0 <y <4/3. The above x and y can be changed depending on manufacturing conditions, and may be set according to the embodiment.

As a method of forming a material represented by SiO _x N _y , PCVD (13.56 MHz), LPCVD, light C
A gas phase method such as a VD method or a PCVD method that applies a pulse waveform can be used.

Further, the insulating film represented by SiO _x N _y of the present invention can be artificially doped with another halogen element or an impurity, if necessary.

[0013]

[Action] SiO _x N _y is, Eg is 5.3 ～7.0Eg, specific since a dielectric constant 4-6, floor notes Nordheim current (tunnel current through an insulating film), a silicon oxide film than about one order of magnitude A large amount of flow can be caused, and it is possible to suppress the occurrence of electrostatic breakdown.

The SiO _x N _y film serving as a gate insulating film contains oxygen, which acts to eliminate hysteresis, and furthermore, N (SiN bond) is converted to Na.
And acts to prevent drift of heavy metal (Fe, Ni, or Co) ions.

Further, since chlorine (Cl) is added, Na ions or Fe ions can be neutralized (fixed) as NaCl or FeCl, and furthermore, the adverse effect of impurity ions in the gate insulating film can be suppressed. Can be.

[0016]

[Embodiment 1] FIG. 1 shows an example of manufacturing a TFT using the present invention. First, a glass substrate (Corning 7059, 300 mm x 300 mm or 100 mm
A silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 102 on (× 100 mm) 101. Chlorine is added to this silicon oxide film so as to suppress the influence of mobile ions of Na and heavy metals.

The oxide film may be formed by a sputtering method in an oxygen atmosphere or a method of annealing a film obtained by decomposing and depositing TEOS by plasma CVD at 450 to 650 ° C. Chlorine may be added to the atmosphere or, if a sputtering method is used, to the target.

Thereafter, a plasma CVD method (PCVD method)
Silicon film 1 by LPCVD or LPCVD
03 is 30 to 150 nm, preferably 50 to 100 nm.
accumulate. This silicon film 103 becomes an active layer constituting a source region, a channel formation region, and a drain region.

Here, T using amorphous silicon
If an FT is manufactured, a gate insulating film may be formed on the silicon film 103. If crystalline silicon is used, thermal annealing (preferably at 600 ° C. or lower) or crystallization by laser light irradiation may be performed here. During crystallization, it is effective to provide the protective film 104 with a silicon oxide film or the like to prevent contamination of the silicon film.

Next, an SiO _x N _y film (hereinafter abbreviated as SiON) 107 serving as a gate insulating film is formed on the silicon film 103 serving as an active layer to a thickness of 200 to 1500 °. Since the SiON film has a relative dielectric constant of 4 to 6 and is about 50% larger than the relative dielectric constant of the silicon oxide film of 3.8, the thickness of the silicon oxide film must be increased to obtain the same electrical conditions. 50% thicker than in the case of The fact that the thickness of the gate insulating film can be made thicker under the same electrical conditions is due to the problem of withstand voltage (when the same voltage is applied, the thicker method weakens the electric field), and furthermore, through the pinhole. This is advantageous for the problem of leak.

As a forming method, a PCVD method using chlorosilane or dichlorosilane as a source gas is used. The formation conditions are such that the substrate temperature is 300 to 600 degrees and a high frequency of 13.56 MHz is used as the applied high frequency energy. A glass substrate represented by Corning 7059 generally has a glass transition temperature of 600 to 900 ° C., and preferably has a process temperature of 600 ° C. or less.

For example, when dichlorosilane (SiH ₂ Cl ₂ ) is used as a raw material gas, ammonia (NH ₃ ) and nitric oxide (N
₂ O), SiO _x N _y and H
Cl and H ₂ O are generated, and an SiO _x N _y film to which Cl (chlorine) is added is obtained. Also, when chlorsilane is used as a source gas, Cl can be similarly added to the film.

The SiO _x N _y film 107 is formed by a PCVD method in which an applied voltage is pulsed,
A PCVD method and a photo CVD method can be used.

Thereafter, if necessary, the silicon layer 103 is formed.
Annealing at 350 ° C. for 2 hours in a hydrogen atmosphere to improve the interface characteristics between the gate insulating film 107 and the gate insulating film 107.

Next, the silicon layer 103 is patterned into an island shape to form an NTFT region 105 and a PTFT region 106. NTFT is an abbreviation for N-channel TFT,
PTFT is an abbreviation for P-channel TFT.

Thereafter, an aluminum film having a thickness of 200 nm to 5 μm is formed by an electron beam evaporation method, and this is patterned, and as shown in FIG.
08 and 109 were formed.

Thereafter, an impurity imparting one conductivity type was implanted in a self-aligned manner into the island-shaped silicon film of each TFT by ion doping using the gate electrode portion as a mask. In this case, first phosphine (PH ₃ )
Is doped as a doping gas, then only the island-like region 105 in the figure is covered with a photoresist, and diborane (B ₂ H ₆ ) is used as a doping gas to form the island-like region 106.
Only boron was injected. The dose is 2 to 8 × 10
¹⁵ cm ^-2 , boron was set to 4 to 10 × 10 ¹⁵ cm ^-2, and the dose of boron was set to exceed that of phosphorus.

Further, as shown in FIG. 1D, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was applied to improve the crystallinity of the portion where the crystallinity was deteriorated by introducing the impurity region. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² .

Thus, the N-type impurity (phosphorus) is
P-type impurities (boron) are added to regions 112 and 11 at 0 and 111, respectively.
3 was formed. The sheet resistance in these regions is 200-8
It was 00Ω / □.

After that, an interlayer insulator 114 is formed on the entire surface.
Plasma CVD of TEOS as raw material and oxygen
Method, reduced pressure CVD method with ozone, or normal pressure CV
A 300-nm-thick silicon oxide film was formed by Method D. The substrate temperature is 150 to 400 ° C., preferably 200 to 30 ° C.
0 ° C.

Then, contact holes are formed in the source / drain of the TFT, and aluminum wirings 115 to 11 are formed.
7 was formed. FIG. 1E shows that the left NTFT and the right PTFT form an inverter circuit.

When the silicon film 103 is crystallized by thermal annealing, the mobility of the TFT is 50 to 10 for NTFT.
^{0cm 2 / Vs, 30~100cm 2 /} Vs in the PTFT
was gotten. In this embodiment, the maximum process temperature is 600 ° C.
Since it is as follows, if it is non-alkali glass such as Corning 7059, there is no shrinkage or warpage of the substrate. For this reason, even if the substrate is large as in this embodiment, the pattern is hardly displaced, which is convenient when applied to a large-area display or its driving circuit.

[Embodiment 2] FIG. 2 shows an outline of a manufacturing process of this embodiment. This embodiment is an example of manufacturing a TFT used for driving pixels of an active matrix liquid crystal display device.

As the substrate 201, a Corning 7059 glass substrate (thickness: 1.1 mm, 300 × 400 mm) was used. In order to prevent impurities such as sodium from the glass substrate from diffusing into the TFT, the glass substrate has a thickness of 5 to 50 nm, preferably 5 nm, over the entire surface by plasma CVD.
A silicon nitride film 202 having a thickness of about 20 nm is formed.

First, a base oxide film 2 is formed on the above glass substrate.
03 (silicon oxide) is formed. Then, the amorphous silicon film 20 is formed by LPCVD or plasma CVD.
4 (thickness 30 to 150 nm, preferably 30 to 50 n
m), and after dehydrogenation at 400 ° C. for 1 hour,
This was patterned to form an island-shaped semiconductor region (TFT active layer).

Further, in the same manner as in Example 1, Si
The ON film was formed as the gate insulating film 205. Of course, before forming the gate insulating film, the amorphous silicon film 2
04 is irradiated with laser light or thermally annealed (preferably at a temperature of 600 ° C. or less) to promote its crystallization, and has crystalline silicon (crystallite, polycrystal, polysilicon, semi-amorphous, etc.) (General term for silicon film).

Next, an aluminum gate electrode 206 was formed in the same manner as in Example 1, and the substrate was immersed in an electrolytic solution, and this was used as an anode to conduct electricity. A coating 209 was formed.
Such anodizing technology is disclosed in Japanese Patent Application Nos. 4-30220, 4-38637 and 4-38637 filed by the present inventors.
54322. FIG. 2B shows a state in which this step is completed. After the anodization step is completed, a negative voltage, for example, a voltage of -100 to -200 V may be applied for 0.1 to 5 hours. At this time, the substrate temperature is preferably set to 100 to 250C, typically 150C.

In this step, mobile ions in the silicon oxide or at the silicon oxide-silicon interface are attracted to the gate electrode (Al). Thus, after anodizing,
Alternatively, a technique of applying a negative voltage to the gate electrode during anodic oxidation is disclosed in Japanese Patent Application No. 4-115503 filed by the present inventors.
(Filed on April 7, 1992).

The oxide film 209 on the side surface of the gate electrode 206 serves as a mask during the subsequent ion implantation.
An offset gate structure can be formed.

Thereafter, boron as a P-type impurity is implanted into the silicon layer by ion doping in a self-aligned manner.
FT source / drain 208 and 209 are formed, and further, as shown in FIG. 2 (C), this is irradiated with a KrF excimer laser beam to crystallize the silicon film whose crystallinity has been deteriorated due to the ion doping. Improve the sex. At this time, the energy density of the laser beam is 250-30.
It was set to 0 mJ / cm ² . By this laser irradiation, the source / drain sheet resistance of this TFT becomes 30
0 to 800Ω / □.

At this time, an offset gate structure is realized in a self-aligned manner by the action of the oxide film 209.

Thereafter, the interlayer insulator 2 is made of polyimide.
10 was formed, and the pixel electrode 211 was formed by ITO. Then, a contact hole is formed, and T
Electrodes 212 and 213 were formed of a chrome / aluminum multilayer film in the source / drain regions of the FT, and one of the electrodes 213 was also connected to ITO. The chromium / aluminum multilayer film has a chromium film of 20 to 200 n underneath.
m, typically 100 nm, with an aluminum film 10
It is made of deposited 0-2000 nm, typically 500 nm. It is desired that these are continuously formed by a sputtering method.

Finally, the silicon was annealed at a temperature of 200 to 300 ° C. for 2 hours in hydrogen to complete the hydrogenation of silicon.
Thus, the TFT was completed.

The example shown here is an example in which one driving TFT (P-channel type TFT) is formed in one pixel, but by performing the above steps simultaneously, a large number of TFTs are formed.
Are arranged in a matrix, and an active matrix liquid crystal display device can be manufactured.

Another application example of the present invention is a so-called three-dimensional IC for forming a TFT in a semiconductor integrated circuit after a metal wiring is formed. Various other applications are also possible.

[0046]

[Effect] TF provided on an insulating substrate, particularly a glass substrate
T gate insulating film is SiO_xN _yBy this, it is possible to prevent electrostatic breakdown of the gate electrode.・ Drift of Na and heavy metal ions by SiN bond
Can be prevented.・ Since there is no fixed charge in the film, C─V characteristic
Expects stable operation without hysteresis
Can be.

In the method of producing the SiO _x N _y film, Cl (chlorine) can be added to the film by using chlorosilane or dichlorosilane as a raw material gas. Since the ions can be immobilized, more stable effects can be obtained in addition to the above effects.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of Example 1.

FIG. 2 shows a manufacturing process of Example 2.

[Explanation of symbols]

 Reference Signs List 101 glass substrate 102 base oxide film 103 silicon film 104 protective film 105 island-shaped semiconductor region (for NTFT) 106 island-shaped semiconductor region (for PTFT) 107 gate insulating film 108 gate electrode (for NTFT) 109 gate electrode (for PTFT) 110 N-type impurity region 111 N-type impurity region 112 P-type impurity region 113 P-type impurity region 114 Interlayer insulator 115 to 117 Metal wiring 201 Glass substrate 202 Silicon nitride film 203 Base oxide film 204 Silicon film 205 Gate insulating film 206 Gate electrode 208 / 209 Source / drain 210 Interlayer insulator 211 Pixel electrode 212,213 Electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 627E 627F

Claims (5)

[Claims] 1. A method for manufacturing an insulated gate type field effect semiconductor device, comprising: using chlorsilane, ammonia, and nitric oxide as a source gas to form a SiO _x N _y to which chlorine is added.
A method for manufacturing a semiconductor device, comprising forming a gate insulating film made of a material represented by the following formula: 2. A method for manufacturing an insulated gate field effect semiconductor device, dichlorosilane as a raw material gas by using ammonia and nitric oxide, SiO _x doped with chlorine
The method for manufacturing a semiconductor device, which comprises forming a gate insulating film made of a material represented by N _y. 3. A method of manufacturing insulated gate field effect semiconductor device, a silicon film, chlorosilane as a raw material gas by using ammonia and nitric oxide, SiO _x N _y doped with chlorine
A method of manufacturing a semiconductor device, comprising: forming a gate insulating film made of a material represented by the following formula: and annealing the silicon film and the gate insulating film in a hydrogen atmosphere. 4. A method for manufacturing an insulated gate type field effect semiconductor device, comprising: forming a silicon film, using dichlorsilane, ammonia, and nitrogen monoxide as a source gas, thereby adding SiO _x to which chlorine is added.
A method for manufacturing a semiconductor device, comprising: forming a gate insulating film made of a material represented by N _y , and annealing the silicon film and the gate insulating film in a hydrogen atmosphere. 5. The gate insulating film according to claim 1, wherein an energy band gap of the gate insulating film is 5.
3 to 7.0 eV; a relative dielectric constant of 4 to 6; and x and y satisfy 0 <x <2 and 0 <y <4/3.