JP2000315739A - Manufacture of nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a malfunction of a split gate type EEPROM(Electrically Erasable and Programmable Readout Memory) from being generated and to prolong the life of the EEPROM. SOLUTION: A sidewall spacer 9 is formed on the side surface of a floating gate 7. Therefore, at the time of forming a tunnel oxide film 13, the side surface of the gate 7 is prevented from being oxidized. Even though the spacer 9 itself is oxidized and is retreated (from broken lines to the position being shown by the full line in the diagram), the side surface of the gate 7 itself is protected with the spacer 9. Hereby, the distance between a control gate 12 and the acute part 7a of the gate 7 can be shortened and an FN(Fowler-Nordheim) tunnel current becomes easy to flow. As the result, a malfunction of an EEPROM is prevented from being generated and moreover, the life of the EEPROM is also prolonged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device. More specifically, the present invention relates to a technique for preventing a malfunction of a split gate type EEPROM and further extending the life of the device.

[0002]

2. Description of the Related Art With the expansion of application fields such as mobile phones and digital still cameras, electrically programmable and erasable read-only memory devices (EEPROMs)
rasable and programmable read only memory) is rapidly spreading. EE that can be erased electrically at once
The PROM is called a flash EEPROM.

An EEPROM stores binary or multi-valued digital information depending on whether a predetermined amount of charge is stored in a floating gate, and changes the conduction of a channel region in accordance with the amount of charge. , A non-volatile semiconductor storage device for reading digital information.

[0004] EEPROMs are classified into a stacked gate type and a split gate type. Among them, a split gate type EEPROM is disclosed, for example, in US Pat.
Nos. 130, 5045488, 5067108 and the like.

FIG. 5 shows a sectional structure of the split gate type EEPROM device. A drain region 102 and a source region 10 are formed on a P-type semiconductor substrate 101 at predetermined intervals.
3 are formed, and a channel region 104 is formed therebetween. On a region extending from a part of the channel region 104 to a part of the source region 103, a floating gate 106 is formed via a gate insulating film 105. And, on this floating gate 106,
A thick oxide film 107 (hereinafter, referred to as minilocos) formed by a selective oxidation method is provided.

[0008] A tunnel oxide film 108 is formed to cover the side surface of the floating gate 106 and a part of the minilocus 107. In addition, tunnel oxide film 1
A control gate 109 is formed on a portion of the drain region 102 from above the channel region 08 and a portion of the channel region 104.

The operation of this split gate type EEPROM device is as follows. First, when writing data, the control gate 109 and the source region 103
A predetermined voltage (for example, 2
V, 12 V) is applied to the source region 103 and a current flows through the channel region 104 to inject and store channel hot electrons (CHE) into the floating gate 106.

On the other hand, when erasing data, the drain region 102 and the source region 103 are grounded, and a predetermined voltage (for example, 15 V) is applied to the control gate 109 so that the electrons accumulated in the floating gate 106 are erased. Fowler-Nordheim tunnel current (Fo
wler-Nordheim tunneling current, hereinafter referred to as FN current. ), The control gate 109 is pulled out.

At this time, since the sharp edge 106a is provided at the upper edge of the floating gate 106, electric field concentration occurs in this portion, and an FN tunnel current flows at a lower voltage, thereby performing an efficient erase operation. ing.

[0010]

FIG. 6 is a partially enlarged view of FIG. After forming the floating gate 106 and the minilocus 107, a tunnel oxide film 108 is formed. At this time, the end of the floating gate 106 is also oxidized at the same time,
End recedes toward the center of the floating gate 106.

Therefore, tunnel oxide film 10 between control gate 109 and floating gate 106 is formed.
8 becomes substantially thicker and the distance L between them becomes longer, so that the FN tunnel current hardly flows.

As a result, data stored in the floating gate 106 cannot be erased, and a malfunction may occur. In addition, the life of the EEPROM device is shortened.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to prevent a malfunction of a split gate type EEPROM and extend the life of the device.

[0014]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device for erasing data by flowing charges accumulated in a floating gate to a control gate through a tunnel oxide film. Forming a floating gate on a substrate, forming a sidewall spacer covering at least a side surface of the floating gate, and forming a tunnel oxide film covering a part of a side surface and an upper surface of the floating gate. And forming a control gate extending over a part of the channel region by covering a part of the side surface and the upper surface of the floating gate through the tunnel oxide film.

Referring to FIG. 1, since the sidewall spacers 9 are formed on the side surfaces of the floating gate 7, the side surfaces of the floating gate 7 are prevented from being oxidized when the tunnel oxide film 13 is formed. Even if the sidewall spacer 9 itself is oxidized and receded (from a broken line to a position shown by a solid line in the figure), the side surface of the floating gate 7 itself is protected.

As a result, the distance L between the control gate and the sharp portion 7a of the floating gate can be reduced, and the FN tunnel current can easily flow.
The malfunction of the OM device is prevented, and the service life is prolonged.

[0017]

Next, an embodiment of a method of manufacturing a nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS.

As shown in FIG. 2A, a P-type single crystal silicon substrate 1 is formed on a P-type single crystal silicon
A gate oxide film 2 of 0 ° is formed, and then a polysilicon film 3 of about 1500 ° is deposited by using a low pressure CVD method. Then, phosphorus is ion-implanted into the polysilicon film 3 to lower the resistance. The suitable ion implantation conditions at this time are an acceleration energy of 25 KeV and a dose of 2.5 × 10 ¹⁴ cm ^−2.
It is.

Further, the pressure is reduced to about 1000 using a low pressure CVD method.
The silicon nitride film 4 is formed, and the silicon nitride film 4
Is selectively etched to form an opening 5.

Next, as shown in FIG. 2B, the LOCOS to be thermally oxidized is used by using the silicon nitride film 4 as an oxidation-resistant mask.
An SiO2 film 6 (hereinafter, referred to as minilocus) is formed on the polysilicon film 3 by a (Local Oxidation Of Silicon) method.

Then, as shown in FIG. 2C, the silicon nitride film 4 is removed by hot phosphoric acid, and the polysilicon film 3 is anisotropically etched using the minilocos 6 as a mask to form a floating gate 7. . At this time, since the bird's beak 6a is formed on the minilocos 6, a sharp portion 7a is formed on the upper edge of the floating gate 7 along the bird's beak 6a.

Thereafter, the gate oxide film 2 damaged by the anisotropic etching may be etched with a hydrofluoric acid-based etchant so that the gate oxide film 2 remains only under the floating gate 7.

Next, as shown in FIG.
A polysilicon film 8 of about 300.degree. Further, the polysilicon film 8 may be doped with phosphorus to reduce the resistance.

Then, as shown in FIG. 3B, the polysilicon film 8 was completely anisotropically etched, so that the side surface of the floating gate 7 was electrically connected to the floating gate 7. The sidewall spacer 9 is formed.

At this time, the conditions of the completely anisotropic etching use a mixed gas of Cl 2, HBr, and O 2, and the respective flow rates are 25 sccm, 40 sccm, and 5 sccm, and the power is suitably 30 W.

Thereafter, a process for forming a tunnel oxide film is performed. First, a second gate oxidation is performed to form a thin oxide film 10 of about 70 °. At this time, in the conventional example, the side surface of the floating gate 7 has receded, but in the present embodiment, the oxidation of the side surface of the floating gate 7 is prevented because the sidewall spacer 9 is formed.

Then, as shown in FIG.
A high-temperature oxide film 11 (hereinafter, referred to as an HTO film) of about 150 ° to 160 ° is deposited on the entire surface by the VD method. This H
The formation of the TO film 11 is performed in an oxidizing atmosphere at about 700 ° C. to 800 ° C. Thereafter, in order to improve the quality of the HTO film 11, third gate oxidation may be performed.

Next, as shown in FIG.
A polysilicon film is deposited on the entire surface by the method D, and the polysilicon film and the HTO film 11 are selectively etched to form a control gate 12 and a tunnel oxide film 13.

A tunnel oxide film 13 covering the side surface of the floating gate 7 and a part on the minilocos 6 is formed. Further, control gate 12 is formed on tunnel oxide film 13 and substrate 1. In this embodiment, the side wall spacer 9 is provided on the side surface of the floating gate 7.
Remains, the distance L between the sharp portion 7a of the floating gate 7 and the control gate 12 is shorter than in the conventional example, and FN tunneling is likely to occur.

Then, as shown in FIG. 4B, an n-type impurity such as phosphorus or arsenic is ion-implanted by ion implantation using the floating gate 7 and the control gate 12 as a mask, and thermally diffused. A drain region 14 and a source region 15 are formed. The source region is deeply diffused in order to increase the coupling capacitance ratio with the floating gate 7. Thus, while channel hot electron injection is performed efficiently, the potential difference between the control gate 12 and the floating gate 7 is increased even in the erase mode, so that FN tunneling is easily caused.

[0031]

As described above, according to the present invention,
Since the sidewall spacer is formed on the side surface of the floating gate, the side surface of the floating gate is prevented from being oxidized when the tunnel oxide film is formed. Even if the sidewall spacer itself is oxidized and receded, the side surface of the floating gate is protected.

As a result, the distance L between the control gate and the floating gate can be reduced, and the FN flowing from the floating gate to the control gate during data erasure of the split gate type EEPROM is reduced.
As a result of the tunnel current flowing more easily, the malfunction of the EEPROM device is prevented, and the life of the EEPROM device is further increased.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a sectional view illustrating an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 4 is a sectional view illustrating an embodiment of the present invention.

FIG. 5 shows a conventional split gate type EEPROM.
It is sectional drawing of an apparatus.

FIG. 6 shows a conventional split gate type EEPROM.
It is sectional drawing of an apparatus.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takumi Horie 3000 Chiya Ko, Ojiya-city, Niigata Prefecture F-term in Niigata Sanyo Electric Co., Ltd. 5F001 AA09 AA21 AA22 AA25 AA63 AB03 AB09 AC02 AC06 AC20 AD12 AD16 AD41 AD51 AD52 AF07 AG10 AG12 AG21 AG29 5F083 EP15 EP25 ER02 ER09 ER14 ER17 ER22 GA11 GA21 NA02 PR03 PR05 PR21 PR36

Claims (3)

[Claims] In a method of manufacturing a nonvolatile semiconductor memory device for erasing data by flowing charges accumulated in a floating gate to a control gate through a tunnel oxide film, a floating gate is formed on a semiconductor substrate. A step of forming a sidewall spacer covering at least a side surface of the floating gate; a step of forming a tunnel oxide film covering a part of a side surface and an upper surface of the floating gate; and Forming a control gate that covers a part of the side surface and the upper surface of the floating gate and extends over a part of the channel region. 2. A method of manufacturing a nonvolatile semiconductor memory device for erasing data by flowing charges accumulated in a floating gate to a control gate through a tunnel oxide film, wherein the charges accumulated in the floating gate are tunneled. In a method for manufacturing a nonvolatile semiconductor memory device for erasing data by flowing to a control gate through an oxide film, a step of forming a floating gate on a semiconductor substrate; and covering at least a side surface of the floating gate; A step of forming a sidewall spacer electrically connected to the floating gate; a step of forming a tunnel oxide film covering a part of a side surface and an upper surface of the floating gate; a side surface of the floating gate through the tunnel oxide film And part of the top surface Forming a control gate extending over a portion of the channel region, wherein after forming the tunnel oxide film, the sidewall spacer is left on the side surface of the floating gate, and the side surface of the floating gate is oxidized. A method for manufacturing a nonvolatile semiconductor memory device, characterized in that it is prevented from being performed. 3. The nonvolatile semiconductor memory according to claim 1, wherein the floating gate is formed by etching using a minilocus as a mask, and has a sharp portion at an upper edge of the floating gate. Device manufacturing method.