JP2000310972A - Image displaying method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a constitution to display a video image more correctly by executing a plurality of steps for signal fall in a plurality of display elements and a driving device applying voltage with a different fall timing to each display element. SOLUTION: A row-wiring driving part is provided in every row-wiring line with a current source to apply a current while a brightness data (a pulse signal) is on and a switching circuit to switch to give a direct current bias potential (earth level) of current limited by a resistance of off-period or to give a direct current bias. A PWN generator gives first a direct current bias during a short period of a fall of the pulse signal and then an earth level bias of current-limited through a resistor. With this constitution a potential waveform applied to the row wiring falls very rapidly to a potential Vb and later falls gradually based on a time constant decided by a current limiting resistance and the floating capacitance component of wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image display method for displaying an image by driving a plurality of display elements.

[0002]

2. Description of the Related Art In recent years, research and development of thin and large screen display devices have been actively conducted. The present inventor has been conducting research using a cold cathode as an electron source as a thin large-screen display device.

Conventionally, two types of electron-emitting devices, a hot cathode device and a cold cathode device, are known. Among them, as the cold cathode device, for example, a surface conduction type emission device, a field emission type device (hereinafter referred to as FE type), a metal / insulating layer / metal type emission device (hereinafter referred to as MIM type), and the like are known. .

[0004] As the surface conduction type emission element, for example, M.
I. Elinson, Radio E-ng. Electron Phys., 10, 1290,
(1965) and other examples described later.

[0005] The surface conduction electron-emitting device utilizes a phenomenon in which electron emission occurs when a current flows in a small-area thin film formed on a substrate in parallel with the film surface. Examples of the surface conduction electron-emitting device include a device using an SnO2 thin film by Elinson et al., And a device using an Au thin film [G. Dittmer: “Thin Solid Films”, 9,317 (1)
972)] and those based on In2O3 / SnO2 thin films [M. Hart
well and CG Fonstad: "IEEE Trans. ED Conf."
519 (1975)] and those using carbon thin films [Hisashi Araki
Others: Vacuum, Vol. 26, No. 1, 22 (1983)].

As a typical example of the device configuration of these surface conduction electron-emitting devices, FIG. 19 is a plan view of the device by M. Hartwell et al. Described above. In the figure, reference numeral 3001 denotes a substrate, and reference numeral 3004 denotes a conductive thin film made of a metal oxide formed by sputtering. Conductive thin film 3
004 is formed in an H-shaped planar shape as shown. By subjecting the conductive thin film 3004 to an energization process called energization forming, which will be described later,
005 are formed. The interval L in the figure is 0.5 to 1 [m
m] and the width W are set to 0.1 [mm]. still,
For convenience of illustration, the electron emitting portion 3005 is formed of the conductive thin film 30.
Although a rectangular shape is shown in the center of 04, this is a schematic one and does not exactly represent the actual position or shape of the electron-emitting portion.

In the above-described surface conduction electron-emitting device, such as the device by M. Hartwell et al., Before the electron emission, an electron emission portion 3005 is formed by subjecting the conductive thin film 3004 to an energization process called energization forming. Was common. That is, energization forming is
An electron-emitting portion is formed by energization. For example, a constant DC voltage or a DC voltage that increases at a very slow rate of, for example, about 1 V / min is applied to both ends of the conductive thin film 3004 and energized. And the conductive thin film 30
04 is locally destroyed or deformed or altered,
This is to form the electron-emitting portion 3005 in a state of being electrically high in resistance. Note that a crack is generated in a part of the conductive thin film 3004 that is locally broken, deformed, or altered.
When an appropriate voltage is applied to the conductive thin film 3004 after the energization forming, electron emission is performed in the vicinity of the crack.

The above-mentioned surface conduction electron-emitting device has an advantage that a large number of devices can be formed over a large area because of its simple structure and easy manufacture. Therefore, as disclosed in, for example, Japanese Patent Application Laid-Open No. 64-31332 by the present applicant, a method for arranging and driving a large number of elements has been studied.

As an example of the FE type, for example, WP Dyke
& WW Dolan, “Field emission”, Advance in Ele
ctron Physics, 8, 89 (1956) or CA Spind
t, “Physical properties of thin-film field emissi
on cathodes with molybdeniumcones ”, J. Appl. Phy
s., 47, 5248 (1976).

As a typical example of this FE type device configuration, FIG. 20 shows a cross-sectional view of the device by CA Spindt et al. Described above. In the figure, 3010 is a substrate, 3011 is an emitter wiring made of a conductive material, 3012 is an emitter cone, 3013 is an insulating layer, and 3014 is a gate electrode. This device comprises an emitter cone 3012 and a gate electrode 3
By applying an appropriate voltage during 014, field emission is caused from the tip of the emitter cone 3012. As another element configuration of the FE type, FIG.
There is also an example in which an emitter and a gate electrode are arranged on a substrate almost in parallel with the substrate plane instead of the laminated structure as described above.

Examples of the MIM type include, for example, C.I.
A. Mead, “Operation of tunnel-emission Devices,
J. Appl. Phys., 32,646 (1961) and the like are known.
FIG. 21 shows a typical example of the MIM type element configuration.
The figure is a cross-sectional view, in which 3020 is a substrate,
3021 is a lower electrode made of metal, 3022 is a thickness of 100
[Å] a thin insulating layer, 3023 has a thickness of 80 to 300
This is an upper electrode made of a metal of about [Å]. In the MIM type, electrons are emitted from the surface of the upper electrode 3023 by applying an appropriate voltage between the upper electrode 3023 and the lower electrode 3021.

The above-described cold cathode device can obtain electrons at a lower temperature than the hot cathode device, and therefore does not require a heater for heating. Therefore, the structure is simpler than that of the hot cathode element, and a fine element can be produced. Further, even when a large number of elements are arranged on a substrate at a high density, problems such as thermal melting of the substrate hardly occur. Also, unlike the response speed is slow because the hot cathode element operates by heating the heater,
In the case of a cold cathode device, there is also an advantage that the response speed is high. For this reason, research for applying the cold cathode device has been actively conducted.

For example, the surface conduction electron-emitting device has the advantage of being able to form a large number of devices over a large area because it has a particularly simple structure and is easy to manufacture among the cold cathode devices. Therefore, for example, Japanese Patent Application Laid-Open No.
As disclosed in Japanese Patent Publication No. 32, a method for arranging and driving a large number of elements has been studied.

With respect to applications of the surface conduction electron-emitting device, for example, image forming apparatuses such as image display apparatuses and image recording apparatuses, and charged beam sources have been studied.

In particular, as an application to an image display device, for example, US Pat. No. 5,066,883, JP-A-2-257551 and JP-A-4-28137 by the present applicant.
As disclosed in Japanese Patent Application Laid-Open Publication No. H10-115, an image display device using a combination of a surface conduction electron-emitting device and a phosphor that emits light by irradiation with electrons has been studied. An image display device using a combination of a surface conduction electron-emitting device and a phosphor is expected to have better characteristics than other conventional image display devices. For example, compared to a liquid crystal display device that has become widespread in recent years, it can be said that it is excellent in that it is a self-luminous type and does not require a backlight and has a wide viewing angle.

A method of arranging and driving a large number of FE elements is disclosed in, for example, US Pat.
No. 895. Further, as an example of applying the FE type to an image display device, for example, a flat panel display device reported by R. Meyer et al. Is known. [R. Meyer: “Re
cent Development on Microtips Display at LETI ”, T
ech.Digest of 4th Int.Vacuum Microelectronics Co
nf., Nagahama, pp. 6-9 (1991)].

An example in which a number of MIM types are arranged and applied to an image display device is disclosed in, for example, Japanese Patent Application Laid-Open No.
No. 5738.

The inventors of the present application have attempted surface conduction type emission devices having various materials, manufacturing methods and structures, including those described in the above-mentioned prior art. Further, research has been conducted on a multi-electron source in which a large number of surface conduction electron-emitting devices are arranged, and on an image display device using the multi-electron source. For example, a multi-electron source based on the electrical wiring method shown in FIG. 22 has been tried. That is, the surface conduction type emission device is
This is a multi-electron source in which a large number of elements are arranged in a dimension, and these elements are wired in a matrix as shown in the figure.

In the figure, 4001 schematically shows a surface conduction electron-emitting device, 4002 shows a row direction wiring, and 4003 shows a column direction wiring. Although the row direction wiring 4002 and the column direction wiring 4003 actually have a finite electric resistance, they are shown as wiring resistances 4004 and 4005 in the figure. The above-described wiring method is called simple matrix wiring. Although a 6 × 6 matrix is shown for convenience of illustration, the size of the matrix is not limited to this. For example, in the case of a multi-electron source for displaying images, a desired image is displayed. Only enough elements are arranged and wired.

In the multi-electron source in which the surface conduction electron-emitting devices are arranged in a simple matrix as described above, an appropriate electric signal is applied to the row wiring 4002 and the column wiring 4003 in order to output a desired electron beam. For example,
In order to drive any one row of surface conduction electron-emitting devices in the matrix, the selection potential Vs is applied to the row direction wiring 4002 of the selected row, and at the same time, the row direction wiring 40 of the non-selected row is applied.
02 is applied with a non-selection potential Vns. In synchronization with this, a driving potential Ve for outputting an electron beam is applied to the column wiring 4003. According to this method, the wiring resistance 400
If the voltage drops due to 4 and 4005 are ignored, a voltage of (Ve-Vs) is applied to the surface conduction type emission elements of the selected row, and (Ve-Vs) is applied to the surface conduction type emission elements of the non-selected rows.
Vns). Here, if Ve, Vs, and Vns are set to potentials of appropriate magnitudes, an electron beam having a desired intensity should be output only from the surface conduction electron-emitting device in the selected row, and each of the column-directional wirings should be output. Different drive potential Ve
Is applied, each of the elements in the selected row should output an electron beam having a different intensity. In addition, since the response speed of the surface conduction electron-emitting device is high, the driving potential Ve
By changing the length of time during which the electron beam is applied, it is possible to change the length of time during which the electron beam is output.

Hereinafter, the element applied voltage at the time of selection (Ve-Vs)
Is called Vf.

Further, as another method for obtaining an electron beam from a multi-electron source having a simple matrix wiring as described above, a driving current is supplied instead of connecting a voltage source for applying a driving potential Ve to a column wiring. And a selection potential Vs is applied to the row direction wiring of the row to be selected.
, And at the same time, driving by applying a non-selection potential Vns to the row direction wiring of the non-selected row. Thus, due to the strong threshold characteristics of the surface conduction electron-emitting device, an electron beam can be obtained only from the device in the selected row. Here, the current flowing through the electron source is hereinafter referred to as an element current If,
The emitted electron beam current is called emission current Ie.

Therefore, a multi-electron source having a surface conduction type electron-emitting device arranged in a simple matrix has various applications. For example, if an electric signal corresponding to image information is appropriately applied, the multi-electron source can be used as an electron source for an image display device. It can be suitably used.

[0024]

SUMMARY OF THE INVENTION It is an object of the present invention to realize a configuration capable of displaying an image more accurately.

[0025]

One of the inventions of the image display device according to the present invention has the following configuration.

An image display apparatus comprising: a plurality of display elements; and a drive circuit for applying signals having different fall timings to each of the display elements, wherein the drive circuit determines the fall of the signal by a plurality of steps. An image display device characterized in that the image display is performed separately.

One of the inventions of the image display device according to the present invention has the following configuration.

An image display apparatus comprising: a plurality of display elements; and a drive circuit for applying signals having different falling timings to each of the display elements, wherein the drive circuit performs non-display from a predetermined display state level. An image characterized by changing an operation state of a signal fall circuit from a predetermined level in the display state to a predetermined level in a non-display state when the signal falls to a predetermined level in a state. Display device.

The signal level is, for example, the magnitude of the potential of a signal supplied to an element or a wiring to which the element is connected.

One of the inventions of the image display device according to the present invention has the following configuration.

An image display apparatus comprising: a plurality of display elements; and a drive circuit for applying signals having different falling timings to each of the display elements, wherein the drive circuit determines a level of the signal to a predetermined display state. And a plurality of charge paths for approaching a predetermined level in the non-display state from the predetermined level in the non-display state when the signal falls. An image display device, wherein operating states of the plurality of charge paths are changed.

Here, the charge path may have various controllable configurations. For example, by using a voltage source (which may be GND) that gives a predetermined potential, the charge is quickly moved from a certain potential, which is a signal level in a display state, to a predetermined potential given by the voltage source, for example. , The signal level can be quickly brought closer to the signal level in the non-display state. In addition, by using a current source that can flow a predetermined current, charges can be moved at a desired speed, and the signal level can be made to approach the non-display state signal level at a desired speed.

Also, the combination of a plurality of charge paths can have various configurations. For example, charge paths (eg, the voltage source and the current source) having different amounts of change in the signal level per unit time when the signal level falls can be used. In this case, a plurality of charge paths may be operated exclusively. Further, the fall of the signal level may be controlled by using a plurality of charge paths that can operate in parallel and controlling the number of charge paths that operate in parallel. The control of the plurality of charge paths arranged in parallel may be controlled so that they operate at different timings, and each of the plurality of charge paths may be turned on.
A configuration may be used in which a circuit having a threshold value for transition between the state and the OFF state is used, the threshold value is changed for each of the plurality of charge paths, and the number of charge paths that operate in parallel automatically changes according to the signal level. .

Further, the change of the operation state of the plurality of charge paths is a change from a predetermined level of the display state to a threshold level at which the display element operates or a level at which display luminance by the display element becomes substantially zero. The time when the level of the signal changes to the level of 1 from the first level is
A configuration may be adopted in which the signal level is changed to a reference level, which is a predetermined level in the non-display state, shorter than a time when the level of the signal changes. According to this configuration, when the signal level falls, the signal level can be quickly shifted to the non-display state (for example, the non-light emitting state), and then the signal level can be made closer to the reference level while suppressing the influence of crosstalk.

The change of the operation state of the plurality of charge paths is as follows.
It is preferable that the threshold value is changed at or near a threshold level at which the display element operates, or at or near a level at which display luminance of the display element becomes substantially zero.

It is preferable that a circuit for determining an operation state of the plurality of charge paths is provided. With this circuit, it is possible to determine whether or not to perform the above-described signal level fall control.

Further, particularly, the image display device has a wiring for supplying the signal to each of the plurality of display elements corresponding to each of the plurality of display elements, and the operating state of the plurality of charge paths May be a circuit that determines the operating states of the plurality of charge paths according to the level of a signal supplied to a wiring other than the wiring to which the charge path to be controlled is connected.

Further, the image display device has a wiring for supplying the signal to each of the plurality of display elements corresponding to each of the plurality of display elements, and the operation state of the plurality of charge paths is determined. The determining circuit may determine the operation states of the plurality of charge paths according to the level of a signal supplied to a wiring adjacent to a wiring to which the charge path to be controlled is connected.

[0039] The signal may be an image signal. Also,
The signal may be a pulse width modulated signal.

It is preferable that the driving circuit has a rising circuit for raising the level of the signal separately from a circuit for lowering the signal level. As the start-up circuit, for example, a current source or a voltage source can be used.

The plurality of display elements may be connected in a matrix by a plurality of scanning signal wirings and a plurality of modulation signal wirings intersecting the scanning signal wirings. In this configuration, the drive circuit only needs to be connected to the modulation signal wiring.

Further, it is preferable that a scanning circuit for applying a predetermined potential to a scanning signal wiring selected from a plurality of scanning signal wirings is connected to the scanning signal wiring. Here, the driving circuit is connected to the modulation signal wiring, and the driving circuit is configured to generate a potential difference from the predetermined potential applied to the scanning signal wiring selected by the scanning circuit.
A configuration for applying a potential for driving the display element may be employed.

Various elements can be used as the display element. For example, an electron-emitting device can be used. In this case, preferably, an image can be displayed by using a light emitter that emits light by the electrons emitted from the electron-emitting device. Further, an EL element can be used. As the electron-emitting device, an FE type, a MIM type, a surface conduction type, or the like can be used.

One of the image display methods according to the present invention has the following configuration.

An image display method for driving by applying signals with different falling timings to each of a plurality of display elements, wherein the falling of the signals is performed in a plurality of steps. .

One of the image display methods according to the present invention has the following configuration.

An image display method for driving by applying signals having different falling timings to each of a plurality of display elements, wherein the signal falls from a predetermined level in a display state to a predetermined level in a non-display state. And changing an operation state of a signal fall circuit from a predetermined level in the display state to a predetermined level in the non-display state.

One of the image display methods according to the present invention has the following configuration.

An image display method for driving by applying signals having different falling timings to each of a plurality of display elements, wherein the level of the signals is brought closer from a predetermined level in a display state to a predetermined level in a non-display state. A plurality of charge paths for changing the operation state of the plurality of charge paths from a predetermined level in the display state to a predetermined level in the non-display state when the signal falls. Image display method to be used.

[0050]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A desired beam output can be obtained by applying a drive voltage or a drive current to a display element and performing pulse width modulation. However, a finite length from the drive means to the multi-electron source is obtained. A method of applying a drive current to suppress ringing at the time of pulse application (rising) caused by resonance generated due to an inductance component of a wiring having a capacitance, a capacitance component between adjacent wirings, a stray capacitance component, or the like; When a drive voltage is applied, a method of limiting the current can be adopted. On the other hand, at the end of the pulse application (fall), switching means should be provided to apply a voltage bias having low impedance in order to quickly discharge the charge accumulated by the stray capacitance and shorten the fall time. Can be. By these means, each element can be driven while preventing the occurrence of ringing exceeding the rated value of the applied voltage of the multi-electron source.

However, another problem has occurred in the above configuration.

That is, as shown in FIG. 2, when a pulse signal having a different pulse width is applied between two (or more) adjacent wirings, a pulse having a longer width is caused by the capacitance between the wirings. A phenomenon occurs in which the signal level decreases due to the influence of the pulse signal that has fallen earlier, and the effective application amount decreases. Due to such a phenomenon, when the gradation is expressed by the pulse width, an error occurs in the gradation due to the influence of the adjacent wiring. In particular, when a large-screen panel is configured, there is a problem in that the capacitance between wirings increases, and this error in gradation characteristics increases.

Here, before specifically describing the first embodiment according to the present invention, a first reference example will be described.

(Reference Example 1) FIG. 1 is a block diagram showing a circuit configuration of an image display device of Reference Example 1, FIG. 3 is a diagram for explaining the effect of the circuit of FIG. 1, and FIG. FIG. 6 is a waveform chart showing signal timings of FIG.

In FIG. 1, reference numeral 11 denotes a display panel in which a plurality of surface conduction electron-emitting devices having device voltage-emission current characteristics described later are arranged in an m × n matrix. Reference numeral 1 denotes a video input signal terminal for inputting a video signal, 2 denotes an analog signal processing unit, and an A / D conversion unit 3 converts a video luminance signal into a predetermined number of gradations. Performs level clamping, amplitude level adjustment, and band limitation. Reference numeral 4 denotes a synchronization separation unit, which separates synchronization signals (horizontal and vertical synchronization signals, etc.) from an input video signal. Reference numeral 5 denotes a timing generation unit which inputs a synchronization signal output from the synchronization separation unit 4 and supplies necessary timing signals to the A / D unit 3 and various parts.

The A / D section 3 converts the video analog luminance signal into n serial digital signals per horizontal period and outputs the serial digital signals.
, And is converted to a parallel signal, sent to the one-line memory 7 and stored. Column wiring drive unit 10
A current source I1 for applying a current to the column wiring via the switch circuit 103 when an output pulse signal of a PWM generator 101, which will be described later, according to input luminance data is on, for each column wiring; When the data is off, the transistor 100 drives the column wiring with a current limited by the current source I2 through the switch circuit 103, and a PWM generator (PW) that outputs a signal of a pulse width proportional to the luminance data for switching on / off of the transistor 100 PWN GEN) 101. That is, the switch circuit 103 outputs a pulse signal (luminance data) from the PWM generator (PWN GEN) 101.
Is high level, the current from the current source I1 flows through the column wiring, and when the pulse signal goes low, the column wiring is connected to the transistor 100 side. Here, to protect the potential applied to the element from exceeding the rated value when the luminance data is at a high level, the potential applied to the column wiring is set to V
There is also a diode 102 for clipping to m. Note that the potential Vss connected to the current source I2 of the column wiring drive unit 10 may be at the ground level or about several volts. Vdd is substantially the same as the potential Ve in FIG.

The row wiring drive section 9 has a switch circuit 110 for selecting whether to apply a DC potential bias Vs to the row wiring or to ground the row wiring for each row of the display panel 11.
The connection of these switch circuits 110 is sequentially switched by an output signal from the vertical shift register 8 to sequentially display the display panel 1.
Each line of the display panel 11 is sequentially scanned and driven by applying the DC potential bias Vs to each row in order. The vertical shift register receives, for example, a horizontal synchronizing signal from the timing generator 5 and outputs a signal so as to sequentially switch and select a row wiring every time the horizontal synchronizing signal is input.

As shown in FIG. 3, when the pulse signal shown in FIG. 2 is turned off (falling), the effective voltage drop due to the stray capacitance between the adjacent column wirings is reduced. It is improved by applying current limiting.

Next, the operation of the circuit of FIG. 1 will be described with reference to FIG.

In FIG. 4, reference numeral 401 denotes an analog video signal input to the video signal input terminal 1; 402, an analog / digital conversion of the analog video signal; 2 shows digital data for each line input to the wiring drive unit 10. 4
03 is for one line, that is, n pulse width modulation circuits 10
1 shows a pulse width modulation signal output from the control unit 1. The pulse width of each pulse signal is a pulse width corresponding to the luminance of the digital luminance data. Reference numeral 404 denotes an output signal of the vertical shift register 8, and the row wiring is sequentially switched and selected each time a horizontal synchronizing signal is input. Reference numeral 405 denotes a potential applied to each row wiring, and the potential Vs is applied to the row wiring selected by the output signal of the vertical shift register 8.
Is applied.

In this example, the rise time of the pulse is delayed due to the drive by the current source I1, but, for example, the voltage source is driven up to a certain potential and then the current source is activated. Similar effects can be obtained even when the drive signal rise time is made steep.

[First Embodiment] A first embodiment of the present invention will be described in detail below.

FIG. 5 is a block diagram showing a circuit configuration of the image display device according to the first embodiment of the present invention. Portions common to FIG. 1 described above are denoted by the same reference numerals, and description thereof will be omitted.

The column wiring drive section 10a includes, for each column wiring, a current source I1 for applying a current when the luminance data (pulse signal) is on, and a DC current limited by a resistor 105 (r) when the luminance data (pulse signal) is off. Apply a bias potential (ground level)
Alternatively, a switch circuit 104 for switching whether to apply the DC bias Vb is provided. PWM generator (PWMGE
The N) 101 further applies the DC bias Vb in the first short period at the time of the fall of the pulse signal, and then applies the current-limited ground level bias via the resistor 105. Incidentally, when the current supply from the current source I1 is on, as a protection to prevent the potential applied to the column wiring from exceeding the rating, the applied potential is set to V by the diode 102.
The point of clipping to m is the same.

With such a configuration, the potential waveform applied to the column wiring rapidly falls to the potential Vb as shown in FIG. 6, and then has a time constant determined by the current limiting resistor 105 and the floating capacitance of the wiring. Fall slowly based on.
It can be seen from this effect that the decrease in the effective voltage due to crosstalk as shown in FIG. 2 is further reduced, and the decrease in the effective voltage is improved.

In the configuration of the first embodiment, the pulse signal does not fall in one step, but falls halfway when the pulse signal falls, and after the step, the pulse signal reaches the reference potential. By performing the step of lowering, crosstalk is suppressed. In particular, in the first half of the fall of the pulse signal, the light emission state can be quickly reduced to a low luminance state or a non-light emission state by rapidly falling. Here, it is particularly effective to have a configuration in which the voltage is quickly reduced to near the threshold voltage at which the element emits electrons in the first half of the fall of the pulse signal. In particular, in a display panel using a surface conduction electron-emitting device having a steep threshold characteristic in drive voltage-emission luminance (device emission current), which will be described later, even if the voltage width (Ve-Vb) of sharply falling is small, In terms of the displayed luminance, it can sufficiently follow.

The operation of the circuit of FIG. 5 is the same as that of the timing chart of FIG.

<Method of Manufacturing and Application of Surface Conduction Emission Element Used in Embodiment of the Present Invention> FIG. 7 is an external perspective view of a display panel 1000 of the present embodiment, which is shown to show the internal structure thereof. The panel 1000 is partially cut away.

In the figure, 1005 is a rear plate, 1006
Is a side wall, 1007 is a face plate, 1005
1007 form an airtight container for maintaining the inside of the display panel at a vacuum. When assembling this hermetic container, it is necessary to seal the joints of each member to maintain sufficient strength and airtightness.For example, frit glass is applied to the joints, and in the air or in a nitrogen atmosphere, Sealing was achieved by baking at 400 ° C. to 500 ° C. for 10 minutes or more. A method of evacuating the inside of the airtight container to a vacuum will be described later.

The rear plate 1005 has a substrate 1001
Are fixed, but N × M surface-conduction emission devices 1002 are formed on the substrate 1001 (where N and M are positive integers of 2 or more, and the desired number of display pixels) For example, in a display device for displaying high-definition television, N = 300.
It is desirable to set 0, M = 1000 or more.
In the present embodiment, N = 3072, M = 1024
And). The N × M surface conduction electron-emitting devices 1002
Are M row-directional wirings 1003 and N column-directional wirings 10
04 is a simple matrix wiring. 100
The portion constituted by 1 to 1004 is called a multi-electron source. The manufacturing method and structure of the multi-electron source will be described later in detail.

In this embodiment, the substrate 1001 of the multi-electron source is fixed to the rear plate 1005 of the hermetic container. However, when the substrate 1001 of the multi-electron source has a sufficient strength, The substrate 1001 of the multi-electron source may be used as the rear plate of the airtight container.

On the lower surface of the face plate 1007, a fluorescent film 1008 is formed. Since the display panel 1000 of this embodiment is for color display, phosphors of three primary colors of red (R), green (G), and blue (B) used in the field of CRT are provided on the fluorescent film 1008. It is painted separately. The phosphor of each color is separately applied in a stripe shape as shown in FIG. 8A, for example, and a black conductor 1010 is provided between the stripes of the phosphor of each color. The purpose of providing the black conductor 1010 is to prevent the display color from being shifted even if the electron irradiation position is slightly shifted, or to prevent the reflection of external light to prevent the reduction of the display contrast. This is to prevent charge-up of the fluorescent film by electrons. Although graphite is used as a main component for the black conductor 1010, any other material may be used as long as it is suitable for the above purpose.

FIG. 8 shows how to paint the three primary color phosphors.
The arrangement is not limited to the stripe arrangement shown in FIG. 8A, but may be, for example, a delta arrangement as shown in FIG. 8B or another arrangement. Note that when a monochrome display panel is manufactured, a single-color phosphor material may be used for the phosphor film 1008, and a black conductive material is not necessarily used.

A metal back 1009 known in the field of CRT is provided on the surface of the fluorescent film 1008 on the rear plate side.
Is provided. The purpose of providing the metal back 1009 is to improve the light utilization rate by mirror-reflecting a part of the light emitted from the fluorescent film 1008 so that the fluorescent film 1
008, to act as an electrode for applying an electron accelerating potential, and to make the fluorescent film 1008 act as a conductive path for excited electrons. The metal back 1009 was formed by forming a fluorescent film 1008 on the face plate substrate 1007, smoothing the surface of the fluorescent film, and vacuum-depositing aluminum thereon. Note that when a fluorescent material for low voltage is used for the fluorescent film 1008, the metal back 1009 is not used.

Although not used in the present embodiment,
For the purpose of applying acceleration potential and improving the conductivity of the fluorescent film,
A transparent electrode made of, for example, ITO may be provided between the face plate substrate 1007 and the fluorescent film 1008.

Dx1 to DxM, Dy1 to DyN, and Hv are electric connection terminals having an airtight structure provided for electrically connecting the display panel 1000 to an electric circuit (not shown). Dx1 to DxM are the row direction wirings 1 of the multi-electron source
003 and Dy1 to DyN are the column wirings 10 of the multi-electron source.
04 and Hv are the metal back 100 of the face plate
9, respectively.

To evacuate the inside of the hermetic container to a vacuum, after assembling the hermetic container, an exhaust pipe (not shown) and a vacuum pump are connected, and the inside of the hermetic container is set to about 10 −7 [torr]. Evacuate to a vacuum. After that, the exhaust pipe is sealed,
In order to maintain the degree of vacuum in the airtight container, a getter film (not shown) is formed at a predetermined position in the airtight container immediately before or after sealing. The getter film is, for example, a film formed by heating and depositing a getter material containing Ba as a main component by a heater or high-frequency heating. × 10
The degree of vacuum is maintained at a power of −7 torr.

The display panel 1 according to the embodiment of the present invention has been described above.
000 has been described.

Next, the display panel 100 of this embodiment
A method for manufacturing the multi-electron source used for the first embodiment will be described.
The multi-electron source used for the image display device of the present embodiment is
There is no limitation on the material, shape, or manufacturing method of the surface conduction electron-emitting device as long as it is an electron source in which the surface conduction electron-emitting devices are arranged in a simple matrix. Therefore, for example, a cold cathode device such as a surface conduction type emission device, an FE type, or an MIM type can be used. However, the present inventors have found that among the surface conduction electron-emitting devices, those in which the electron-emitting portion or its peripheral portion is formed of a fine particle film have excellent electron-emitting characteristics and can be easily manufactured. Therefore,
It can be said that it is most suitable for use in a multi-electron source of a high-brightness, large-screen image display device. Therefore, in the display panel of the above embodiment, a surface conduction electron-emitting device in which the electron-emitting portion or its peripheral portion is formed of a fine particle film is used. Therefore, the basic structure, manufacturing method and characteristics of a suitable surface conduction electron-emitting device will be described first, and then the structure of a multi-electron source in which a large number of devices are arranged in a simple matrix will be described.

(Suitable Device Configuration and Manufacturing Method of Surface Conduction Emission Device) Representative configurations of a surface conduction electron-emitting device in which an electron-emitting portion or its peripheral portion is formed of a fine particle film include a flat type and a vertical type. Kinds are given.

(Planar surface conduction electron-emitting device) First, the structure and manufacturing method of a flat surface conduction electron-emitting device will be described. FIG. 9 shows a plan view (A) and a cross-sectional view (B) for describing the configuration of a planar surface conduction electron-emitting device. In the figure, 1101 is a substrate, 1102 and 1
103, a device electrode; 1104, a conductive thin film; 1105, an electron-emitting portion formed by an energization forming process;
Reference numeral 13 denotes a thin film formed by the activation process.

As the substrate 1101, for example, various glass substrates such as quartz glass and blue plate glass, various ceramics substrates such as alumina, or an insulating layer made of, for example, SiO 2 is formed on the various substrates described above. A stacked substrate or the like can be used.

The device electrodes 1102 and 1103 provided on the substrate 1101 so as to be opposed to the substrate surface in parallel are formed of a conductive material. For example, N
i, Cr, Au, Mo, W, Pt, Ti, Cu, Pd,
Materials may be appropriately selected and used from metals such as Ag and the like, alloys of these metals, metal oxides such as In 2 O 3 —SnO 2, and semiconductors such as polysilicon. The electrodes can be easily formed by using a combination of a film forming technique such as vacuum evaporation and a patterning technique such as photolithography and etching. However, the electrodes can be formed using other methods (for example, printing techniques). I can't wait.

The shapes of the device electrodes 1102 and 1103 are appropriately designed according to the application purpose of the electron-emitting device.
Generally, the electrode interval L is usually designed by selecting an appropriate numerical value from the range of several hundreds of squares to several hundreds of μm.
m. Further, regarding the thickness d of the device electrode,
Usually, an appropriate numerical value is selected from the range of several hundred [Å] to several μm.

Further, a fine particle film is used for the portion of the conductive thin film 1104. The fine particle film described here refers to a film including a large number of fine particles as constituent elements (including an island-shaped aggregate). When the fine particle film is examined microscopically, usually, a structure in which the individual fine particles are spaced apart from each other, a structure in which the fine particles are adjacent to each other, or a structure in which the fine particles overlap each other is observed.

The particle size of the fine particles used in the fine particle film is in the range of several to several thousand 、, but preferably in the range of 10 [Å] to 200 [Å]. Further, the thickness of the fine particle film is appropriately set in consideration of various conditions described below. That is, the device electrode 1102
Or conditions necessary for good electrical connection with 1103, conditions necessary for good energization forming described later, conditions necessary for setting the electrical resistance of the fine particle film itself to an appropriate value described later. , And so on. Specifically, it is set in the range of several to several thousand, but the most preferable is between 10 [500] and 500 [$].

Materials that can be used to form the fine particle film include, for example, Pd, Pt, Ru, Ag,
Au, Ti, In, Cu, Cr, Fe, Zn, Sn, T
a, W, Pb and other metals, PdO, Sn
Oxides such as O2, In2O3, PbO, Sb2O3 and the like, HfB2, ZrB2, LaB6, CeB6, Y
Borides such as B4, GdB4, etc., TiC, Z
Carbides such as rC, HfC, TaC, SiC, WC, etc .; nitrides such as TiN, ZrN, HfN, etc .; semiconductors such as Si, Ge, etc .; and carbon. Are appropriately selected from these.

As described above, the conductive thin film 1104 is formed of a fine particle film.
It was set so as to be included in the range of 10 3 to 10 7 [Ω / □].

The conductive thin film 1104 and the device electrode 11
Since it is desirable that the wires 02 and 1103 be electrically connected well, they have a structure in which a part of each overlaps. In the example of FIG. 9, the overlapping manner is such that the substrate, the device electrode, and the conductive thin film are stacked in this order from the bottom, but in some cases, the substrate, the conductive thin film, and the device electrode are stacked in this order from the bottom. I can't wait.

The electron-emitting portion 1105 is a crack-like portion formed in a part of the conductive thin film 1104, and has an electrically higher resistance than the surrounding conductive thin film. The crack is formed by performing a later-described energization forming process on the conductive thin film 1104.
Fine particles having a particle size of several to several hundreds of mm may be arranged in the crack. Since it is difficult to accurately and accurately show the actual position and shape of the electron-emitting portion, they are schematically shown in FIG.

The thin film 1113 is a thin film made of carbon or a carbon compound, and covers the electron emitting portion 1105 and its vicinity. The thin film 1113 is formed by performing an energization activation process described later after the energization forming process.

The thin film 1113 is made of any one of single crystal graphite, polycrystalline graphite, and amorphous carbon, or a mixture thereof, and has a thickness of 500 [Å] or less, but 300 [Å] or less. Is more preferred. Since it is difficult to accurately show the actual position and shape of the thin film 1113, it is schematically shown in FIG. FIG. 9A shows an element in which a part of the thin film 1113 is removed.

The basic configuration of the preferred element has been described above. In the embodiment, the following element is used.
That is, blue glass was used for the substrate 1101, and Ni thin films were used for the device electrodes 1102 and 1103. The thickness d of the device electrode was 1000 [Å], and the electrode interval L was 2 [μm].

Pd or P is used as the main material of the fine particle film.
The thickness of the fine particle film was about 100 [膜], and the width W was 100 [μm] using dO.

Next, a description will be given of a method of manufacturing a suitable planar surface conduction electron-emitting device. FIGS. 10A to 10D
Is a cross-sectional view for explaining the manufacturing process of the surface conduction electron-emitting device, and the notation of each member is the same as in FIGS. 9A and 9B.

(1) First, as shown in FIG.
Element electrodes 1102 and 1103 are formed over a substrate 1101. In forming these electrodes, the substrate 1101 is sufficiently washed in advance with a detergent, pure water, and an organic solvent, and then the material of the device electrode is deposited (for example, a deposition method such as a vapor deposition method or a sputtering method). Vacuum film forming technology may be used). Thereafter, the deposited electrode material is patterned by using a photolithography / etching technique, and a pair of device electrodes (1102 and 1102) shown in FIG.
Form 3).

(2) Next, a conductive thin film 1104 is formed as shown in FIG. This conductive thin film 1104
In forming (1), first, an organic metal solution is applied to the substrate (a), dried, heated and baked to form a fine particle film, and then patterned into a predetermined shape by photolithography and etching. Here, the organic metal solution is a solution of an organic metal compound containing, as a main element, a material of fine particles used for a conductive thin film (specifically, in this embodiment, Pd was used as a main element. In the embodiment, a dipping method is used as a coating method.
Other than that, for example, a spinner method or a spray method may be used).

As a method for forming a conductive thin film made of a fine particle film, a method other than the method of applying an organometallic solution used in the present embodiment, for example, a vacuum evaporation method, a sputtering method, or a chemical vapor deposition method In some cases, a deposition method or the like is used.

(3) Next, as shown in FIG. 9C, the forming electrodes 1110 and 1112 are supplied from the forming power supply 1110.
The electron emitting portion 1105 is formed by applying an appropriate voltage during the period 03 and performing the energization forming process.

This energization forming treatment is to energize the conductive thin film 1104 made of a fine particle film, to appropriately break, deform, or alter a part of the conductive thin film 1104 to obtain a structure suitable for emitting electrons. This is the process of changing.
A portion of the conductive thin film made of the fine particle film that has been changed to a structure suitable for emitting electrons (that is, the electron emitting portion 110
In 5), an appropriate crack is formed in the thin film.
Note that the electrical resistance measured between the device electrodes 1102 and 1103 is significantly increased after the formation of the electron emission portions 1105 as compared to before the formation.

FIG. 11 shows an example of an appropriate voltage waveform applied from the forming power supply 1110 in order to explain the energization method in more detail. When forming a conductive thin film made of a fine particle film, a pulse-like voltage is preferable. In the case of the present embodiment, a triangular wave pulse having a pulse width T1 is continuously generated at a pulse interval T2 as shown in FIG. Was applied. At that time, the peak value Vpf of the triangular wave pulse is
The pressure was increased sequentially. Also, monitor pulses Pm for monitoring the state of formation of the electron-emitting portion 1105 are inserted at appropriate intervals between the triangular-wave pulses, and the current flowing at that time is measured by the ammeter 1.
It was measured at 111.

In the embodiment, for example, in a vacuum atmosphere of about 10 −5 [torr], for example, the pulse width T1 is 1 [msec], the pulse interval T2 is 10 [msec], and the peak value Vpf is 1 [msec]. The voltage was increased by 0.1 [V] for each pulse. Then, each time five triangular waves were applied, the monitor pulse Pm was inserted at a rate of once. The monitor pulse voltage Vpm was set to 0.1 [V] so as not to adversely affect the forming process. The electrical resistance between the device electrodes 1102 and 1103 is 1 × 10 6
At the stage when the power became [Ω], that is, when the current measured by the ammeter 1111 at the time of application of the monitor pulse became 1 × 10 −7 or less [A], the energization related to the forming process was terminated.

The above method is a preferable method for the surface conduction electron-emitting device according to the present embodiment. For example, the design of the surface conduction electron-emitting device such as the material and film thickness of the fine particle film or the element electrode interval L is changed. In such a case, it is desirable to appropriately change the energization conditions accordingly.

(4) Next, as shown in FIG.
The device electrodes 1102 and 1103 are supplied from the activation power source 1112.
During the energization activation process, apply an appropriate voltage during
Improve electron emission characteristics. This energization activation process
This is a process of energizing the electron-emitting portion 1105 formed by the energization forming process under appropriate conditions to deposit carbon or a carbon compound in the vicinity thereof.
(In the figure, a deposit made of carbon or a carbon compound is schematically shown as a member 1113). Note that by performing the energization activation process, the emission current at the same applied voltage can be typically increased by 100 times or more compared to before the energization activation process.

More specifically, by periodically applying a voltage pulse in a vacuum atmosphere within the range of 10 −4 to 10 −5 [torr], the organic compound existing in the vacuum atmosphere is applied. Is deposited. The deposit 1113 is any one of single-crystal graphite, polycrystalline graphite, and amorphous carbon, or a mixture thereof, and has a thickness of 500 [Å] or less, more preferably 300 [Å] or less.

FIG. 12A shows an example of an appropriate voltage waveform applied from the activation power supply 1112 in order to explain the energization method in more detail. In the present embodiment, the energization activation process is performed by applying a rectangular wave of a constant voltage periodically, but specifically, the rectangular wave voltage Vac is 14
[V], pulse width T3 is 1 [msec], pulse interval T4
Was set to 10 [msec]. The above-described energization conditions are preferable conditions for the surface conduction electron-emitting device of the present embodiment, and when the design of the surface conduction electron-emitting device is changed,
It is desirable to change the conditions accordingly.

Reference numeral 1114 shown in FIG. 10D denotes an anode electrode for capturing the emission current Ie emitted from the surface conduction electron-emitting device. The anode electrode 1114 is connected to a DC high-voltage power supply 1115 and an ammeter 1116. (Note that the substrate 1101
When the activation process is performed after the display panel is incorporated in the display panel, the phosphor screen of the display panel is connected to the anode electrode 1114.
Used as). While the voltage is applied from the activation power supply 1112, the emission current Ie is measured by the ammeter 1116 to monitor the progress of the energization activation process, and the activation power supply 111
2 is controlled. An example of the emission current Ie measured by the ammeter 1116 is shown in FIG. Activation power supply 11
When the pulse voltage starts to be applied from 12, the emission current Ie increases with time, but eventually saturates and hardly increases. As described above, when the emission current Ie is substantially saturated, the application of the voltage from the activation power supply 1112 is stopped, and the energization activation process ends.

The above-mentioned energization conditions are preferable conditions for the surface conduction electron-emitting device of the present embodiment, and when the design of the surface conduction electron-emitting device is changed, the conditions should be changed accordingly. Is desirable.

As described above, the plane type surface conduction electron-emitting device shown in FIG. 10E was manufactured.

(Vertical Type Surface Conduction Emission Element) Next, another typical structure of a surface conduction type emission element in which the electron emission portion or its periphery is formed of a fine particle film, that is, a vertical type surface conduction type emission device. The configuration of the element will be described.

FIG. 13 is a schematic cross-sectional view for explaining the vertical basic structure of the present embodiment.
01 is a substrate, 1202 and 1203 are device electrodes, 1206
Denotes a step forming member, 1204 denotes a conductive thin film using a fine particle film, 1205 denotes an electron emitting portion formed by an energization forming process, and 1213 denotes a thin film formed by an energization activation process.

The difference between the vertical type and the flat type described above is that one of the device electrodes (1202) is provided on the step forming member 1206, and the conductive thin film 1204 is provided on the side surface of the step forming member 1206. It is in the point of coating. Therefore, the device electrode interval L in the planar type shown in FIG.
Is the step height L of the step forming member 1206 in the vertical type.
s. In addition, the substrate 1201, the element electrode 1
202 and 1203, conductive thin film 1 using fine particle film
204, the materials listed in the description of the planar type can be used in the same manner. For the step forming member 1206, an electrically insulating material such as SiO2 is used.

Next, a method of manufacturing a vertical surface conduction electron-emitting device will be described. FIGS. 14A to 14F are cross-sectional views for explaining a manufacturing process.
Is the same as

(1) First, as shown in FIG.
An element electrode 1203 is formed over a substrate 1201.

(2) Next, as shown in FIG. 13B, an insulating layer for forming a step forming member is laminated. The insulating layer may be formed by laminating, for example, SiO2 by a sputtering method. However, another film forming method such as a vacuum evaporation method or a printing method may be used.

3) Next, as shown in FIG. 13C, an element electrode 1202 is formed on the insulating layer.

4) Next, as shown in FIG. 14D, a part of the insulating layer is removed by using, for example, an etching method to expose the element electrode 1203.

5) Next, as shown in FIG. 11E, a conductive thin film 1204 using a fine particle film is formed. For the formation, as in the case of the flat type, a film forming technique such as a coating method may be used.

6) Next, similarly to the case of the above-mentioned flat type, the energization forming process is performed to form an electron emission portion (the same process as the flat type energization forming process described with reference to FIG. 10C). Just do it.)

(7) Next, as in the case of the flat type,
An energization activation process is performed to deposit carbon or a carbon compound in the vicinity of the electron emission portion (the same process as the planar energization activation process described with reference to FIG. 10D may be performed).

As described above, the vertical surface conduction electron-emitting device shown in FIG.

(Characteristics of Surface Conduction Emission Device Used in Display Device) The element structure and manufacturing method of the planar and vertical surface conduction electron-emitting devices have been described above. Next, the characteristics of the device used in the display device will be described. Is described.

FIG. 15 shows (emission current Ie) vs. (element applied voltage Vf) characteristics of the element used in the display device of the present embodiment.
And typical examples of (device current If) versus (device applied voltage Vf) characteristics. Note that the emission current Ie is significantly smaller than the device current If, and it is difficult to show the same current on the same scale. In addition, these characteristics are changed by changing design parameters such as the size and shape of the device. For,
The two graphs are shown in arbitrary units.

The device used in the display device has the following three characteristics with respect to the emission current Ie.

First, when a voltage higher than a certain voltage (hereinafter referred to as a threshold voltage Vth) is applied to the element, the emission current Ie sharply increases. On the other hand, when the voltage is lower than the threshold voltage Vth, the emission current Ie increases. Ie is hardly detected. That is, it is a non-linear element having a clear threshold voltage Vth with respect to the emission current Ie.

Secondly, since the emission current Ie changes depending on the voltage Vf applied to the element, the emission current Ie depends on the voltage Vf.
Size can be controlled.

Third, since the response speed of the current Ie emitted from the element is fast with respect to the voltage Vf applied to the element, the charge amount of the electrons emitted from the element depends on the length of time for applying the voltage Vf. Can control.

Because of the above characteristics, the surface conduction electron-emitting device could be suitably used for a display device. For example, in a display device in which a large number of elements are provided corresponding to pixels of a display screen, if the first characteristic is used, display can be performed by sequentially scanning the display screen. That is,
The driving element has a threshold voltage Vth according to a desired light emission luminance.
The above voltage is appropriately applied, and a voltage lower than the threshold voltage Vth is applied to the non-selected elements. By sequentially switching the elements to be driven, the display screen can be sequentially scanned and displayed.

Further, since the emission luminance can be controlled by using the second characteristic or the third characteristic, a gradation display can be performed.

(Structure of a Multi-Electron Source in which Many Devices are Wiring in a Simple Matrix) Next, the structure of a multi-electron source in which the above-mentioned surface conduction electron-emitting devices are arranged on a substrate and wired in a simple matrix will be described.

FIG. 16 shows the display panel 10 of FIG.
It is a top view of the multi-electron source used for 00. Substrate 100
1, surface-conduction emission type devices similar to those shown in FIG. 9 are arranged.
And the column-directional wiring electrodes 1004 are arranged in a simple matrix. An insulating layer (not shown) is formed between the row-directional wiring electrodes 1003 and the column-directional wiring electrodes 1004 where they intersect, so that electrical insulation is maintained.

FIG. 17 shows a cross section along the line AA ′ in FIG.

Incidentally, the multi-electron source having such a structure is as follows.
After previously forming a row direction wiring electrode 1003, a column direction wiring electrode 1004, an interelectrode insulating layer (not shown), and a device electrode and a conductive thin film of a surface conduction electron-emitting device on a substrate,
Row direction wiring electrode 1003 and column direction wiring electrode 1004
The device was manufactured by supplying power to each element through the device and performing an energization forming process and an energization activation process.

FIG. 18 shows a configuration in which image information provided from various image information sources such as television broadcasting can be displayed on a display panel using the surface conduction electron-emitting device described above as an electron source. It is a figure for showing an example of a multifunctional display. In the figure, 1000 is the display panel described above, 2101 is a driving circuit of the display panel, 2102 is a display panel controller, 2103 is a multiplexer,
2104 is a decoder, 2105 is an input / output interface circuit, 2106 is a CPU, 2107 is an image generation circuit,
2108, 2109 and 2110 are image memory interface circuits, 2111 is an image input interface circuit, 2112 and 2113 are TV signal receiving circuits, and 2114 is an input unit.

(Note that, when the present display device receives a signal containing both video information and audio information, such as a television signal, for example, it reproduces the audio simultaneously with the display of the video. Descriptions of circuits, speakers, and the like relating to reception, separation, reproduction, processing, storage, and the like of audio information that are not directly related to the characteristics of the present invention are omitted. go.

First, the TV signal receiving circuit 2113 is a circuit for receiving a TV image signal transmitted using a wireless transmission system such as radio waves or spatial optical communication. The format of the received TV signal is not particularly limited, and may be, for example, various systems such as the NTSC system, the PAL system, and the SECAM system. Further, a TV signal (for example, a so-called high-definition TV including the MUSE system) including a larger number of scanning lines than the above is a signal suitable for taking advantage of a display panel suitable for a large area and a large number of pixels. Source. The TV signal received by the TV signal receiving circuit 2113 is output to the decoder 2104.

The TV signal receiving circuit 2112 is a circuit for receiving a TV image signal transmitted using a wired transmission system such as a coaxial cable or an optical fiber. Similarly to the TV signal receiving circuit 2113, the system of the TV signal to be received is not particularly limited, and the TV signal received by this circuit is also output to the decoder 2104.

The image input interface circuit 21
Reference numeral 11 denotes a circuit for capturing an image signal supplied from an image input device such as a TV camera or an image reading scanner. The captured image signal is output to a decoder 2104.

The image memory interface circuit 2
110 is a video tape recorder (hereinafter abbreviated as VTR)
Is a circuit for capturing the image signal stored in the decoder 2104. The captured image signal is output to the decoder 2104.

The image memory interface circuit 2
Reference numeral 109 denotes a circuit for capturing an image signal stored in the video disk, and the captured image signal is output to the decoder 2104.

The image memory interface circuit 2
Reference numeral 108 denotes a circuit for taking in an image signal from a device that stores still image data, such as a so-called still image disk.
04 is output.

The input / output interface circuit 210
Reference numeral 5 denotes a circuit for connecting the present display device to an external computer, a computer network, or an output device such as a printer. In addition to inputting and outputting image data, character data, and graphic information, control signals and numerical data can be input and output between the CPU 2106 included in the display device and the outside in some cases. .

The image generation circuit 2107 is provided with image data and character / graphic information input from the outside via the input / output interface circuit 2105, or the CPU 21.
This is a circuit for generating display image data based on the image data and character / graphic information output from the controller 06. Within this circuit, for example, a rewritable memory for storing image data and character / graphic information, a read-only memory for storing image patterns corresponding to character codes, and a processor for performing image processing Circuits necessary for generating an image, such as those described above, are incorporated. The display image data generated by this circuit is
4, but it is also possible to input / output an external computer network or a printer via an input / output interface circuit 2105 in some cases.

The CPU 2106 mainly performs operations related to operation control of the display device and generation, selection, and editing of a display image.

For example, a control signal is output to the multiplexer 2103, and image signals to be displayed on the display panel are appropriately selected or combined. In this case, a control signal is generated for the display panel controller 2102 in accordance with an image signal to be displayed, and a display frequency, a scanning method (for example, interlaced or non-interlaced), and the number of scanning lines for one screen are displayed. The operation of the device is appropriately controlled.

Further, image data and character / graphic information are directly output to the image generation circuit 2107, or an external computer or memory is accessed through the input / output interface circuit 2105 to access the image data or character / graphic information. Enter

The CPU 2106 may, of course, be involved in operations for other purposes. For example,
It may be directly related to a function of generating and processing information, such as a personal computer or a word processor.

Alternatively, as described above, the computer may be connected to an external computer network via the input / output interface circuit 2105 to perform operations such as numerical calculations in cooperation with external devices.

The input unit 2114 is connected to the CPU 2106
The user inputs commands, programs, data, and the like. For example, in addition to a keyboard and a mouse, various input devices such as a joystick, a barcode reader, and a voice recognition device can be used.

The decoder 2104 is a circuit for inversely converting various image signals input from 2107 to 2113 into three primary color signals or a luminance signal and I and Q signals. It is to be noted that the decoder 2104 desirably includes an image memory therein, as indicated by a dotted line in FIG. This is for handling television signals that require an image memory when performing inverse conversion, such as the MUSE method. The provision of the image memory facilitates display of a still image, or facilitates image processing and editing including image thinning, interpolation, enlargement, reduction, and synthesis in cooperation with the image generation circuit 2107 and the CPU 2106. This is because the advantage of being able to do so is born.

The multiplexer 2103 has a CPU
A display image is appropriately selected based on a control signal input from 2106. That is, the multiplexer 21
A driving circuit 2 selects a desired image signal from among the inversely converted image signals input from the decoder 2104.
Output to 101. In that case, by switching and selecting an image signal within one screen display time, it is possible to divide one screen into a plurality of areas and display different images depending on the areas, as in a so-called multi-screen TV. .

The display panel controller 2102
Is based on a control signal input from the CPU 2106,
This is a circuit for controlling the operation of the driving circuit 2101.

First, as a signal related to the basic operation of the display panel, for example, a signal for controlling an operation sequence of a drive power source (not shown) for the display panel is output to the drive circuit 2101. In addition, a signal for controlling, for example, a screen display frequency and a scanning method (for example, interlaced or non-interlaced), which is related to the display panel driving method, is output to the driving circuit 2101.

In some cases, a control signal related to image quality adjustment such as luminance, contrast, color tone, and sharpness of a display image may be output to the drive circuit 2101.

The driving circuit 2101 is connected to the display panel 1.
000, which operates based on an image signal input from the multiplexer 2103 and a control signal input from the display panel controller 2102.

The function of each section has been described above. With the configuration illustrated in FIG. 18, in this display device, image information input from various image information sources can be displayed on the display panel 1000. That is, various image signals including television broadcasts are inversely converted by the decoder 2104, appropriately selected by the multiplexer 2103, and input to the drive circuit 2101. on the other hand,
The display controller 2102 generates a control signal for controlling the operation of the driving circuit 2101 according to an image signal to be displayed. The drive circuit 2101 applies a drive signal to the display panel 1000 based on the image signal and the control signal. Thus, an image is displayed on the display panel 1000. These series of operations are performed by the CPU 2106
Is generally controlled by the

In this display device, the decoder 2
An image memory built in the image processing circuit 104;
And the CPU 2106 involve not only displaying a selected one of a plurality of pieces of image information but also displaying, for example, enlargement, reduction, rotation, movement, edge emphasis, thinning, interpolation, It is also possible to perform image processing such as color conversion and image aspect ratio conversion, and image editing such as combining, deleting, connecting, replacing, and fitting. Although not particularly described in the description of the present embodiment, a dedicated circuit for processing and editing audio information may be provided as in the above-described image processing and image editing.

Therefore, the present display device is a television broadcast display device, a video conference terminal device, an image editing device that handles still and moving images, a computer terminal device, an office terminal device such as a word processor,
It can be equipped with the functions of a game machine etc. by one unit, and has a very wide application range for industrial or consumer use.

FIG. 18 shows only an example of the configuration of a display device using a display panel using a surface conduction electron-emitting device as an electron source, and it goes without saying that the present invention is not limited to this. No. For example, among the components in FIG. 18, circuits relating to functions that are unnecessary for the intended use may be omitted. Conversely, additional components may be added depending on the purpose of use. For example, when the present display device is applied to a video phone, a TV camera,
It is preferable to add a transmitting / receiving circuit including a voice microphone, a lighting device, and a modem to the components.

In the present display device, in particular, since the display panel using the surface conduction electron-emitting device as the electron source can be easily made thin, the depth of the entire display device can be reduced. In addition, the display panel using the surface conduction electron-emitting device as the electron source is easy to enlarge the screen, has high brightness, and has excellent viewing angle characteristics. It is possible to display.

Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine, a facsimile machine) comprising one device Etc.).

An object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and a computer (or CPU or MPU) of the system or the apparatus to supply the storage medium. This is also achieved by reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) Performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided on a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, The case where the CPU of the function expansion board or the function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing.

As described above, according to the present embodiment, in a display panel using (m × n) matrix-arranged surface-conduction emission devices driven by pulse width modulation, the cross between adjacent wirings It is possible to suppress a decrease in the effective applied voltage on the wiring that is selectively driven due to the talk, so that an image having good gradation characteristics can be displayed.

As described above, according to the present embodiment, it is possible to suppress the fluctuation of the signal level due to the stray capacitance between the adjacent wirings and display an image by faithfully reproducing a predetermined luminance. is there.

Further, according to the present embodiment, the fluctuation of the signal level on the signal line due to the fall of the signal of the adjacent signal line is minimized, so that the fluctuation of the luminance of the displayed image can be made inconspicuous. This has the effect.

[Second Embodiment] Next, a description will be given of a second embodiment in which the circuit configuration for falling the pulse signal used in the first embodiment of the present invention is modified. FIG. 23 shows the second embodiment, which is the same as FIG. 5 used in the first embodiment.
5 is a diagram showing a circuit of a part corresponding to a part corresponding to one column wiring in the column wiring driving unit 10a of FIG. Corresponding parts have the same reference characters allotted.

In FIG. 23, 23002 and 23003
Are transistors, which are controlled by the control unit 23001.

Next, the falling operation of the pulse signal in the second embodiment will be described.

When the controller 23001 detects that the pulse signal falls from the signal from the pulse width modulation signal generator (PWM GEN) 101, the transistor 2300
2 and 23003 are both turned on. As a result, the resistances rd and re are connected in parallel, and the column wiring potential quickly falls. Next, the control unit 23001 controls so that one transistor is turned on and the other is turned off after a predetermined time has elapsed (t2). As a result, the value of the current flowing from the column wiring to GND decreases, so that the potential of the column wiring falls more slowly than the first half of the falling edge of the pulse signal in which the resistors rd and re are connected in parallel. After t2, the transistors 23002 and 2
3003 are both turned on.

FIG. 24 is a timing chart showing the signal A from the pulse width signal generator 101, the signals D and E from the control unit 23001 to each transistor in FIG. 23, and the pulse signal waveform of the column wiring.

In FIG. 23, at time t1, resistance r
Since d and re are connected in parallel, the value of the current flowing to GND increases, and the waveform quickly falls.

[Embodiment 3] Embodiment 3 which is still another modification will be described.

FIG. 25 is a drawing corresponding to FIG. 23 of the second embodiment. Here, the diode 23004
The operation threshold potentials of the switch circuit including the transistor 23003 and the switch circuit including the transistor 23002 and the diode 23004 are different from each other. That is, when the falling of the pulse signal is detected by the signal from the pulse width modulation signal generator 101, the pulse width modulation signal generator 101
Are turned on to quickly bring the potential of the column wiring close to the reference potential (here, GND). When the difference between the potential of the column wiring and the reference potential becomes about 0.6 [V], the transistor 23002 is turned off, and thereafter, only the transistor 23003 is turned on. For this reason, the potential of the column wiring gradually approaches the reference potential.

As described above, according to the circuit configuration of the third embodiment, suitable pulse width modulation can be performed with a circuit having an extremely simple configuration. Although one diode 23004 is shown in the figure, the diode 23004 may be configured by connecting a plurality of diodes in series or a zener diode to control the output voltage at which the transistor 23002 is turned off.

[Embodiment 4] In the following embodiments,
The falling edge of the pulse signal is controlled in accordance with the potential state of a nearby wiring such as an adjacent wiring.

FIG. 26 is a diagram showing an example of occurrence of crosstalk occurring in six column wirings.

As described above, as shown in FIG. 26, due to the capacitance between the wirings, as shown in the drive waveforms of the signals X2 and X5 when the row wiring Y1 is selected, the adjacent column wirings are used. Signal X1 or signals X4 and X6 fall, the drive voltage decreases due to the influence of the wiring capacitance between adjacent wirings (crosstalk). For this reason, the driving voltage of the electron-emitting device driven by the difference voltage between the potential applied to the column wiring and the potential applied to the row wiring fluctuates, and as a result, the gradation of a displayed image is impaired. Is a problem. In particular, in a large-screen display panel, the number of row and column wirings is increased, and the spacing between the wirings is reduced, so that the capacitance between the wirings is increased, and the drive voltage is reduced (crosstalk) due to the potential fluctuation of the adjacent wirings. It is easy to occur. As a result, the gradation of the display image is impaired.

Even in the case of voltage driving, it is not possible to drive at the ideal potential which is the output of the voltage source due to protection resistance, wiring resistance and the like. Therefore, a case where the driving voltage is reduced due to the influence of the wiring capacitance may occur, which may cause a problem that the gradation of a display image is impaired.

In the embodiments described above, a suitable luminance gradation is realized by performing the falling of the pulse signal in a plurality of steps. At that time, the falling of the pulse signal was controlled irrespective of the potential of the nearby wiring. In the following embodiments, a configuration is described in which a pulse signal divided into a plurality of steps is not dropped when unnecessary according to the potential of a nearby wiring.

The matrix type display panel used in the image display device according to the following embodiments is basically similar to the above-described embodiments, and has a large number of substrates mounted on a substrate in a thin vacuum container. An electron source, for example, a multi-electron source in which cold cathode devices are arranged in a matrix, and an image forming member that forms an image by irradiating electrons from the multi-electron source are provided to face each other.

[0185] These cold cathode devices can be precisely positioned and formed on a substrate by using a manufacturing technique such as photolithography and etching, so that many cold cathode devices can be arranged at minute intervals. Moreover, CR
Compared to the hot cathode device used in T etc., the cathode itself and its surroundings can be driven at a relatively low temperature,
A multi-electron source with a finer arrangement pitch can be easily realized. Note that the configuration and manufacturing method of the matrix type display panel are the same as those described in the first embodiment.

First, features of the following embodiments will be described with reference to FIG.

FIG. 27 is a diagram for explaining the concept of the display driving method according to the embodiments hereinafter, and shows a circuit for driving a multi-electron source. Here, for ease of explanation, the matrix type display panel 100
Reference numeral 01 indicates an electron source in which 3 × 3 cold cathode devices are arranged in a matrix, and further omits the wiring resistance of wiring connecting these cold cathode devices. In the figure, 50c denotes a cold cathode element, and Cc denotes a capacity between column wirings.

In FIG. 27, in order to drive the cold cathode element 50c, the switching circuit 50b applies a potential -Vss sequentially from the row wiring Y1 in synchronization with the horizontal synchronizing signal of an image, and grounds the other row wirings to ground. To scan. on the other hand,
A column driver 50a has a controllable constant current source Cs. These constant current sources Cs convert a current for driving the cold cathode element 50c into a pulse width (pulse width modulation signal) corresponding to an image signal to be displayed. ) Is output as a pulse signal. Sw is a switch circuit. Vas is a voltage source, and the potential Vas
[V] is output. The switch circuit Sw is a switch for controlling whether or not the potential from the voltage source Vas is applied to the modulation signal wiring for flowing a current from the constant current source Cs to the element 50c. The switching is controlled by a control circuit (not shown). ing. That is, considering the line of the modulation signal X1, when the signal X1 falls, if the signal X2 is input to the adjacent wiring, the switch Sw connected to the signal X1 is turned on (closed). Thus, when the signal X1 falls, the signal X1 does not fall to the GND level and the potential Vas does not fall.
It only falls until. This can minimize the potential fluctuation of the signal X2 due to the capacitance between adjacent modulation signal wirings. This operation is similar to the other modulation signals X2,
The same applies to the wiring to which X3 is input.

FIG. 28 is a drive waveform diagram for explaining an outline of the operation of the circuit of FIG.

The crosstalk to the column wiring X2 due to the change in the signal level in the column wiring X1 is shown by 200 in FIG. As described above, also in the fourth embodiment, a slight crosstalk occurs due to the fall of the signal of the column wiring X1.
It can be seen that it occurs in 2, but is smaller than the crosstalk in FIG. 26 described above. This is because, in the fourth embodiment, when the column wiring X1 falls, the potential thereof becomes G
This is because it does not fall to ND. That is, in FIG. 28, when the drive waveform of the column wiring X1 falls, Vas
This is because, since the voltage drops only to the potential [V], the change in the potential at the falling edge is reduced, thereby reducing the influence on the adjacent column wiring X2. This potential Vas
[V] is a voltage (Vas + Vs) applied to the cold cathode element 50c.
s) may be determined to be a value close to a threshold voltage (corresponding to Vth described later) at which the cold cathode element 50c starts emitting electrons. If the output potential of the voltage source Vas is low, the effect of removing crosstalk is small. Conversely, if the output potential is high, the cold cathode element 50c emits electrons when not driven, which may lower the image contrast.

The following embodiments will be described in detail with reference to the drawings.

First, the structure of the display driving circuit of the image display device of the present embodiment will be described with reference to FIG.

FIG. 29 is a block diagram showing a configuration of a display drive circuit of the image display device of the present embodiment.

In FIG. 29, reference numeral 10001 denotes a display panel provided with a multi-electron source in which a large number of electron sources, for example, cold cathode devices are arranged in a matrix, on a substrate in a thin vacuum vessel. So, for example, 48
0 elements, that is, 160 pixels × 3 (RGB), and 240 elements are arranged in the vertical direction. In the present embodiment, 48
An example of a display panel 10001 having 0 elements × 240 elements will be described. However, the number of these cold cathode elements is not limited since the number is determined by a product application as needed. Each cold cathode element of the matrix type display panel 10001 matches Rmn (m = 1 to 240, n = 1, 4, 7,...) According to the color at the time of displaying an image (corresponding to the color of the corresponding phosphor).
..), Gmn (m = 1 to 240, n = 2, 5, 8,...),
Bmn (m = 1 to 240, n = 3, 6, 9,...). This display panel 10001 is, as shown in FIG.
The respective phosphors of RGB are arranged in the order of RGB in a vertical stripe.

Reference numeral 10002 denotes an analog-to-digital converter (A
/ D converter) converts an analog RGB signal decoded from, for example, an NTSC signal to an RGB signal by a decoder (not shown) into digital RGB signals having an 8-bit width, for example.
Convert to a signal. 10003 is a data rearranging unit,
It has a function of inputting a digital RGB signal (signal S1) from a / D converter 10002 or a computer or the like, rearranging it according to the pixel arrangement of the matrix type display panel 10001, and outputting it (signal S2). Reference numeral 10004 denotes a luminance data converter which converts digital data input from the data rearranging unit 10003 into a desired luminance characteristic.
For example, conversion is performed using a gamma conversion table or the like (signal S3). A shift register 10005 sequentially shifts and transfers serial data (signal S3) sent from the luminance data converter 10004 in synchronization with a shift clock (SCLK), and converts parallel digital data (corresponding to each element of the display panel 10001). XD1 to XD48
0) is formed. A modulation signal generator 10006 determines a pulse width based on a PWM clock (PCLK) according to the value of digital data from the shift register 10005 and outputs pulse signals (XDP1 to XDP480).
Reference numeral 10007 denotes a modulation signal driver.
A drive signal X1 for driving the modulation signal line of the display panel 10001 according to the pulse signal output from
~ X480 is output.

Reference numeral 10008 denotes a scanning shift register which inputs a horizontal scanning synchronizing signal (HD) as a shift clock.
A signal for sequentially selecting the scan wiring of the display panel 10001 corresponding to the scan line of the input image is generated. A scan driver 10009 applies a potential (−Vss) to a scan line selected in accordance with the output of the scan shift register 10008, connects an unselected scan line to GND (grounds), and outputs a signal to the display panel 10001. The scanning lines are sequentially selected and driven. A timing control unit 10010 generates and outputs various timing signals to be supplied to each functional block based on a synchronization signal (sync) and a sampling clock (DCLK) input together with an image signal.

FIG. 31 is a circuit diagram showing a configuration of a modulation signal generation circuit for one digital data (XD) of modulation signal generation section 10006 of the present embodiment.

In FIG. 31, reference numeral 61 denotes a down counter,
62 is an inverter. The down counter 61 loads, for example, 8-bit digital data (each of XD1 to XD480) output from the shift register 10005 at the timing of the load signal (Ld), and every time the PWM clock (PCLK) is input. Count down. Then, for example, the borrow output of the down counter 61 is inverted by the inverter 62 to obtain a pulse width modulation output. This borrow output becomes low level at the load timing by the load signal, and the value of the loaded data is equal to PC.
When LK is counted, it becomes high level. That is, “loaded data (set value)” × “clock (PCLK)
A pulse signal having a pulse width determined by the “cycle” is output.

FIG. 32 is a timing chart showing the operation of the circuit of FIG.

Here, a case where "p" is set in down counter 61 at the rise of load signal Ld is shown.
When the number of clocks PCLK corresponding to "p" is counted, the borrow output becomes low level, and PWMou is output.
t is output at high level.

FIG. 30 is a timing chart for explaining the operation of the display driving circuit of the image display device according to the present embodiment.

Next, the operation of the image display device according to the following embodiment will be described with reference to these figures.

In FIG. 29, an analog RGB signal decoded from, for example, an NTSC signal to an RGB signal by a decoder (not shown) is input to the A / D converter 10.
002, each is converted into, for example, an 8-bit digital RGB signal. The data rearranging unit 10003 performs A / D
A digital RGB signal (S1) from the converter 10002 or a computer or the like is input. At this time, the number of data in one scan line (1H) depends on the matrix type display panel 1.
If the number of pixels on the modulation signal line side of 0001 is determined, the processing is simplified. In the case of the present embodiment, the display panel 1000
The number of pixels on one modulation signal line side is set to “160”. A
The digital RGB signal (S1) from the / D converter 10002 or a computer is output in synchronization with the data sampling clock (DCLK). Here, FIG.
As shown in (1), the RGB parallel signal of the input signal (S1) is switched by the data rearranging unit 10003 at the timing of the shift clock (SCLK) which is a clock having a frequency three times the frequency of the data sampling clock (DCLK). The pixels are sequentially output according to the arrangement of the RGB pixels on the panel 10001.

The output signal (S2) of data rearranging section 10003 is input to luminance data converter 10004.
This luminance data converter 10004 is provided with a conversion table (RO) (not shown) in which predetermined conversion data is stored in advance.
M), the output signal (S2) of the data rearranging unit 10003 is converted into a signal having a luminance characteristic suitable for, for example, a gamma characteristic of a CRT.

The output signal S3 of the luminance data converter 10004 is further sent to a shift register 10005. In the shift register 10005, serial data is sequentially shifted and transferred in synchronization with a shift clock (SCLK). Are output to the modulation signal generating unit 10006 in units of horizontal scanning time as parallel digital data (XD1 to XD480) corresponding to the above elements. Here, for example, 8-bit digital data (XD1 to XD480) is input to the modulation signal generation unit 10006. As described above, the modulation signal generator 10006
Determines the pulse width of a pulse signal to be output according to digital data (“set value”) and a PWM clock (PCLK) for each element. That is, the modulation signal generation unit 10006
A pulse signal (pulse width modulation signal) having a pulse width determined by the time until the “number of PWM clocks (PCLK)” becomes equal to the “set value” is output. Then, the modulation signal driver 10007 applies a modulation signal to the column wiring of the display panel 10001 for a time determined by the pulse width of the pulse signal output from the modulation signal generation unit 10006, and drives it.

In the present embodiment, the NTSC signal is set to 2
In order to display on the display panel 10001 of 40 scanning lines, 48 of the interlaced effective scanning lines are used.
Of the five lines, 480 lines are displayed on a display panel 100
01 was overwritten. NTSC signal 1
The display panel 10001 treats the field as one frame. That is, the display panel 10001 was driven as an image signal having a frame frequency of 60 Hz and 240 scanning lines.

On the other hand, the time required to display one scan line is about 63.5 μsec for the NTSC signal, and about 56.5 μsec within that time is determined as the maximum time of the drive pulse (X 1 to X 480). As the PWM clock (PCLK) selects digital data (“set value”) for 8 bits, the PWM clock (PCLK)
The number of pulses of the M clock (PCLK) was selected to be about 56.5 μsec when the number of pulses is 256. That is, 1
The pulse width is about 220 ns clock, about 4.5 ns.
MHz frequency clock as PWM clock (PCL
K).

On the other hand, the scanning shift register 10008
A horizontal scanning synchronization signal (HD) is input as a shift clock, and a scanning signal is output by sequentially transferring a signal (YST) for determining the start time of scanning with the horizontal scanning synchronization signal (HD) as shown in FIG. . Scan driver 100
09 sequentially selects the scanning wiring from the first according to the scanning signal output from the scanning shift register 10008,
A potential -Vss (for example, -8 V) is applied to the selected scanning wiring (row wiring), and the potential of the other wiring is set to 0 V to perform scanning driving. As a result, the scan driver 10009 is connected to the selected scan line (−Vss = −8 V) and connected to the modulation signal line (column line) to which the drive potential (about +8 V) is applied by the modulation signal driver 10007. A voltage of about 16 V is applied between the electrodes of the cold cathode device. Thereby, electrons are emitted from the cold cathode device. Drive potential +8 V by modulation signal driver 10007
Are applied, and the scan driver 1000
As a result, a voltage of about 8 V is applied to the cold cathode device connected to the scanning wiring (0 V) not selected by the reference numeral 9, but as apparent from FIG. Because it is less than the voltage at which emission starts,
For example, even if the driving potential (approximately +8 V) is applied by the modulation signal driver 10007 and connected to the required wiring, the cold cathode element connected to the scanning wiring not selected by the scanning driver 10009 emits electrons. Therefore, the phosphor of the display panel 10001 corresponding to the element does not emit light.

On the contrary, the output of the modulation signal driver 10007 is connected to the non-drive (0 V) modulation signal wiring,
A voltage of about 8 V is applied to the cold cathode device connected to the selected scanning wiring (-8 V). However, as is clear from FIG. 33, the voltage applied to these cold cathode devices is lower than the threshold voltage described above, so that they do not emit electrons, and the phosphors corresponding to those devices do not emit light.

As described above, the scanning driver 1000
Electrons are emitted from the cold cathode device connected to the scanning wiring selected at 9 and to which the output of the modulation signal driver 10007 is applied with a pulse width proportional to the desired luminance. Such display driving is sequentially performed to display the display panel 1000.
1 is displayed.

Next, a configuration of a modulation signal driver 10007 for preventing crosstalk due to a potential change in an adjacent column wiring according to the fourth embodiment of the present invention will be described.

FIG. 34 is a block diagram showing a circuit configuration of modulation driver 10007 according to Embodiment 4 of the present invention.

In FIG. 34, reference numeral 70 denotes a voltage source for outputting a potential Vas [V]; 71, an input terminal to which a modulation signal (XDPi: i = 1 to 480) is input from a modulation signal generator 10006; Type display panel 10001
A current source for driving the cold cathode element to display an image, a diode 73, an inverter circuit 74, and a MOSFET 75 for controlling the driving current of the current source 72 to be supplied to or not supplied to the display panel 10001. A transistor, 76 is a 3-input OR circuit, 77 is a level shift circuit, 78 is an NPN transistor, and the display panel 1000
It controls whether or not the potential Vas is applied to one modulation signal line. 79 is a diode.

In the configuration of FIG. 34, the operation is as follows. Here, for convenience of explanation, the case of driving the j-th modulation signal line (column wiring) will be described, but the case of other modulation signal lines may be considered in the same manner.

The output of modulation signal generating section 10006 is a pulse width modulation signal (XDPi) modulated to a pulse width corresponding to the value of the luminance signal. This modulation signal is input to input terminal 71. This modulation signal is inverted by an inverter 74 and input to the base of a transistor 75 such as a MOSFET, which controls the on / off of the transistor 75. Therefore, when the modulation signal (XDPi) is at a high level, the output of the current source 72 is supplied to the modulation signal wiring through the diode 73. Conversely, when the modulation signal is low level,
Since the transistor 75 is turned on and the current from the current source 72 flows through the transistor 75, the current is not supplied to the modulation signal wiring. The driving current output from the current source 72 has a current value enough for the cold cathode device to emit electrons sufficiently. For example, in FIG. 33, the value of the element current If when the element voltage is 16 [V] may be determined.

The modulation signal input to the input terminal 71 is input to the first input terminal (76a) of the three-input OR circuit 76. Also, the second input terminal (7
6b), the (j-1) -th (left-hand side) modulation signal is input, and the third input terminal (7
The (j + 1) th (right) modulated signal is input to 6c). Also, a three-input OR circuit 76 for the modulation signal wirings at both ends to which signals such as signals X1 and X480 are input.
As described above, the second or third input terminal of the three-input OR circuit 76 in which no modulation signal is present on the left or right side is connected to GND. The output of the three-input OR circuit 76 is level-converted by the level shift circuit 77, and is output to GND or Vas [V].
Output at the potential of The output of the level shift circuit 77 is NP
The transistor 78 supplies a drive potential to the modulation signal wiring from the emitter through the diode 79. Here, for the sake of simplicity, the description will be made while ignoring the voltage drop between the base and the emitter of the NPN transistor 78 and the forward voltage drop of the diode 79 (each about 0.6 in an actual circuit).
[V] voltage drop). Therefore, the output potential of the power supply 70 may be about 1.2 [V] higher than a desired output potential (driving potential: Vas [V]).

With such a configuration, when a modulation signal is applied to the j-th modulation signal wiring, the output of the current source 72 is output through the diode 73 to drive the j-th modulation signal wiring. If a modulation signal is output to either the right (j + 1) or left (j-1) modulation signal wiring, the output of the NPN transistor 78 is output through the diode 79, so that the j-th modulation signal is output. Even if the signal falls, the potential of the j-th modulation signal wiring drops only to Vas.

FIG. 35 shows modulated signals (XDP1, XDP2,...) According to the fourth embodiment and actual display panel 100.
FIG. 4 is a diagram for explaining a drive waveform of a modulation signal (X1, X2,...) Supplied to the signal 01.

Referring to FIG. 35, the effect of removing the crosstalk of the drive waveform of the signal (X4) on the fourth modulation signal wiring will be described. Of course, the effect of removing the crosstalk of the drive waveforms of the other modulation signal wirings can be similarly considered.

In FIG. 35, when the signal (X3) on the third modulation signal wiring falls, the adjacent second and fourth modulation signals are output at a high level, so that the signal X3 is GND. Without dropping to the level, it drops to a potential substantially equal to Vas. As a result, in the second and fourth modulation signals (X2, X4), the influence of the inter-wiring capacitance due to the fall of the signal (X3) of the adjacent third modulation signal wiring is reduced, and the signal level is slightly reduced. I just let it. Thus, it can be seen that the potential change of the signals X2 and X4 is smaller than the crosstalk shown in FIG.

The portion indicated by reference numeral 91 in the modulation signal X4 falls from the state where the potential of the modulation signal X3 is Vas [V] to 0 [V] when the modulation signals of the adjacent modulation signal wirings are further turned off. At this time, since the cold cathode element to which the modulation signal X4 is applied is in a non-lighting state at this time, even if there is a change in the potential of the modulation signal X4, the image is displayed. Has no effect.
Further, since the potential difference between the potential Vas [V] and 0 [V] of the modulation signal X3 is small, the absolute amount of the potential change of the modulation signal X4 due to this is also small.

As described above with reference to FIG. 27, since the voltage Vas [V] is set to the threshold voltage (Vth) at which the cold cathode element starts emitting electrons, deterioration of image contrast is minimized. Can be suppressed. Further, the potential Vas [V] is applied to the modulation signal line only during the time when the modulation signal is applied to the modulation signal line adjacent to a certain modulation signal line, so that the modulation signal adjacent to the driven modulation signal line is applied. The fall of the wiring always drops only to Vas [V].
Further, since the potential Vas [V] is applied to the modulation signal line only during the time when the logical sum of the adjacent modulation signal lines is obtained, the potential (V) is applied to the element not driven by the modulation signal line.
(as + Vss) [V] is not applied. Therefore, the cold cathode element is not driven at the potential (Vas + Vss) [V] for a longer time than necessary, and deterioration of image contrast is minimized. As a result, a drive circuit capable of driving a display panel with reduced crosstalk between adjacent wirings can be provided even if there is inter-wiring capacitance between adjacent modulation signal lines. As a result, an image having good gradation characteristics can be displayed.

[Fifth Embodiment] FIG. 36 is a block diagram showing a configuration of a modulation signal driver 10007a according to a fifth embodiment of the present invention. Portions common to FIG. 34 described above are denoted by the same reference numerals. Description is omitted.

In FIG. 36, reference numeral 706 denotes a 5-input OR circuit, and the other configuration is the same as that of the above-described fourth embodiment, so that the description is omitted. Here, for convenience of description, the case of driving the j-th modulation signal line will be described. Of course, the same applies to the driving of other modulation signal lines.

The output of modulation signal generating section 10006 is a pulse width modulation signal (XDPi) modulated to a pulse width corresponding to the value of the luminance signal. This modulation signal is input to input terminal 71. This modulation signal is inverted by an inverter 74 and
By driving a transistor 75 such as an SFET, a current source 72
It is determined whether or not the output current from is supplied to the modulation signal wiring. That is, when the level of the modulation signal is high,
A drive current is supplied to the modulation signal wiring through the diode 73. The drive current is determined as a current that the cold cathode device emits electrons sufficiently. For example, in FIG. 33, the value of the element current If when the element voltage is 16 [V] may be determined.

The modulation signal (XDPi) input to the input terminal 71 is input to the first input terminal (706a) of the 5-input OR circuit 706. Also, a 5-input OR circuit 706
(J-2) th (second on the left) modulated signal is applied to the second input terminal (706b) of the
The (j-1) th (left adjacent) modulation signal is applied to a third input terminal (706c) 06. The (j + 1) -th (right adjacent) modulation signal is applied to the fourth input terminal (706d) of the five-input OR circuit 706, and the five-input OR circuit 7
The (j + 2) th (second right) modulation signal is applied to the fifth input terminal (706e) 06.

In this case as well, the first and second input terminals or the fourth and fifth input terminals of the five-input OR circuit 706 for the modulation signal wirings at both ends are connected to the low level, and the second from the end. The first input terminal or the fifth input terminal of the five-input OR circuit 706 for the modulation signal wiring is also connected to the low level. The output of the 5-input OR circuit 706 is level-converted by the level shift circuit 77 and input to the base of the NPN transistor 78, followed by an emitter follower to supply a drive potential to the modulation signal wiring through the diode 79.

As described above, according to the fifth embodiment,
In addition to the modulation signal wiring adjacent to the left and right, it is possible to eliminate the influence of crosstalk due to the fall of the modulation signal in the modulation signal wiring adjacent to the modulation signal wiring. The detailed description is the same as that of the above-described fourth embodiment, and thus will be omitted.

Of course, the number of inputs of the five-input OR circuit 706 may be increased to prevent the occurrence of crosstalk due to the fall of the modulation signal in the adjacent modulation signal wiring, for example, by skipping two.

As described above, according to the fifth embodiment, it is possible to prevent the occurrence of crosstalk due to the capacitance between the adjacent modulation signal lines and the skipped modulation signal line.

[Embodiment 6] FIG. 37 is a block diagram showing a configuration of a modulation driver 10007b according to Embodiment 6 of the present invention. Portions common to the above-mentioned drawings are denoted by the same reference numerals, and description thereof will be made. Omitted.

In FIG. 37, reference numeral 716 denotes a 4-input OR circuit, and the other configuration is the same as that of the fourth embodiment. Incidentally, also in the sixth embodiment, for convenience of explanation, the case of driving the j-th modulation signal line will be described. Of course, the same applies to the driving of other modulation signal lines.

The modulation signal (XD
Pi) is the first input terminal (71) of the 4-input OR circuit 716.
6a). The (j-1) -th (left adjacent) modulation signal is applied to the second input terminal (716b) of the 4-input OR circuit 716, and (j + 1) is applied to the third input terminal (716d) of the 4-input OR circuit 716. ) -Th (right next) modulated signal is added. As described above, in the four-input OR circuit 716 for the modulation signal wirings at both ends, the input terminal of the four-input OR circuit 716 in which the corresponding adjacent modulation signal does not exist is connected to the low level. Further, in the third embodiment, the fourth input terminal (71
6d) are commonly connected, and the signal PPRE is input.

As shown in FIG. 38, this signal PPRE becomes high level just before the modulation signal (XDPi) becomes high level (active) (rising), that is, at the beginning of the horizontal scanning period, and the modulation signal becomes high level. At the same time, it is falling to a low level. For example, it rises 1 [μsec] before the modulation signal goes high, and falls to the low level at the same time as the modulation signal goes high.
In FIG. 38, reference numeral 95 indicates crosstalk of the modulated signal X4 due to the fall of the adjacent modulated signal X3 to the potential Vas, and reference numeral 96 indicates the modulated signal X3 having the potential Vas.
7 shows the crosstalk of the modulated signal X4 due to the fall from the signal to GND (these are the same as in the fourth and fifth embodiments). Further, reference numeral 97 indicates a state where the potential of the modulation signal wiring is increased to the potential Vas by the signal PPRE before the modulation signal X4 rises.

Thus, when the modulation signal is applied to the wiring adjacent to the left and right of the currently driven modulation signal wiring, the potential drops to the potential Vas at the time of the fall in the above-described fourth and fifth embodiments. However, when the modulation signal rises, the potential rises to the potential Vas before the modulation signal rises, so that the rise time of the modulation signal wiring can be reduced. That is, the gradation characteristics in the pulse width modulation can be improved.

As a result, even if there is a capacitance between adjacent modulation signal wirings, each element of the display panel can be driven to display an image with little crosstalk. As a result, an image display device having good gradation characteristics could be provided.

In the present embodiment, the display panel 100 is driven by the current from the current source 72 in accordance with the pulse width modulation signal.
01 is driven, and such a circuit is an IC
In this case, each element may be driven using a voltage source (in this case, the internal resistance is relatively high due to a protective resistance or the like). With the configuration of the present embodiment described above, crosstalk can be similarly reduced even when a voltage source is used.

Further, in the present application, in each embodiment, the configuration using the cold cathode type electron-emitting device has been described. However, it is needless to say that the present invention can be applied to the EL device and any other electron-emitting device. For example, even if the cold cathode electron source is constituted by a surface conduction type emission element, an FE type emission element, or an MIM type emission element, it can be applied to the embodiment without any problem.

The image display device according to the embodiment of the present invention basically includes a multi-electron source in which a large number of electron sources, for example, cold-cathode devices are arranged on a substrate in a thin vacuum vessel. An image forming member (phosphor) that forms an image by irradiation of electrons emitted from the electron source is provided to face the image forming member.

The cold cathode elements can be precisely positioned and formed on the substrate by using a manufacturing technique such as photolithography and etching, so that a large number of cold cathode elements can be arranged at minute intervals. In addition, as compared with a hot cathode conventionally used in a CRT or the like, the cathode itself and its peripheral portion can be driven at a relatively low temperature, so that a multi-electron source with a finer arrangement pitch can be easily realized.

Further, a surface conduction electron-emitting device (SCE) is particularly preferable among the cold cathode devices. That is, among the cold cathode devices, the MIM type device requires relatively precise control of the thickness of the insulating layer and the upper electrode.
It is necessary for the mold element to precisely control the shape of the tip of the needle-like electron emitting portion. For this reason, these elements have a relatively high manufacturing cost, and it is sometimes difficult to manufacture a large-area element due to limitations in the manufacturing process. In contrast, the SCE has a simple structure and is easy to manufacture, and a large-area SCE can be easily manufactured. In recent years, particularly in a situation where a large-screen and inexpensive display device is required, it can be said that the cold-cathode element is particularly suitable.

[Embodiment 7] Embodiments 7, 8, and 9 described below are Embodiments 4, 5, and 9, respectively.
6 are partially modified.

FIG. 39 is a diagram showing a configuration of a column wiring driving circuit used in the seventh embodiment. The modulation driver 1 shown in FIG.
This corresponds to a circuit in one block surrounded by a dotted line in 0007. Equivalent components are given the same reference numerals as in FIG.

In FIG. 39, reference numeral 3902 denotes a switch which receives a modulation signal and switches the output according to the logic level of the input terminal 71, 3901 denotes a switch which switches the output according to the output of the OR circuit 7601, and 7601 denotes a 2-input O.
R switch.

In the configuration of FIG. 39, the operation is as follows. Here, for convenience of explanation, the case of driving the j-th modulation signal line (column wiring) will be described, but the case of other modulation signal lines may be considered in the same manner.

The output of modulation signal generating section 10006 is a pulse width modulation signal (XDPi) modulated to a pulse width corresponding to the value of the luminance signal. This modulation signal is input to input terminal 71. This modulation signal is input to the control terminal of the switch 3902, and controls the switch 3902. When the modulation signal (XDPi) is at the high level, the switch 3902 selects the contact 3902a, and the output of the current source 72 is supplied to the modulation signal wiring. Conversely, when the modulation signal is at a low level, the switch 3902 selects the contact 3902b and supplies a GND potential or a potential Vas as a reference potential to the modulation signal. The driving current output from the current source 72 has a current value enough for the cold cathode device to emit electrons sufficiently. For example, in FIG.
What is necessary is just to determine the value of the element current If at 6 [V].

The (j-1) th (left) modulation signal is input to the first input terminal (76b) of the two-input OR circuit 7601, and the second input terminal (76c) of the two-input OR circuit 76 is further input. ), The (j + 1) th (right) modulated signal is input. Also, like the two-input OR circuit 7601 for the modulation signal wirings at both ends to which signals such as the signals X1 and X480 are input, the first or second of the two-input OR circuit 7601 having no modulation signal on the left or right side thereof. The input terminal is connected to GND. This two-input OR circuit 760
The output of the first output terminal is input to the control terminal of the switch 3901. When the control terminal of the switch 3901 is at the high level, the switch 3901 is set to the contact 3901a.
Connected to When it is at the low level, it is connected to the contact 3901b.

With such a configuration, when a modulation signal is applied to the j-th modulation signal wiring, switch 3902 selects contact 3902a, the output of current source 72 is output to the modulation signal wiring, and the j-th modulation signal wiring is output. Will be driven. In addition, the right side (j + 1) or the left side (j−
When a modulation signal is output to any of the modulation signal wirings of 1), the switch 3901 has selected the switch 3901a, so the j-th modulation signal falls, and the switch 3902 selects the contact 3902b. The potential of the j-th modulation signal wiring drops only to Vas. The switch 3901 is set to the contact 3901 only when both of the modulation signals (potentials) of the adjacent wirings are at the low level.
b is selected, and if the j-th modulation signal becomes low level, j
The potential of the third modulation signal wiring is set to the GND potential which is the reference potential.

[Eighth Embodiment] FIG. 40 shows the eighth embodiment.
36 is a diagram showing a configuration of a column wiring driving circuit used in FIG.
Of the modulation driver 10007 of FIG. Figure 3 shows the equivalent
The same reference numerals as in FIG.

In FIG. 40, 70601 is a 4-input OR
This is a circuit, and the other configuration is the same as that of the above-described seventh embodiment, and the description is omitted. Here, for convenience of description, the case of driving the j-th modulation signal line will be described. Of course, the same applies to the driving of other modulation signal lines.

The output of modulation signal generating section 10006 is a pulse width modulation signal (XDPi) modulated to a pulse width corresponding to the value of the luminance signal. This modulation signal is input to input terminal 71. This modulation signal is input to the control terminal of the switch 3902, and controls the switch 3902. When the level of the modulation signal is high, the switch 3902
Selects the contact 3902a, and the output of the current source 72 supplies a drive current to the modulation signal wiring. The drive current is determined as a current that the cold cathode device emits electrons sufficiently. For example, in FIG. 33, the value of the element current If when the element voltage is 16 [V] may be determined.

The (j-2) th (second left) modulation signal is applied to the first input terminal (706b) of the 4-input OR circuit 70601, and the 4-input OR circuit 70601
The (j-1) th (left adjacent) modulated signal is applied to the second input terminal (706c). Also, a 4-input OR circuit 70
The (j + 1) -th (right-side) modulation signal is applied to the third input terminal (706d) of the 601 and the 4-input OR circuit 7
The (j + 2) th (second right) modulation signal is applied to the fourth input terminal (706e) of 0601.

In this case as well, the first and second inputs of the four-input OR circuit 70601 to the modulation signal lines
The input terminal or the fourth and fifth input terminals are connected to a low level, and the four input terminals O to the second modulation signal wiring from the end are connected.
The first input terminal or the fifth input terminal of the R circuit 70601 is also connected to the low level. This 4-input OR circuit 7060
The output of 1 is input to the control terminal of the switch 3901. When the control input terminal of switch 3901 is at a high level, switch 3901 is connected to contact 3901a, and when the control input terminal of switch 3901 is at a low level, it is connected to contact 3901b.

As described above, according to the eighth embodiment,
In addition to the modulation signal wiring adjacent to the left and right, it is possible to eliminate the influence of crosstalk due to the fall of the modulation signal in the modulation signal wiring adjacent to the modulation signal wiring. The detailed description is the same as that of the above-described seventh embodiment, and thus will be omitted.

Naturally, the number of inputs of the four-input OR circuit 70601 may be increased to prevent the occurrence of crosstalk due to the fall of the modulation signal in the adjacent modulation signal wiring, for example, by skipping two.

As described above, according to the eighth embodiment, it is possible to prevent the occurrence of crosstalk due to the capacitance between the adjacent modulation signal lines and the skipped modulation signal line.

[Ninth Embodiment] FIG. 41 is a diagram showing a configuration of a column wiring driving circuit used in the ninth embodiment.
7 corresponds to a circuit in one block surrounded by a dotted line in the modulation driver 10007. Equivalent components are given the same reference numerals as in FIG.

In FIG. 41, 71601 is a 3-input OR
This is a circuit, and the other configuration is the same as that of the seventh embodiment.
In the ninth embodiment, the driving of the j-th modulation signal line will be described for convenience of explanation. Of course, the same applies to the driving of other modulation signal lines.

The (j-1) th (left adjacent) modulation signal is applied to the first input terminal (716b) of the three-input OR circuit 71601, and is applied to the second input terminal (716d) of the three-input OR circuit 71601. Is the (j + 1) -th (right adjacent) modulation signal added. As described above, in the three-input OR circuit 71601 for the modulation signal wirings at both ends, the three-input OR circuit 71601 in which the corresponding adjacent modulation signal does not exist
Are connected to a low level. Further, in the ninth embodiment, the third input terminal (716d) of the three-input OR circuit 71601 is commonly connected, and the signal PP
RE has been input. The operation based on this signal PPRE is the same as in the sixth embodiment.

[0260] The forms of each seed described above can be used in various combinations.

As described above with reference to the embodiments, according to the present invention, a suitable image display can be realized.

[0262]

As described above, according to the present invention, there is an effect that a high quality image can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of an image display device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a problem of the present invention.

FIG. 3 is a diagram for explaining the operation of the circuit of FIG. 1;

FIG. 4 is a diagram illustrating operation timings of the image display devices according to the first embodiment and the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a circuit configuration of the image display device according to the first embodiment of the present invention.

FIG. 6 is a diagram for explaining an effect of the circuit of FIG. 5;

FIG. 7 is a partially cutaway perspective view of a display panel of the image display device according to the embodiment of the present invention.

FIG. 8 is a plan view illustrating a phosphor array of a face plate of the display panel of the present embodiment.

FIGS. 9A and 9B are a plan view and a cross-sectional view, respectively, of the planar surface conduction electron-emitting device used in the present embodiment.

FIG. 10 is a cross-sectional view showing a manufacturing process of the planar surface conduction electron-emitting device.

FIG. 11 is a diagram showing an applied voltage waveform during energization forming processing.

FIG. 12 shows an applied voltage waveform (a) during energization activation processing,
It is a figure showing change (b) of discharge current Ie.

FIG. 13 is a sectional view of a vertical surface conduction electron-emitting device used in the present embodiment.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of a vertical surface conduction electron-emitting device.

FIG. 15 is a graph showing typical characteristics of the surface conduction electron-emitting device of the present embodiment.

FIG. 16 is a plan view of a substrate of the multi-electron source used in the present embodiment.

FIG. 17 is a sectional view taken along the line A-A ′ in FIG. 8;

FIG. 18 is a block diagram of a multi-function image display device using the image display device according to the embodiment of the present invention.

FIG. 19 is a diagram showing an example of a conventionally known surface conduction electron-emitting device.

FIG. 20 is a diagram showing an example of a conventionally known FE-type electron-emitting device.

FIG. 21 is a view showing an example of a conventionally known MIM type electron-emitting device.

FIG. 22 is a diagram illustrating a wiring method of the electron-emitting device.

FIG. 23 is a diagram showing a circuit configuration of a column line driving circuit used in Embodiment 2 of the present invention.

24 is a timing chart of signal waveforms and control signals in the circuit of FIG.

FIG. 25 is a diagram showing a configuration of a column line driving circuit according to a third embodiment of the present invention.

FIG. 26 is a diagram illustrating an example of occurrence of crosstalk in six column wirings.

FIG. 27 is a diagram illustrating the concept of the display driving method according to the embodiment of the present invention.

FIG. 28 is a drive waveform chart for explaining an operation outline of the circuit of FIG. 27;

FIG. 29 is a block diagram showing a configuration of a drive circuit of an image display device according to Embodiment 4 of the present invention.

FIG. 30 is a timing chart illustrating the operation of the circuit in FIG. 29;

FIG. 31 is a circuit diagram illustrating a configuration of a modulation signal generation unit according to the present embodiment.

FIG. 32 is a waveform diagram illustrating an operation of the modulation signal generation unit according to the present embodiment.

FIG. 33 is a graph illustrating characteristics of the cold cathode element used in the present embodiment.

FIG. 34 is a block diagram showing a configuration of a modulation signal driver according to Embodiment 4 of the present invention.

FIG. 35 is a diagram illustrating a waveform example of a modulation signal according to the fourth embodiment.

FIG. 36 is a block diagram showing a configuration of a modulation signal driver according to Embodiment 5 of the present invention.

FIG. 37 is a block diagram showing a configuration of a modulation signal driver according to Embodiment 6 of the present invention.

FIG. 38 is a diagram illustrating a waveform example of a modulation signal according to the sixth embodiment.

FIG. 39 is a block diagram illustrating a configuration of a column line driving circuit according to a seventh embodiment of the present invention.

FIG. 40 is a block diagram showing a configuration of a column wiring driving circuit according to Embodiment 8 of the present invention.

FIG. 41 is a block diagram showing a configuration of a column wiring driving circuit according to Embodiment 9 of the present invention.

Claims (3)

[Claims] 1. An image display method for driving by applying signals having different falling timings to a plurality of display elements, wherein the falling of the signals is performed in a plurality of steps. Display method. 2. An image display method for driving by applying signals having different falling timings to each of a plurality of display elements, wherein the signals rise from a predetermined level in a display state to a predetermined level in a non-display state. An image display method, comprising: changing an operation state of a signal fall circuit between a predetermined level in the display state and a predetermined level in a non-display state when lowering. 3. An image display method for driving by applying signals having different falling timings to each of a plurality of display elements, wherein the signal level is changed from a predetermined level in a display state to a predetermined level in a non-display state. Using a plurality of charge paths for approaching and changing the operation state of the plurality of charge paths from a predetermined level in the display state to a predetermined level in the non-display state when the signal falls. Characteristic image display method.