JP2000307886A - Horizontal deflection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress image distortions caused by high voltage fluctuations. SOLUTION: This horizontal deflection circuit 10 includes an RGB extracting circuit 22, and the circuit 22 extracts what is equal to or more than a black level of an RGB signal. The extracted RGB signal being equal to or more than the black level is added by an adder 24, a horizontal component is eliminated by a vertical filter 26, and subsequently its phase is inverted by an inverted amplifier 28. For this reason, an output that fluctuates in the same way as a high voltage can be obtained. Also, a beam current is detected in a resistance R11, and a voltage Vd is obtained at one end of a capacitor C14 by the current. The output of the amplifier 28 is clamped by the voltage Vd is a vertical interval. The output of a clamp capacitor Cc and a vertical parabola voltage are added by an adder 32, and a transistor T12 is controlled according to the output of the adder 32. Thus, the inter-terminal voltage of an S-shaped correction capacitor Cs is varied, and horizontal amplitude is adjusted according to high voltage fluctuations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflection circuit,
In particular, the present invention relates to a horizontal deflection circuit which is applied to, for example, a television receiver and a monitor and drives a cathode ray tube.

[0002]

2. Description of the Related Art In a conventional horizontal deflection circuit 1 shown in FIG.
A beam current flowing between the cathode lines (CRT) 3 is detected by a resistor R1 connected to a low-potential output terminal 2a on the secondary side of the flyback transformer (FBT) 2. Also,
Capacitor C provided between output terminal 2a and ground plane
1 is charged by the beam current flowing through the resistor R1. The voltage V1 generated at one end of the capacitor C1 is input to the subtractor 4 after being inverted. Further, the vertical parabola voltage is input to the subtractor 4. That is, the voltage V1 is added (superimposed) to the vertical parabola voltage. The transistor T1 is turned on / off according to the voltage output from the subtractor 4, and the discharge of the unnecessary charges of the S-shaped correction capacitor Cs' is controlled. That is, the voltage between the terminals of the S-shaped correction capacitor Cs' is changed, and accordingly, the voltage between the terminals of the horizontal deflection coil L2 is changed. Therefore, the high voltage generated on the secondary side is varied, and the horizontal amplitude of the screen displayed on the CRT 3 is kept constant.

[0003]

However, when a pattern having a small contrast as shown in FIG. 6A is displayed on the CRT 3, the FBT 2 is a pattern (white portion) in one flyback pulse per horizontal cycle. The anode voltage (high pressure) cannot be replenished. That is, the high voltage decreases in the vertical cycle, and the pattern is deformed into a trapezoid as shown in FIG. In order to prevent this, it is necessary to correct the horizontal amplitude using the pin cushion circuit (PCC) 5 in accordance with the fluctuation (decrease) of the high voltage. However, in this case, the response speed is delayed due to the effect of the capacitor C1, and the correction of the horizontal amplitude cannot be followed within one vertical cycle. When the response speed is increased by reducing the capacitance of the capacitor C1 in order to prevent this, a current (flyback current) by a flyback pulse as shown in FIG. 7A is applied to the resistor R1 as shown in FIG. 7C. Such a voltage is generated. For this reason, the S-shaped correction capacitor Cs' provided in the PCC 5 and the coil L1 resonate in parallel, and the pattern is distorted as shown in FIG. 6C. That is, in the related art, a trapezoidally distorted pattern as shown in FIG. 6B could not be corrected.

[0004] Therefore, a main object of the present invention is to provide a horizontal deflection circuit capable of preventing image distortion.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a horizontal deflection circuit for driving a cathode ray tube, an extraction unit for extracting a black level or more of a primary color signal input to the cathode ray tube, and a high frequency component of an output of the extraction unit. A horizontal deflection circuit comprising: a removing unit for removing; and an adjusting unit for adjusting a horizontal amplitude based on an output of the removing unit.

[0006]

The horizontal deflection circuit drives a cathode ray tube (CRT). The extracting means outputs a primary color signal (RGB) input to the CRT.
Signal) or higher. The removing unit removes a high-frequency component output from the extracting unit. That is, the horizontal component of the primary color signal is removed. The adjusting means adjusts the horizontal amplitude based on the output of the removing means. That is, the primary color signal level corresponds to the luminance level, and the luminance level causes high-voltage fluctuation. By adjusting the horizontal amplitude according to the primary color signal level, image distortion due to high-voltage fluctuation is suppressed.

[0007] In one aspect of the invention, the adjusting means includes a clamping means and an overlapping means. The clamping means is CR
The output of the removing means is clamped during a vertical blanking period by a voltage having a fixed relation to the beam current flowing through T. The superimposing means superimposes the vertical parabola voltage on the output of the clamp means. Therefore, since the horizontal drive transistor is driven by the parabola voltage corrected by the voltage having a fixed relation to the high voltage, image distortion due to the high voltage fluctuation can be prevented.

In one embodiment of the present invention, the extracting means includes an adding means. The adding means adds each of the primary color signals of the black level or higher. That is, the R, G, and B signals are individually extracted above the black level, and the extracted R, G, and B signals are added.

[0009]

According to the present invention, since the horizontal amplitude is adjusted according to the high-voltage fluctuation, it is possible to suppress image distortion caused by the horizontal amplitude.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a horizontal deflection circuit 10 of this embodiment includes an input terminal 12, which is connected to the base of a transistor T11. The collector of the transistor T11 is connected to the primary-side input terminal 14b of the flyback transformer (FBT) 14. Transistor T11
A connection point between the FBT14 and the FBT14 is provided with a damper diode D11.
, One end of capacitor C11 and coil L
11 is connected to one end. The emitter of the transistor T11 is connected to the ground plane. Damper diode D11
Is connected to the cathode of the damper diode D12, and the anode of the damper diode D12 is connected to the ground plane. The connection point between the damper diodes D11 and D12 is connected to the other end of the capacitor C11, one end of the capacitor C12, one end of the capacitor C13 and the coil L12.
Are connected at one end. The other end of the capacitor C12 is
Connected to ground plane. The other end of the capacitor C13 is connected to the other end of the coil L11. The other end of the coil L12 is connected to a ground via an S-shaped correction capacitor Cs. The input terminal 14a on the primary side of the FBT 14 is connected to the ground via the constant voltage source V11.

The output terminal 14 on the secondary side of the FBT 14
c is connected to the anode of a cathode ray tube (CRT) 16. The cathode of the CRT 16 has a CRT drive circuit 1
8 is connected, and a video signal processing circuit 20 is connected to the CRT drive circuit 18. An RGB signal extraction circuit 22 is connected to a connection point between the CRT drive circuit 18 and the video signal processing circuit 20. The RGB signal extraction circuit 22 is connected to a vertical filter 26 via an adder 24. The output terminal of the vertical filter 26 is connected to the input terminal of the inverting amplifier 28. The output terminal of the inverting amplifier 28 is connected to the input terminal of the buffer amplifier 30 via the clamp capacitor Cc. An output terminal of the buffer amplifier 30 is connected to one input terminal of the adder 32. An input terminal 34 is connected to the other input terminal of the adder 32. The output terminal of the adder 32 is connected to the base of the horizontal drive transistor T12, and the collector of the horizontal drive transistor T12 is connected to the ground plane.
The emitter of the horizontal drive horizontal drive transistor T12 is connected to the connection point between the coil L12 and the S-shaped correction capacitor Cs via the coil L13.

The circuit 50 including the RGB signal extracting circuit 22, the adder 24 and the vertical filter 26 will be described in detail. The circuit 50 is shown in FIG. Circuit 50
Includes input terminals 52, 54 and 56 and are connected to the bases of transistors T21, T22 and T23, respectively. The collector of the transistor T21 is connected to the resistor R21.
To the bias Vcc. The collector of the transistor T21 is connected to the output terminal 58, and the connection point between the transistor T21 and the output terminal 58 is connected to the collector of the transistor T22 and the collector of the transistor T23. The emitter of the transistor T21 is connected to the emitter of the transistor T24 via the resistor R22. Further, the emitter of the transistor T22 is connected to the emitter of the transistor T24 via the resistor R23. Further, the emitter of the transistor T23 is connected to the emitter of the transistor T24 via the resistor R24. The collector of the transistor T24 is connected to the bias Vcc, and the base of the same transistor T24 is connected to one end of the resistor R25 and one end of the resistor R26. The other end of resistor R25 is connected to bias Vcc. The other end of the resistor R26 is connected to a ground plane. Further, one end of a capacitor C21 is connected to a connection point between the transistor T21 and the output terminal 58, and the other end of the capacitor C21 is connected to a ground plane.

In this circuit 50, the video signal processing circuit 20
, R, G and B signals are input to the corresponding input terminals 52, 54 and 56, respectively. Therefore, differential amplification is performed between the transistors T21, T22 and T23 and the transistor T24. Capacitor C
21 removes high frequency components from the result of differential amplification. That is, the bias voltage (base voltage) corresponding to the black level is given to the resistor R26, and the transistor T24
, The R, G, and B signals at or above the black level are extracted. The R, G, and B signals of the black level or more are added at point P, and the horizontal component included in the added RGB signals is removed by the capacitor C21. The RGB signal from which the horizontal component has been removed is output from the output terminal 58. The vertical filter 26 shown in FIG. 1 is a low-pass filter formed by the capacitor C21 shown in FIG.

Further, the output terminal 1 on the secondary side of the FBT 14
4d is connected to the input terminal of the buffer amplifier 36. F
A connection point between the BT 14 and the buffer amplifier 36 has a resistor R
11 is connected to one end of the capacitor C14. The other end of the resistor R11 is connected to a ground via a constant voltage source V12. The other end of capacitor C14 is connected to a ground plane. The output terminal of the buffer amplifier 36 is connected to the collector of the transistor T13, and the input terminal 38 is connected to the base of the transistor T13. The emitter of the transistor T13 is connected to a connection point between the clamp capacitor Cc and the buffer amplifier 30.

The input terminal 12 is supplied with a horizontal drive pulse. When the horizontal drive pulse is at a high level,
The transistor T11 turns on. Therefore, the damper diodes D11 and D12 are also turned on. At this time, the sawtooth current I1 flows through the coil (horizontal deflection coil) L11,
Also, the sawtooth current I2 flows through the coil L12. Sawtooth current I
1 and I2 decrease linearly with the elapse of the scanning period, and their directions are reversed (in the direction opposite to the arrow in the drawing) almost at the middle of the scanning period.

In the latter half of the scanning period, the sawtooth current I1 flows to the ground via the transistor T1. When the sawtooth current I1 is larger than the sawtooth current I2, the damper diode D
12, a difference current I1-I2 flows, and a damper diode D
The current of 11 becomes 0. On the other hand, when the sawtooth current I1 is smaller than the sawtooth current I2, the difference current I2-I1 flows through the damper diode D11, and the current of the damper diode D12 becomes zero.

In the vertical flyback period, a low level horizontal drive pulse is applied to the transistor T11, and the transistor T11 is turned off. Therefore, the damper diodes D11 and D12 are also turned off. Then, the sawtooth current I1 charges the capacitor C11, and the sawtooth current I2 charges the capacitor C12. When the charging of the capacitors C11 and C12 is completed, the capacitors C11 and C12
12 starts the discharge. That is, the capacitor C11 and the series circuit of the horizontal deflection coil L11 and the capacitor C13 resonate in parallel, and the capacitor C12 and the series circuit of the coil L12 and the S-shaped correction capacitor Cs resonate in parallel. An approximately sinusoidal retrace pulse voltage is generated between both terminals of the capacitors C11 and C12. When the retrace pulse voltage becomes 0, the damper diodes D11 and D11
12 becomes conductive, and the operation shifts to the operation in the first half of the scanning period again.
Such an operation is repeatedly executed according to the horizontal drive pulse.

Thus, the sawtooth current flows through the horizontal deflection coil L11. The FBT 14 boosts a flyback pulse generated during a flyback period of the sawtooth current flowing through the horizontal deflection coil L11, and generates an anode voltage (high voltage) applied to the CRT 16. Further, the RGB signals output from the video signal processing circuit 20 are supplied to the CRT 16 via the CRT drive circuit 18. Therefore, CRT1
6 outputs an image corresponding to the RGB signal. At this time, a beam current flows from the anode to the cathode of the CRT 16.

The RGB signals output from the video signal processing circuit 20 are supplied to an RGB signal extraction circuit 22.
In the RGB signal extraction circuit 22, the RGB signal extraction circuit 22 shown in FIG.
From the signal, the RGB values equal to or higher than the black level as shown in FIG.
The signal is extracted. The horizontal components are removed from the extracted RGB signals by the vertical filter 26. Therefore, a signal as shown in FIG. 3E is output from the vertical filter 26. The RGB signal from which the horizontal component has been removed is output to an inverting amplifier 28.
Given to. In the inverting amplifier 28, the phases of the RGB signals are inverted, and the RGB signals whose phases have been inverted are supplied to the clamp capacitor Cc as shown in FIG.
That is, an output that fluctuates similarly to a high voltage as shown in FIG.

On the other hand, the output terminal 14 on the secondary side of the FBT 14
3A, the beam current flowing through the CRT 16 is detected by the high voltage as shown in FIG. 3A, and the capacitor C14 is detected by the current flowing through the resistor R11.
Is charged. Therefore, voltage Vb is generated at one end of capacitor C14. This voltage Vb is applied to buffer amplifier 36. In the base of the transistor T13,
A vertical retrace pulse as shown in FIG. 3B is applied through the input terminal 38, and during the vertical retrace period, the transistor T1
3 turns on. Therefore, voltage Vb is applied to clamp capacitor Cc via buffer amplifier 36. For this reason, in the clamp capacitor Cc, the RGB signals whose phases are inverted are clamped by the voltage Vb. The clamped voltage is supplied to the buffer amplifier 30, and a voltage as shown in FIG.
Is input to A vertical parabola voltage is input to the adder 32, and the two voltages are added (combined) by the adder 32. The voltage output from the adder 32 is applied to the base of the horizontal driving transistor T12, and therefore, the magnitude of the current flowing through the emitter of the horizontal driving transistor T12 is varied according to the base voltage of the horizontal driving transistor T12. That is, the voltage between the terminals of the S-shaped correction capacitor Cs is varied. Therefore, the horizontal deflection coil L11
Is generated.

More specifically, when a screen as shown in FIG. 4A is displayed on the CRT 16, a signal as shown in FIG. 4B is output from the RGB extraction circuit 22 corresponding to the screen. You. At this time, the buffer amplifier 30
Outputs a voltage as shown in FIG. This voltage changes in substantially the same manner as the high voltage in FIG. 3A, and is supplied to the adder 32 provided in the pin cushion circuit (PCC) 48. That is, the output of the buffer amplifier 30 as shown in FIG. 4C is added (superimposed) to the vertical parabolic voltage as shown in FIG. 4B. Therefore, FIG.
A voltage as shown in (E) is output from the adder 32.
For this reason, the voltage output from the adder 32 prevents distortion of a portion corresponding to the trapezoidal oblique side of the screen shown in FIG. 4A in the period L1, and distortion generated in the latter half of the vertical cycle in the period L2. Is prevented. That is, the PCC 48 adjusts the horizontal amplitude according to the high-voltage fluctuation in the vertical cycle. Specifically, the pattern can be prevented from being trapezoidally deformed as shown in FIG. FIG.
The screen shown in (A) is rotated 90 degrees to the left for convenience of explanation.

According to this embodiment, since the horizontal amplitude is adjusted according to the high voltage fluctuation in the vertical period, it is possible to suppress the image distortion caused by the high voltage fluctuation.

[Brief description of the drawings]

FIG. 1 is an illustrative view showing one embodiment of the present invention;

FIG. 2 is a circuit diagram showing an RGB signal extraction circuit, an adder, and a vertical filter shown in FIG. 1 embodiment.

FIG. 3 is an illustrative view showing an output waveform of each circuit shown in FIG. 1 embodiment;

FIG. 4 is an illustrative view showing an output waveform of each circuit shown in FIG. 1 embodiment;

FIG. 5 is an illustrative view showing a conventional horizontal deflection circuit;

FIG. 6 is an illustrative view showing a high voltage corresponding to a screen when controlled by the conventional horizontal deflection circuit shown in FIG. 5;

7 is an illustrative view showing a detection voltage of a beam current corresponding to a flyback pulse in the conventional horizontal deflection circuit shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 10 horizontal deflection circuit 14 FBT 16 CRT 18 CRT drive circuit 20 video signal processing circuit 22 RGB signal extraction circuit 26 vertical filter

Claims (3)

[Claims] 1. A horizontal deflection circuit for driving a cathode ray tube, extracting means for extracting a black level or more of a primary color signal input to the cathode ray tube, removing means for removing a high-frequency component of an output of the extracting means, and A horizontal deflection circuit comprising an adjusting unit for adjusting a horizontal amplitude based on an output of the removing unit. 2. The control device according to claim 1, wherein the adjusting unit clamps an output of the removing unit in a vertical blanking period with respect to a voltage having a fixed relationship with a beam current flowing between the cathode lines, and a vertical line to an output of the clamping unit. 2. The horizontal deflection circuit according to claim 1, further comprising superimposing means for superimposing a parabola voltage. 3. The horizontal deflection circuit according to claim 1, wherein said extraction means includes addition means for adding each of said primary color signals having a black level or higher.