JP2000307440A - Data stream converting device and data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of data stream converting device which is suitable for an interleaving process and a deinterleaving process. SOLUTION: An address signal generating circuit 14 which generates write and read address signals A0 to A5 used when an interleaving process is performed by using a memory is equipped with selectors 30a to 30f which switch the output destinations of respective code bits M1 to M6 to respective code bits M1 to M6 generated by an M-sequence code generator 12. According to a select signal SEL, the settings of the selectors 30a to 30f are switched and the code bits M1 to M6 are rearrayed to generate two kind of address signals A0 to A5 for gaining memory access in mutually different order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data transmission system for transmitting digital data, and more particularly, to a data stream conversion device for implementing an interleaving process for reducing the effects of burst errors occurring during transmission.

[0002]

2. Description of the Related Art Conventionally, in a data transmission system for transmitting digital data, one of the methods used to enhance the encryption of data is to use a predetermined order for each unit block of a predetermined length. A method called interleaving for rearranging data is known.

[0003] In other words, the transmission data that has undergone the interleaving process cannot reproduce the original transmission data unless the deinterleaving process for rearranging the data following the reverse procedure is performed. For this reason, a third party who does not know what kind of interleave processing has been performed cannot reproduce the transmission data even if this data is received, and can increase the confidentiality.

It is also known that in a system for transmitting data using an error correction code, the error correction capability of the error correction code can be effectively used by applying interleave processing. That is, when the transmission side interleaves the data coded by the error correction code and transmits the data, even if a burst error occurs on the transmission path, the transmission side must deinterleave the transmitted data. For example, since the burst error is converted into a random error, the distribution of the error data after the deinterleave processing becomes dispersed, and the probability that the error data can be corrected by the error correction code increases.

[0005] As one of the methods for realizing the interleave processing, a method using a readable / writable memory (RAM) is known. For example, considering the case where interleave processing is performed using 64 bits as a unit block, an 8 × 8 size memory is prepared, and digital data to be transmitted is numbered 1 in the figure as shown in FIG. , 2, 3... Are written in the order along the horizontal direction. Then, the data written in this memory is
As shown in (b), the data written in the memory can be output in an order different from the order at the time of input by reading the data in the vertical direction in accordance with the numbers 1, 2, 3,... That is, the data before the interleave processing is represented by Di (i = 1, 2, 3,...
64), the data array after the interleave processing is D1, D9, D17,... D57, D2, D10
..., D56 and D64.

[0006] Such an interleaving process is as follows.
6 bits required to access the memory (2 ⁶ = 6
4) The address is divided into half column addresses and half row addresses, and row-column conversion is performed in which the column address is higher and the row address is lower when writing, and the row address is higher and the column address is lower when reading. Can be easily realized.

Although interleaving using this row-column conversion is effective against burst errors, periodic errors occur periodically due to, for example, fading of the transmission path of wireless communication. in case of,
Deinterleaving causes error data to be rather concentrated, and there is a problem that an error cannot be corrected even with an error correction code.

That is, in the transmission data sequence generated by the interleave processing using the above-mentioned row-column conversion, as shown in the following (1), a burst error "*"
(D36, D44, D52, D60) and a period error "#" (D0
9, D10, D11, D12). (1)
, Each of the data Di of the transmission data sequence is arranged side by side along D01, #, D17,... D57, D02, #, D18.
D56 and D64 are transmitted to the transmission line in this order (the same applies hereinafter).

D01, #, D17, D25, D33, D41, D49, D57, D02, #, D18, D26, D34, D42, D50, D58, D03, #, D19, D27, D35, D43, D51, D59 , D04, #, D20, D28, *, *, *, *, D05, D13, D21, D29, D37, D45, D53, D61, D06, D14, D22, D30, D38, D46, D54, D62, D07 , D15, D23, D31, D39, D47, D55, D63, D08, D16, D24, D32, D40, D48, D56, D64 (1) A transmission data sequence having the data array represented by (1) When the deinterleaving process is performed, a received data sequence having the data array shown in the following (2) is restored.

[0010] D01, D02, D03, D04, D05, D06, D07, D08, #, #, #, #, #, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24 , D25, D26, D27, D28, D29, D30, D31, D32, D33, D34, D35, *, D37, D38, D39, D40, D41, D42, D43, *, D45, D46, D47, D48, D49 , D50, D51, *, D53, D54, D55, D56, D57, D58, D59, *, D61, D62, D63, D64 (2) That is, the burst error "*" is dispersed, The error "#" is rather concentrated and the effect of the error correction code cannot be exhibited. This is because, in the row-column conversion, since the position of the interleaved data has periodicity, if a periodic error synchronized with this period occurs, the errors are concentrated at the time of deinterleaving.

On the other hand, Japanese Patent Application Laid-Open No. Hei 9-116444 uses a code generator for generating an M-sequence code and uses the generated M-sequence code as either a write address or a read address. An interleave device (hereinafter referred to as a conventional device) is disclosed.

That is, since the value of the M-sequence code changes at random, using this as an address eliminates periodicity in the access order, and it is possible to surely prevent concentration of periodic errors due to deinterleaving processing.

[0013]

By the way, this type of interleave processing is currently frequently used in mobile communication devices such as radio telephones, and therefore, the circuit for performing the interleave processing is required to be small. .

However, in the above-described conventional apparatus, two types of address circuits are required for performing the interleave processing: an address circuit for generating a sequentially incremented value as an address signal and an address circuit for generating an M-sequence code as an address signal. Since an address circuit is required, there is a problem that the circuit scale becomes large.

In the interleave processing, the access order at the time of writing to the same unit block is different from the access order at the time of reading. Therefore, normally, reading must be started unless all writing is completed. Can not do it. Therefore, in order to increase the processing speed by continuously processing the data of the unit block sequentially input,
It is necessary to alternately perform the write process and the read process such that two identical circuits are prepared and one performs the write process while the other performs the read process. Was more difficult.

The present invention has been made in order to solve the above problems.
A first object is to reduce the circuit scale of a data string conversion device used for interleave processing and deinterleave processing, and to further enable interleave processing to be performed continuously by a single data string conversion apparatus. This is a second object.

[0017]

According to a first aspect of the present invention, there is provided a data sequence conversion apparatus for achieving the above object.
ⁿ number (where, n: positive integer) as a unit block data has a memory for storing data of the unit block, the memory control means writes into the memory and sequentially inputs the data of the unit block At the same time, the data written in the memory is read out in a different order from that at the time of writing, whereby the arrangement of the input data sequence in the time axis direction is converted and output for each unit block.

In the memory control means, the M-sequence code generation means generates an n-bit width M-sequence code, and the address generation means arranges the arrangement of the M-sequence code in the bit width direction.
By performing conversion according to a predetermined conversion pattern, an address signal used for writing and reading data to and from the memory is generated. Then, the switching control unit switches the conversion pattern in the address generation unit so that the address signal generated by the address generation unit is different between the time of writing and the time of reading data of the same unit block.

As described above, in the data string conversion apparatus of the present invention, since the interleaving process is performed using the M-sequence code having no periodicity, the replacement of the data string becomes complicated, and the privacy characteristic of the data in the transmission path is increased. Not only burst errors, but also periodic errors as well as burst errors are converted into random errors during deinterleaving, so that no matter what error occurs on the transmission line, the error correction code always has Can be used effectively.

In the data string conversion device of the present invention, M
By converting the arrangement of the sequence code in the bit width direction,
Since two types of address signals for writing and reading are generated, only a single M-sequence generating means needs to be provided to generate the address signal, and the circuit scale can be reduced.

It is to be noted that the switching control means is configured to write the first conversion pattern generated by the first conversion pattern at the time of writing.
A first replacement pattern using a second address signal generated by a second conversion pattern different from the first conversion pattern at the time of reading using the address signal;
A configuration may be employed in which an address signal is used and the second replacement pattern using the first address signal at the time of reading is alternately applied to each unit block.

In this case, the exchange of data strings becomes more complicated, and the confidential characteristics of data on the transmission path can be further improved. Further, in this case, the read address applied for reading data of the unit block stored in the memory is the same as the write address applied for writing data of the subsequent unit block. Therefore, each time the memory control unit accesses each address of the memory, the memory control unit continuously reads the data stored in the memory and writes the data in the subsequent unit block. It can be configured to do so.

That is, the interleaving process for each unit block is performed by reading and writing on a single memory instead of starting writing of the next unit block after waiting for completion of reading of the previous unit block. Can be performed in parallel, so that the processing can be speeded up without increasing the size of the configuration.

When configuring a data transmission system for performing interleave processing on transmission data, the data string conversion apparatus according to any one of claims 1 to 3 may be configured to use An interleave device that converts an array and generates transmission data to be transmitted to a transmission line, and a deinterleave device that converts an array of transmission data obtained through the transmission line and restores the transmission data It can be suitably used.

Next, in the data string conversion device according to the fifth aspect, similarly to the device according to the first aspect, 2 ⁿ pieces (where n:
(Positive integer) as a unit block, and has a memory for storing the data of the unit block. The memory control means sequentially inputs and writes the data of the unit block to the memory, and writes the data to the memory. By reading the data in a different order from that at the time of writing, the arrangement of the input data string in the time axis direction is converted and output for each unit block. However, the configuration of the memory control means is different from that of the first embodiment.

That is, according to the present invention, the M-sequence code generation means generates an n-bit width M-sequence code as an address signal used for writing and reading data to and from the memory, and the inversion means generates the M-sequence code generation means. Output at least one specific bit in the bit string of the address signal generated by the inversion or non-inversion. Then, the switching control unit switches the setting of the inversion and non-inversion of the specific bit by the inversion unit between the time of writing and the time of reading the data of the same unit block.

As described above, in the data sequence conversion device according to the fifth aspect, the interleaving process is performed using the M-sequence code having no periodicity. And the effective use of the correction capability of the error correction code.

In the data string conversion device according to the present invention, the address signal for writing and reading is switched by switching between inversion and non-inversion of a specific bit of the M-sequence code. In order to generate a signal, only a single M-sequence generating means may be provided. As an inverting means for arbitrarily switching between inversion and non-inversion of a specific bit, for example, an exclusive OR (XOR) circuit is used. Since the configuration can be simplified by utilizing the configuration and the configuration for switching the address signal can be simplified, the circuit scale can be further reduced.

As described in the sixth and seventh aspects, the data string conversion apparatus according to the fifth aspect can apply the same configuration as that of the second and third aspects to the apparatus according to the first aspect. Therefore, in this case, the same effects as those of the second and third aspects can be obtained.

When configuring a data transmission system for performing interleave processing on transmission data, the data string conversion apparatus according to any one of claims 5 to 7 may be configured to transmit the data stream by using An interleave device that converts an array and generates transmission data to be transmitted to a transmission line, and a deinterleave device that converts an array of transmission data obtained through the transmission line and restores the transmission data It can be suitably used.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing the overall configuration of a data transmission system according to this embodiment.

As shown in FIG. 1, the data transmission system 1 of this embodiment converts an information data sequence Df into a transmission data sequence Df.
a transmitter 3 that converts the signal into a signal d and transmits the signal to the transmission line L;
And a receiver 7 for restoring the original information data sequence Df from the transmission data sequence Dd received via the.

The transmitter 3 transmits the information data sequence D
encoder 4 for encoding the data of f by the error correction code, and a transmission data sequence D output from the encoder 4
An interleaver 5 is provided that divides s into unit blocks (64 bits in this embodiment) and rearranges the data arrangement order along the time axis (hereinafter, referred to as interleave processing).

On the other hand, the receiver 7 replaces the transmission data sequence Dd received via the transmission line L with the data arrangement order along the time axis for each unit block (hereinafter, referred to as “interlacer 5”). , Deinterleaving process), and decoding the data of the received data sequence Dr output from the deinterleaver 8 and correcting any errors that can be corrected. A decoder 9 for restoring the provided information data sequence Df.

A well-known convolutional code or the like can be used as the error correction code. Therefore, since the encoder 4 and the decoder 9 for performing the encoding and decoding processes are also well-known, here, the Detailed description is omitted. The interleaver 5 corresponds to the data string converter of the present invention, and has a storage capacity for storing data for a unit block as shown in FIG. 2, and performs data transfer according to a read signal RD and a write signal WR described later. (RAM) 10 which can freely read and write data, and a clock signal CL which will be described later.
K, an M-sequence code generator 12 as M-sequence code generation means for generating an M-sequence code M (M1 to M6) having a 6-bit width based on the reset signal RST;
Generates the address signals A0 to A5 used when writing data to the memory 10 or reading data from the memory 10 according to a selection signal SEL described later, based on the M-sequence code M (M1 to M6) generated by Signal generation circuit 1 as an address generation means for supplying to memory 10
4 and the clock signal C supplied to the M-sequence code generator 12
LK, reset signal RST, address signal generation circuit 14
And a control circuit 16 as a switching control means for generating a selection signal SEL to be supplied to the interleaver 5 and a read signal RD and a write signal WR to be supplied to the memory 10 and controlling the operation of the entire interleaver 5.

Of these, the M-sequence code generator 12
As shown in (a), six flip-flop (FF) circuits 2 connected in series that operate according to a clock CLK.
0a to 20f. And the last stage (6th stage)
Output of the FF circuit 20f of the first stage (first stage)
The FF circuit 20e at the fifth stage and the FF circuit 20f at the sixth stage
An XOR circuit 22 for obtaining an exclusive OR (XOR) of the outputs of the two FF circuits 20e and 20f is provided between the FF circuits 20e and 20f.
0f is input. In the following, the outputs of the FF circuits 20a to 20f are denoted by A to F, and when they are collectively indicated, they are denoted by {ABCDEF}.

That is, the M-sequence code generator 12
As shown in (b), the generator polynomial Pn (X) = X ⁶ + X ⁵ +
It is configured to generate 6-bit wide M-sequence codes A to F represented by 1. In the M-sequence code generator 12 configured as described above, all F
When the outputs of the F circuits 20a to 20f are set to 0, the output does not change even if the clock CLK is input, and
If any one of the outputs of the F circuits 20a to 20f is set to 1, {ABCD
EF} = {000001} to {111111} are repeatedly output as 63 (2 ⁶ -1) codes.

However, in order to generate the address signal to be supplied to the memory 10, it is necessary to generate 64 codes including {000000}. Therefore, in the M-sequence code generator 12 in the present embodiment, the reset signal RS
By T, the fifth stage FF circuit 20e is preset,
The other FF circuits 20a to 20d, 20f are set so as to be reset (that is, {ABCDEF} = {000010}) (not shown), and the fifth-stage FF circuit 2
An XNOR circuit 24 for obtaining a negative exclusive OR (XNOR) between the output E of the output signal 0e and the reset signal RST is provided, and the outputs A to D of the FF circuits 20a to 20d and 20f are provided.
F and the output E ′ of the XNOR circuit 24
2 output M ({M1, M2, M3, M4, M5, M6}
= {A, B, C, D, E ', F}).

Here, FIG. 4 shows the M
FIG. 9 is a timing chart illustrating an operation of the sequence code generator 12,
The following operation is performed according to the clock signal CLK and the reset signal RST which becomes the Low level (RST = 0) only for a period of one clock every 64 clocks.

That is, during the period when the reset signal RST is at the low level, the outputs of the FF circuits 20a to 20f output the signals {ABC
DEF} = {000010}, but at this time, XNO
Since the output of the R circuit 24 becomes {0} (Low level),
After all, the output of the M-sequence code generator 12 is M (M1 to M1).
M6) = {000000}.

After one clock period has elapsed, the reset signal RST is set at the rising timing of the next clock.
Become high level, the FF circuits 20a to 20e latch the output of the previous stage, respectively, and the FF circuit 20f of the final stage.
Latches the output {1} of the XOR circuit 22. Also,
When the reset signal RST becomes High level, the XNOR circuit 24 outputs the output E of the FF circuit 20e as it is, so that the output of the M-sequence code generator 12 eventually becomes M =
{000001}, and thereafter, the output changes at each rising timing of the clock signal CLK and M = {00
63 types of M-sequence codes other than 0000 ° are output.

When 64 kinds of codes M = {000000} to {111111} are output during the 64 clocks, the reset signal is again generated for one clock period at the next rising edge of the clock signal CLK. R
ST goes to the Low level, and thereafter, the above operation is repeated.

Next, the address signal generation circuit 14
As shown in the figure, for each of the bits M1 to M6 of the code output M input from the M-sequence code generator 12, six selectors 30a to 30f for switching the output destination of each bit M1 to M6 according to the selection signal SEL. It has.

Specifically, the selector 30a outputs the sign bit M1 to the line of the address signal A5 or A2,
The selector 30b outputs the sign bit M2 to the address signal A4.
Alternatively, the selector 30c outputs the sign bit M3 to the address signal A3 or A1 line, the selector 30d outputs the sign bit M4 to the address signal A2 or A4 line, and the selector 30e outputs The sign bit M5 is output to the line of the address signal A1 or A0, and the selector 30f outputs the sign bit M6 to the line of the address signal A0 or A3.

That is, when the selection signal SEL is set to a level corresponding to writing to the memory 10 (Low level in this embodiment), .DELTA.A5, A4, A3, A2, A
1, A0} = {M1, M2, M3, M4, M5, M6}
On the other hand, when the selection signal SEL is set to a level (High level in this embodiment) corresponding to reading from the memory 10, ｛A5, A4, A3, A2, A1, A
Address signals A0 to A5 are obtained by converting the bit arrangement of the code output M so that 0 = {M2, M4, M6, M1, M3, M5}.

That is, {A5, A4, A3} is a column address, {A2, A1, A0} is a row address, and a storage area on the memory 10 for storing data of a unit block (64 bits) is a column address. When the data (transmission data sequence Ds) is written in the memory 10 in the format of 8 bits × 8 bits specified by the row address, the access order indicated by 1 to 64 in FIG. The reading of the data (transmission data sequence Dd) from the memory 10 is performed according to the access order β shown by 1 to 64 in FIG. 6B.

FIG. 7 is a timing chart showing the signals CLK, RST, SEL, RD, WR generated by the control circuit 16 and the operation of each section of the interleaver 5. FIG.
As shown in the figure, the control circuit 16 resets the reset signal RST, which becomes the Low level for one clock period every 64 clocks,
The selection signal SEL whose signal level is inverted at the falling timing of the reset signal RST, and the write signal WR and the selection signal SEL output at the same timing as the clock CLK while the selection signal SEL is at the Low level (hereinafter referred to as a writing period). During the high level (hereinafter referred to as a reading period), the read signal RD output at the same timing as the clock CLK is generated.

Thus, in the writing period, address signals A0-A whose address values change in accordance with access order α.
5, data for a unit block of the transmission data sequence Ds supplied from the encoder 4 (see FIG. 8A).
Are sequentially written into the memory 10 at the rising timing of the write signal WR (see FIG. 8B).

In the subsequent read period, data stored in the previous write period is read from memory 10 based on address signals A0 to A5 whose address values change in accordance with access order β, and the read data is read out. , Read signal R
It is latched at the rising timing of D and sent out to the transmission line L (see FIG. 8C).

Next, the de-interleaver 8 sets the selection signal SEL for controlling the address signal generation circuit 14 to the Low level at the time of reading, contrary to the above-described interleaver 5,
Other than being set to the high level at the time of writing, that is, writing data (transmission data series Dd) to the memory 10 in accordance with the access order β, and reading data (reception data series Dr) from the memory 10 Is performed in accordance with the access order α, except that the above-described interleaver 5 is used.

Therefore, in the writing period, the transmission data sequence Dd received via the transmission path L is based on the address signals A0 to A5 whose address values change in accordance with the access order β.
(See FIG. 8C) are sequentially written to the memory 10 at the rising timing of the write signal WR (see FIG. 8B). In the subsequent read period, data stored in the previous write period is read from the memory 10 based on the address signals A0 to A5 whose address values change in accordance with the access order α, and the rising timing of the read signal RD And supplied to the decoder 9 (see FIG. 8A).

Here, in the transmission data sequence Dd shown in FIG. 8C, as shown in FIG.
(D62, D11, D24, D43) and burst error "*"
It is assumed that (D04, D30, D51, D03) has occurred. D01, #, D57, D28, D10, D08, D07, D22, D44, #, D05, D39, D36, D47, D15, D54, D16, #, D34, D12, D46, D06, D18, D23, D09, #, D14, D29, *, *, *, *, D52, D37, D21, D48, D19, D49, D20, D53, D50, D38, D45, D25, D26, D35, D27, D13, D42, D58, D 55, D 59, D 56, D 17, D 31, D 40, D 32, D 41, D 33, D 63, D 60, D 64, D 61, D 02 (3) Received data sequence generated by deinterleaving this with deinterleaver 8 In the case of Dr, the periodic error “#” and the burst error “*” are sufficiently dispersed without being concentrated as shown in (4). Then, the received data sequence Dr is
Will be supplied.

D01, D02, *, *, D05, D06, D07, D08, D09, D10, #, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, # , D25, D26, D27, D28, D29, *, D31, D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, #, D44, D45, D46, D47, D48, D49 , D50, *, D52, D53, D54, D55, D56, D57, D58, D59, D60, D61, #, D63, D64 (4) As described above, the data transmission system 1 of the present embodiment
, The interleaver 5 and the deinterleaver 8
Generates an address signal A0 to A5 using an M-sequence code M (M1 to M6) having no periodicity, and writes and reads data to and from the memory 10 using the address signal, thereby performing an interleave process. , And a deinterleave process.

Therefore, the data transmission system 1 of the present embodiment
In this case, the data sequence exchange in the interleaving process becomes complicated as compared with the row-column conversion, so that not only a high privacy characteristic on the transmission path L can be realized, but also a burst generated on the transmission path L during deinterleaving. Since both errors and periodic errors are converted into random errors, the correction capability of the error correction code can always be used effectively.

Further, in the data transmission system 1 of the present embodiment, the interleaver 5 and the deinterleaver 8 convert the bit arrangement of the code M generated by the single M-sequence code generator 12 so that Since the write and read address signals A0 to A5 are generated, the circuit scale can be reduced as compared with a conventional device that requires different address circuits for write and read.

In this embodiment, writing in the interleaver 5 is performed in accordance with the access order α and reading is performed in accordance with the access order β, and writing in the deinterleaver 8 is performed in accordance with the access order β and reading is performed in accordance with the access order α. On the contrary, as shown in FIG. 9, writing in the interleaver 5 is performed in accordance with the access order β and reading is performed in accordance with the access order α, and writing in the deinterleaver 8 is performed in the access order α and reading is performed. It may be performed according to the order β.

In this embodiment, the M-sequence code generator 1
2 is configured to obtain the reset signal RST from the control circuit 16, and the output of each of the FF circuits 20a to 20f is a specific pattern (here, {ABCDEF} = {00
0010}), the reset signal RST may be generated inside the M-sequence code generator 12 by adding a circuit that generates a reset signal RST that becomes Low level for the next one clock.

Further, in the present embodiment, the address signal generation circuit 14 generates the signals {A5, A4,
A3, A2, A1, A0} = {M1, M2, M3, M
4, M5, M6} or {M2, M4, M6, M1, M
Although the bit arrangement of the code M generated by the M-sequence code generator 12 is exchanged so as to be 3, M5}, the present invention is not limited to this, and the bit arrangement may be exchanged in any manner. Second Embodiment Next, a second embodiment will be described.

In the data transmission system of this embodiment, the write signal WR and the read signal RD generated by the control circuits 16 of the interleaver 5 and the deinterleaver 8 are different from each other. The configuration is exactly the same except that the method of applying the access order used when reading data from the memory 10 is different, so that the description will focus on the different parts of this configuration.

That is, in this embodiment, the interleaver 5
And the control circuit 16 of the deinterleaver 8 has the same configuration, and as shown in FIG.
A write signal WR having a Low level period of １ ／ cycle of LK and rising at the rising timing of the clock CLK and a read signal RD rising at the falling timing of the clock CLK are generated.

In the first period in which the selection signal SEL is at the low level, based on the address signals A0 to A5,
Access to the memory 10 is performed according to the access order α. The address values of the address signals A0 to A5 are held for one clock period.
The data read from the memory 10 is a read signal RD
At the rising timing of the write signal WR and transmitted to the transmission line L (in the case of the interleaver 5) or the decoder 9 (in the case of the deinterleaver 8), and the subsequent write signal WR
At the rising timing of the transmission data sequence Ds supplied from the encoder 4 (in the case of the interleaver 5) or the data of the transmission data sequence Dd supplied from the transmission path L (in the case of the deinterleaver 8) are written into the memory 10. .

In the second period in which the selection signal SEL is at the high level, the access to the memory 10 is performed in accordance with the access order β based on the address signals A0 to A5, and is exactly the same as in the first period. Operate. As a result, the data DA01 to DA64 of the unit block written in the memory 10 during the first period are read out from the memory 10 during the subsequent second period, and are also stored in the memory 10 during the second period. DB of unit block written to
01 to DB64 are read from the memory 10 during the following first period.

That is, in the interleaver 5 and the deinterleaver 8 in the present embodiment, when writing and reading data to and from the memory 10,
A first replacement pattern for reading in the access order β and a second replacement pattern for writing in the access order β and reading in the access order α are applied alternately for each unit block. In addition, the reading of the preceding unit block and the writing of the succeeding unit block are performed in parallel within the same period.

However, for the unit block to which the first replacement pattern is applied by the interleaver 5, the second replacement pattern is applied by the deinterleaver 8, and conversely, the second block is applied by the interleaver 5. The deinterleaver 8 operates to apply the first replacement pattern to the unit block to which the replacement pattern is applied. As described above, according to the data transmission system 1 of the present embodiment, the interleaver 5 and the deinterleaver 8 use the M-sequence code M generated by the single M-sequence code generator 12, respectively. Address signals A0 to A5 are generated, and the address signals A0 to A5 are generated.
By controlling the access order of the memory 10 by using .about.A5, the interleave processing and the deinterleave processing are realized, so that the same effect as in the first embodiment can be obtained.

Further, according to the data transmission system 1 of the present embodiment, two types of replacement patterns having different data arrangements after the interleaving processing are alternately applied to each unit block. The arrangement of the above transmission data series becomes more complicated, and the confidential characteristics of data on the transmission path L can be further improved.

In the data transmission system 1 of this embodiment, two types of replacement patterns are alternately applied to each unit block, so that the reading of the preceding unit block and the succeeding unit block are performed in the same access order. Since the writing of the unit block is performed in parallel in the same period on the same memory 10, the interleaver 5 and the deinterleaver 8 can be duplicated without increasing the device configuration. Thus, the processing speed can be increased. Third Embodiment Next, a third embodiment will be described.

The data transmission system of this embodiment has the same configuration as that of the first embodiment except that the configuration of the address signal generating circuit 14 of the interleaver 5 and the deinterleaver 8 is different. The following description focuses on the differences. That is, in the present embodiment, the address signal generation circuit 14a converts the code bits M1, M2, M3, M5, and M6 of the code output M input from the M-sequence code generator 12 as shown in FIG. It is configured to output the address signals A5, A4, A3, A1, and A0 respectively to the lines.

The code bit M4 is output to the line of the address signal A2 via the XOR circuit 32 which outputs an exclusive OR with the selection signal SEL. That is, the signal level of the address signal A2 is inverted between when the selection signal SEL is at a high level and when it is at a low level.

Then, the storage area on the memory is defined as $ A5, A
4, A3}, {A2, A1, A
8 bits × 8 specified by row address consisting of 0 $
When expressed in a bit format, the address signal generation circuit 14
a generates the address signals A0 to A5
When L is at the Low level, the access order α indicated by 1 to 64 in FIG. 12A is realized, while the selection signal SEL is
At the time of the High level, the access order γ shown by 1 to 64 in FIG. 12B is realized.

In this embodiment, in the interleaver 5, writing of data to the memory 10 is performed in the access order α.
And the data read is performed in the access order γ. On the other hand, the deinterleaver 8
Data writing to 0 is performed in the access order γ, and data reading is performed in the access order α.

The control circuit 16 operates exactly the same as the first embodiment described above with reference to the timing chart of FIG. 7, except that the access order is different. However, in the deinterleaver 8, the selection signal SEL is set to a low level at the time of reading and to a high level at the time of writing, contrary to the case of the interleaver 5 shown in the figure.

Thus, in interleaver 5,
In the writing period, the encoder 4 is controlled based on address signals A0 to A5 whose address values change in accordance with the access order α.
The data (see FIG. 13A) for the unit block of the transmission data series Ds supplied from the memory is sequentially written into the memory 10 at the rising timing of the write signal WR (see FIG. 13B). In the subsequent reading period, the address signal A0 whose address value changes in accordance with the access order γ
A5, the data stored during the previous writing period is read from the memory 10, and the read data is
Latched at the rising timing of the read signal RD,
It is transmitted to the transmission line L (see FIG. 13C).

On the other hand, in the deinterleaver 8, in the writing period, based on the address signals A0 to A5 whose address values change in accordance with the access order γ, the unit data of the transmission data sequence Dd received via the transmission line L is used. Data (see FIG. 13C) is sequentially written to the memory 10 at the rising timing of the write signal WR (FIG. 13).
(B)). In the subsequent readout period, address signals A0 to AA whose address values change in accordance with the access order α
5, the data stored in the previous writing period is read from the memory 10, latched at the rising timing of the read signal RD, and supplied to the decoder 9 (FIG. 13).
(See (a)).

Here, in the transmission data sequence Dd shown in FIG. 13C, as shown in (5), a periodic error "#" (D33, D48, D25, D08) and a burst error "*" ( D46, D59, D28, D16). D62, #, D42, D05, D04, D43, D22, D26, D11, #, D09, D40, D24, D54, D45, D32, D53, #, D23, D41, D34, D07, D19, D13, D18, #, D49, D31, *, *, *, *, D02, D21, D44, D55, D51, D58, D47, D12, D20, D03, D06, D35, D15, D29, D39, D10, D27, D60, D37, D64, D17, D14, D36, D61, D63, D38, D30, D50, D56, D01, D57, D52 (5) Reception data generated by deinterleaving the deinterleaver 8 In the sequence Dr, the periodic error “#” and the burst error “*” are sufficiently dispersed without being concentrated as shown in (6). Then, the received data sequence Dr is supplied to the decoder 9.

D01, D02, D03, D04, D05, D06, D07, #, D09, D10, D11, D12, D13, D14, D15, *, D17, D18, D19, D20, D21, D22, D23, D24 , #, D26, D27, *, D29, D30, D31, D32, #, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, *, D47, D48, D49 , D50, D51, D52, D53, D54, D55, D56, D57, D58, *, D60, D61, D62, D63, D64 (6) As described above, the data transmission system 1 of this embodiment
, The interleaver 5 and the deinterleaver 8
Generates address signals A0 to A5 using the M-sequence code M generated by the single M-sequence code generator 12, and controls the access order of the memory 10 using the address signals A0 to A5. As a result, the interleave processing and the deinterleave processing are realized.
The same effects as in the embodiment can be obtained.

Further, in the data transmission system 1 of the present embodiment, the address signal generating circuit 14a has a very simple configuration consisting of one XOR circuit 32. The size can be reduced. In this embodiment, the address signal A2 is selected according to the selection signal SEL.
However, the present invention is not limited to this, and any address signal may be inverted, or two or more address signals may be simultaneously inverted.

Further, the code output M of the M-sequence code generator 12
When generating the address signals A0 to A5 from, the replacement of the bit arrangement of the code output M and the inversion of the specific bit may be performed in combination. Further, a first replacement pattern in which data is written to the memory 10 in the access order α and reading is performed in the access order γ, and writing of data to the memory 10 is performed in the access order γ and reading is performed in the access order α In the same manner as in the second embodiment, these two types of replacement patterns are alternately applied to each unit block, and the reading of the preceding unit block and the writing of the succeeding unit block are performed. May be performed on the same memory 10 in parallel within the same period.

In this embodiment, the first replacement pattern is applied to the interleaver 5 and the second
However, the combination of the first replacement pattern and the second replacement pattern can be arbitrarily set. That is, in addition to the combination of applying the second replacement pattern to the interleaver 5 and applying the first replacement pattern to the deinterleaver 8, the same first replacement pattern or the second replacement pattern is used for the interleaver 5 and the deinterleaver 8. May be used.

That is, in the first and second embodiments, if the application order of the two types of access order αβ is reversed between the interleaver 5 and the deinterleaver 8, the data cannot be correctly restored, and It is necessary to synchronize the switching of the selection signal SEL in units of the two unit blocks described above. However, in this embodiment, the order in which the two types of access order αγ are applied may be arbitrary. It is sufficient to synchronize the switching of the signal SEL, and the control can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a data transmission system according to an embodiment.

FIG. 2 is a block diagram illustrating a configuration of an interleaver and a deinterleaver.

FIG. 3 is a circuit diagram illustrating a detailed configuration of an M-sequence code generator.

FIG. 4 is a timing chart showing the operation of the M-sequence code generator.

FIG. 5 is a circuit diagram illustrating a detailed configuration of an address signal generation circuit.

FIG. 6 is an explanatory diagram showing an access order by an address signal generated by the address signal generation circuit shown in FIG. 5;

FIG. 7 is a timing chart illustrating the operation of each unit of the interleaver.

FIG. 8 is an explanatory diagram illustrating a state in which a data array is converted by an interleave process and a deinterleave process.

FIG. 9 is an explanatory diagram illustrating a state in which a data array is converted by an interleave process and a deinterleave process.

FIG. 10 is a timing chart illustrating the operation of each unit of the interleaver in the second embodiment.

FIG. 11 is a circuit diagram illustrating a detailed configuration of an address signal generation circuit according to a third embodiment.

12 is an explanatory diagram showing an access order based on an address signal generated by the address signal generation circuit shown in FIG.

FIG. 13 is an explanatory diagram illustrating a state in which a data array is converted by an interleave process and a deinterleave process.

FIG. 14 is an explanatory diagram for describing interleaving processing using row-column conversion.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data transmission system 3 ... Transmitter 4 ... Encoder 5 ... Interleaver 7 ... Receiver 8 ... Deinterleaver 9 ... Decoder 10 ... Memory 12 ... M-sequence code generator 14, 14a ... Address signal generation circuit 16 ... Control circuit 20a to 20f: flip-flop (FF) circuit 22, 32: XOR circuit 24: XNOR circuit 30a to 30f: selector L: transmission line

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (8)

[Claims] 1. A memory for storing 2 ⁿ (where n: a positive integer) data is a unit block, storing data for the unit block, and sequentially inputting and writing data of the unit block to the memory. A memory control means for reading data written in the memory in an order different from that at the time of writing; and a data sequence for converting an input data sequence in a time axis direction and outputting the data sequence for each of the unit blocks. In the conversion device, the memory control means may be a predetermined M-sequence code generation means for generating an M-sequence code having an n-bit width, and an arrangement of the M-sequence codes generated by the M-sequence code generation means in a bit width direction. Address generating means for generating an address signal used for writing and reading data to and from the memory by performing conversion in accordance with the converted conversion pattern; Address signal generated Te data string conversion device comprising a switching control means for switching the converted pattern Ile so each other in the writing time and reading, that consists for data of the same unit block. 2. The data string conversion device according to claim 1, wherein said switching control means uses a first address signal generated by a first conversion pattern at the time of writing, and said first address signal at the time of reading. A first replacement pattern that uses a second address signal generated by a second conversion pattern different from the conversion pattern; and a second replacement pattern that uses the second address signal during writing and uses the first address signal during reading. A data string conversion apparatus, wherein the replacement pattern is alternately applied to each unit block. 3. The data string conversion device according to claim 2, wherein the memory control means reads data stored in the memory and reads data of a subsequent unit block every time each address of the memory is accessed. A data string conversion apparatus, wherein writing of data is performed continuously. 4. An interleave device for converting an array of transmission data to generate transmission data to be transmitted to a transmission line by using the data sequence conversion device according to claim 1; A data transmission system, wherein the data transmission system is used as a deinterleave device for converting an array of transmission data obtained through the transmission and restoring the transmission data. 5. A memory for storing 2 ⁿ (where n: a positive integer) data is a unit block, a memory for storing the data for the unit block, and sequentially inputting and writing the data for the unit block to the memory. And a memory control means for reading data written in the memory in an order different from that at the time of writing. The memory control means generates an M-sequence code having an n-bit width as an address signal used for writing and reading data to and from the memory.
Sequence code generating means; inverting means for inverting or non-inverting and outputting at least one specific bit in the bit sequence of the address signal generated by the M-sequence code generating means; A data string conversion device, comprising: switching control means for switching between inversion and non-inversion of the specific bit by the inversion means at the time of writing and at the time of reading. 6. The data string conversion device according to claim 5, wherein the switching control means uses a first address signal generated by non-inverting the setting of the specific bit at the time of writing, and uses the first address signal generated at the time of reading. A first replacement pattern that uses a second address signal generated by inverting the setting of a specific bit; and a second replacement pattern that uses the second address signal during writing and uses the first address signal during reading. Are applied alternately for each of the unit blocks. 7. The data sequence conversion device according to claim 6, wherein the memory control means reads data stored in the memory and reads data of a subsequent unit block every time each address of the memory is accessed. A data string conversion apparatus, wherein writing of data is performed continuously. 8. An interleave device for converting a data stream conversion device according to claim 5 into an array of transmission data and generating transmission data to be transmitted to a transmission line, and A data transmission system, wherein the data transmission system is used as a deinterleave device for converting an array of transmission data obtained through the transmission and restoring the transmission data.