JP2000306391A - Method for erasure of electrically erasable memory cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the durability for erasing memory by applying a first voltage of a first polarity to a first-conductivity-type well. a second voltage, of the first polarity, which is by a specific value or higher larger than the first voltage in terms of an absolute value, to a second-conductivity-type drain region, and a third voltage of a second polarity to a control gate. SOLUTION: A memory device 10 is provided with an erasure circuit which selectively erases a memory cell by applying a prescribed voltage. A first voltage of a first polarity is supplied to a P-well 16 by a switch block 30a. The first voltage is a positive voltage. In the P-well 16, a P+ region 34 is formed so that the first voltage is supplied to the P-well 16. A second voltage of the first polarity is set at a voltage which is by at least 2 V larger than the first voltage in terms of an absolute value, and it is supplied to a drain region 21. The second voltage is a positive voltage, and it is supplied by a bias power supply and a switch block 30b. A third voltage of a second polarity is a negative voltage, and it is supplied by a switch block 30c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory and a device incorporating such a memory, and more particularly to a method of manufacturing an electrically erasable read only memory (EEPROM) and an erasing method thereof.

[0002]

2. Description of the Related Art Non-volatile memories are used in various products because of their characteristics of retaining information even when power is not supplied. Electrically erasable programmable read only memory (EEPROM)
Is a type of non-volatile memory whose contents can be erased and different data stored. Flash memory has an EE where programming or erasing is performed on a sector-by-sector basis rather than at the individual cell level.
It is a kind of PROM. Flash memories typically have better read access time characteristics than conventional EEPROMs.

A typical EEPROM device has a memory cell array, each cell having a floating gate and a control gate on the floating gate. The floating gate is disposed on a channel of the transistor defined between the source and drain regions formed on the semiconductor substrate. An insulator layer is interposed between the channel and the floating gate and between the floating gate and the control gate. One of the memory cell configurations is a so-called stack gate arrangement, in which a control gate is located immediately above a floating gate. Stack gate structures are described, for example, in US Pat. Nos. 5,077,691 and 5,598,36.
No. 9 is described.

Another configuration is a split gate arrangement, in which the control gate extends over the floating gate, but also extends to a region on the transistor channel horizontally adjacent to the floating gate. I have. For example, U.S. Pat. No. 5,867,425 describes a split-gate memory cell that includes a bipolar transistor whose collector is a biased depletion region below the channel of the sensing transistor. The selection transistor is configured adjacent to the sensing transistor. The source of the select transistor is the emitter of the bipolar transistor.

[0005] Programming of this type of memory cell involves:
It is usually performed by injecting electrons into the floating gate. Conversely, erasing is realized by extracting electrons from the floating gate by a tunnel current. Programming and erasing of flash memory impose conflicting requirements on semiconductor junctions in the memory. Steep junctions (abrupt junctions) increase programming speed, while smooth junctions (graded junctions) avoid hot hole injection during erase.
In the prior art, this problem has been addressed in stacked gate devices by using an approach of programming from the drain and erasing from the source. This approach typically adds cost because the source and drain regions must be individually optimized. Further, in a split gate device, the floating gate cannot be accessed from the source junction side and must be erased only from the drain side. This usually limits its endurance cycle performance. However, stacked gate flash memories are susceptible to "over-erase" which is not a problem with split gate devices.

[0006] EEPROMs are typically programmed by causing hot electron injection from the channel region near the drain to the floating gate. this is,
This is usually achieved by applying a relatively high voltage to the control gate with the source and substrate grounded, and then applying a moderately positive voltage to the drain to produce high energy or hot electrons. You. When the negative charge is accumulated in the floating gate, the threshold voltage of the field effect transistor increases, and the channel current at the time of reading is blocked. Of course, the value of the read current determines whether the cell is programmed or not.

At the time of erasing, the floating gate is discharged, and usually, Fowler-Nordheim (Fowler-Nordh) between the floating gate and the source or between the floating gate and the substrate.
eim) Performed by causing tunneling. Erasure caused by tunneling between the floating gate and the source due to tunneling is referred to as source erasure, in which the control gate and the substrate are grounded while applying a high positive voltage to the source, while the drain is left floating.

[0008] Erasure due to tunneling between the floating gate and the substrate is generally known as channel erasure. In channel erasing, a high positive voltage is applied to the substrate, the control gate is grounded, and the drain and source are left floating. Both of these prior art methods have various disadvantages.

Source erasing usually requires an external power supply for high voltages and requires a complex and expensive double diffused structure as the source. Source erasure leaves holes on the surface of the dielectric layer below the floating gate, reducing the reliability of programming. Channel erase operations are sensitive to defects in the channel because the entire channel is used for tunneling, resulting in a relatively wide distribution of thresholds for memory cells in the array. Channel erasing requires that a higher voltage be applied to the substrate than in source or drain erasing. Therefore, channel erasing is more difficult and optimizing high voltage processing for channel erasing is more costly.

The negative gate erase operation is generally realized by applying a positive voltage to the source region and applying a negative voltage to the control gate to ground the substrate and make the drain floating. Negative gate erasure requires a negative charge pumping circuit, and may also require a positive charge pumping circuit for the source voltage. Usually, a double diffused source structure is also required, and the threshold distribution is relatively wide.

[0011]

It is generally known that hot carrier generation induced by band-to-band tunneling (BBT) during erasing of a flash memory causes deterioration of a read current. Thus, reducing BBT leakage current during operation is one of the main goals in flash technology. Previous approaches to reduce this current include introducing a gentle junction, which does not increase the electric field at the junction to a level where BBT occurs. It is possible to use an erase voltage of the order of magnitude. However, this technique requires separate impurity ion implantation for the source and drain,
The cost increases and the channel length becomes longer.

US Pat. No. 5,867, supra to Wong.
No. 425 describes a triple well structure for a memory cell in which the innermost P-well, the surrounding N-well, and the drain region are biased to a positive voltage of Vcc or higher, while the control gate is connected to-. From 7-
Biased to a negative voltage in the range of 14V. The drain bias cannot be higher than the P-well bias by about 1 V or more to avoid the problem of the gate induced drain leakage current (GIDL). Thus, despite advances in the construction and erasing techniques of nonvolatile memory cells, there remains a need for methods of erasing nonvolatile memory cells and for ensuring that such nonvolatile memory cells have higher erase cycle endurance. Have been.

[Problems to be solved by the invention]

In view of the above, it is an object of the present invention to provide a method for erasing a memory while improving the erasing durability. Still another object of the present invention is to provide a method for forming a nonvolatile memory having high erase durability.

A method for erasing an electrically erasable memory cell according to the present invention has the features described in claim 1.

Further, the present invention has the features described in claim 2. Further, the present invention has the features described in claim 3. Further, the present invention has the features described in claim 4.
Further, the present invention has the features described in claim 6.

The present invention has the features described in claim 5, which can reduce the manufacturing cost. Furthermore, the present invention has the features described in claim 7. Alternatively, it has the characteristics described in claim 8 of the present invention.

The present invention has the features described in claim 9.

[0018]

FIG. 1 shows an electrically erasable memory device 10 having a stacked gate structure according to the present invention. Although the memory device 10 has a substrate 11 and a plurality of memory cells formed on the substrate, only a single memory cell 15 is illustrated for the sake of clarity. The memory cell 15 has a well 16 having the first conductivity type. In the embodiment shown,
The well 16 is an innermost well having a P-type conductivity and is surrounded by a second well having an N-type conductivity. In other words, the illustrated memory cell 15 has a triple well structure, and can be easily manufactured by a conventional semiconductor manufacturing technique, as will be easily understood by those skilled in the art. The triple well structure is used for the purpose that the innermost well 16 can be applied with an individual bias voltage different from that of the substrate 11 which is normally connected to the ground potential.

The memory cell 15 has a source region 20 of the second conductivity type, which is N-type in the illustrated embodiment.
And a drain region 21 formed separately therefrom. Source and drain regions 20, 21 define a channel 22 therebetween (shown in dashed lines), as will be readily understood by those skilled in the art. The floating gate 25 is formed above the channel 22, and the first insulating layer 24
Is disposed between the floating gate and the channel. The control gate 27 is formed on the floating gate 25, and the second insulator layer 26 extends between the control gate and the floating gate.

The memory device 10 has an erase circuit for selectively erasing at least one of the memory cells by applying a predetermined voltage as described below. The erasure circuit is schematically illustrated by three bias voltage sources and their associated switches 30a-30c. These bias sources may be implemented on-chip or by external circuitry or a combination thereof, as will be readily appreciated by those skilled in the art. One or more external input pins are provided for the entire integrated circuit package including the memory device according to the present invention, and are connected to corresponding pads of the integrated circuit for receiving external voltages.

In this embodiment, the switch is shown in the erase position. Accordingly, a first voltage having a first polarity is applied to the switch 30 associated with the bias source.
a to the well 16. The first voltage is a positive voltage in the range of approximately 2-3V. The well 16 has a P + region 34 for the purpose of supplying a first voltage to the well.
Are formed.

The second voltage having the first polarity is set to a value that is at least approximately 2 V larger than the first voltage in absolute value, and is supplied to the drain region 21. As shown, the second voltage is a positive voltage in the range of approximately 5 to 9V and is provided by the bias source and switch block 30b. In addition, a third voltage having a second polarity is applied to the control gate 27. The third voltage is a negative voltage in the range of approximately -5 to -8 volts and is provided by the third bias source and switch block 30c. As will be readily understood by those skilled in the art, the conductivity types of the various semiconductor regions can be reversed,
At that time, the polarities of various bias voltages also need to be inverted.

Further, as will be readily appreciated by those skilled in the art, the memory device 10 includes various programming voltages P1-P3 and read voltages R from corresponding bias sources and switch circuits 30a-30c, respectively.
1-R3 is applied. Therefore, no further discussion is needed on these voltages and associated circuitry.

In accordance with the salient features of the present invention, drain region 21 and source region 20 are symmetric, thereby reducing process costs. In addition, the drain region 21, more preferably both the source region 20 and the drain region 21, form a relatively steep junction with the adjacent part of the well. Therefore, the manufacturing process is simplified, and the cost is reduced as compared with, for example, a case where a gentle junction is used. Steep junctions and symmetries are made possible by the erasure techniques and circuits according to the present invention.

Next, referring to the schematic sectional view of FIG.
A split gate memory device according to the present invention formed in a digital signal processor 40 is described.
This split gate device includes a P-type substrate 41, an N-type well 47 formed in the substrate 41, and an N-type well 4.
7 has a P-type well 46 formed therein. The device further includes a source region 50 and a drain region 51 formed spaced therefrom, both of which have an N + conductivity type, as will be readily understood by those skilled in the art. are doing. Of course, channel 52 extends between source region 50 and drain region 51. P + region 64 is formed in the embodiment shown to provide a well bias voltage to well 46.

The floating gate 55 is disposed on the insulator layer 54, and the insulator layer 54 is disposed on a portion where the channel 52 exists. In this embodiment, the split gate cell extends horizontally over the floating gate 55 and over adjacent portions of the channel adjacent to and adjacent to the floating gate, as will be readily understood by those skilled in the art. It has a control gate 57.

In a split gate cell, access to the source is not possible. Therefore, the drain erase technique according to the present invention is very useful. In the illustrated embodiment, the erase circuit 60 is schematically illustrated as providing three different voltages during the erase period. Each of the first, second and third voltages is the same as described in connection with the aforementioned memory device 10 shown in FIG. Of course, these voltages may be generated on-chip by one or more charge pumping circuits or supplied from a separate external power source, as will be readily understood by those skilled in the art.

The erasing circuit 60 is connected to an on-chip processor 61 which is schematically shown. In other words, the memory device and the erase circuit may be included as part of an embedded memory in another device, such as digital signal processor 40, for example. Thus, as used herein, the term "memory device" refers to either a dedicated memory chip or an integrated circuit such as a digital signal processor that incorporates the memory cells and erase circuit according to the present invention.

As will be readily appreciated by those skilled in the art, various programming and read bias voltages are applied to the associated circuitry. In addition, the erasing circuit 60 provides a group of memory cells, ie,
These groups of memory cells or memory cell sectors can be connected for the purpose of erasing them all at once, in which case, for example, the memory device is a flash EEPROM.

The first, second and third erase voltages according to the present invention reduce inter-band tunneling (BBT) caused by hot carrier generation during the erase operation. In the past, attempts have been made to address this BBT leakage by smoothing the source and drain junctions, but only with the undesirable consequence of increasing process steps and costs. The channel or well erase technique has the disadvantage of requiring a relatively high well voltage, which required special treatment. For split gate devices, well erasure resulted in oxide breakdown.
The poly-poly erase technique requires an additional polysilicon layer or sharp corners, which compromises the reliability of the memory cell. The erasure technique according to the present invention overcomes these disadvantages of the prior art.

The present invention is based on the observation that the coupling coefficient between the drain and the floating gate is usually much smaller than the coupling coefficient between the well and the floating gate. For example,
The coupling coefficient between the drain and the floating gate is about 0.1, and the coupling coefficient between the well and the floating gate is about 0.3. Thus, if both the drain and well voltages are increased by the same amount, the voltage difference between the drain and the floating gate increases, as shown in FIG. Here, V_tun_ox is the potential difference between both ends of the tunnel oxide film, Vw is the well voltage, and the value obtained by subtracting the well voltage from the drain voltage Vd is equal to 6.75V. This increases the erase speed, as shown in FIG.

In FIG. 4, the read current I_read is shown on the Y-axis in amperes, and the erase time T_erase is shown on the X-axis in milliseconds. Three plots are shown, with diamond plots for well bias of 0.0.
For V, the rectangular plot shows a well bias of 1.0V
And the triangle plots are for a well bias of 2.0V. The drain voltage is equal to 6.75V plus the respective well bias, and the control gate voltage is -5V for all plots.
As will be readily appreciated by those skilled in the art, the higher the well bias, the faster the erase speed.

The voltage difference between the drain and the floating gate can be kept constant by keeping the intrinsic floating gate voltage and the control gate voltage at constant values. This reduces the voltage between the drain and the well, as shown in FIG. The reduced drain-well voltage exponentially reduces the BBT current, as will be readily appreciated by those skilled in the art,
As a result, the deterioration of the cell read current is reduced.
By reducing this leakage current, the capacitance in the charge pumping circuit required for a single external power supply flash memory device, for example, is reduced.

For the purpose of verifying the above effects, split gate cells were fabricated using 0.35 micron flash technology and repeated write / erase cycles over 50,000 cycles under various drain and substrate voltages. Was done. The result is shown in FIG. Specifically, the bottom plots labeled C are from the prior art erase scheme, where the well voltage is 0V, the control gate is -5V, and the drain voltage is 6.75 V, and the erase time is 0.1 second. The plot labeled B has a well bias of 1 V, a drain voltage of 7.15 V, a control gate voltage of -5 V, and an erase time of 0.1 second as well. The plot group labeled A at the top has a well bias of 2V, a drain voltage of 8V, a control gate bias of -5V, and an erase time of 0.1 second.

In accordance with the present invention, the erase speed is improved by the effective erase voltage and a relatively high read cycle endurance is achieved. For example, it has been found that the first voltage applied to the well should be in the range of approximately 2 to 3 volts in absolute value. The second voltage applied to the drain is approximately 5 to 9 absolute
V is desirably in the range of V. Preferably, the third voltage applied to the control gate has a polarity opposite to the first and second voltages and is approximately 3 to 8 volts in absolute value.

The method according to the invention comprises applying a first voltage of a first polarity to the well, a second voltage having a first polarity at least about 2 V higher than the first voltage to the drain region, and a second voltage to the drain region. By simultaneously applying the third voltage to the control gates, the at least one electrically erasable memory cell is erased. More specifically, each memory cell has at least one of a well having a first conductivity type, source and drain regions having a second conductivity type formed apart from each other in the well and defining a channel therebetween, and a channel. A floating gate overlapping the portion, and a first insulator layer extending between the floating gate and the channel. The control gate desirably overlaps at least a portion of the floating gate, and a second insulator extends between the control gate and the floating gate.

[0037] Preferably, the first voltage supply step comprises the step of supplying a first voltage in the range of approximately 2 to 3 volts in absolute value. Preferably, the second voltage supply step comprises the step of supplying a second voltage in the range of approximately 5 to 9 V in absolute value. Further, it is preferable that the third voltage supply step includes a step of supplying a third voltage having an absolute value in a range of about 3 to 8V. Preferably, the first conductivity type is P-type, and the second conductivity type is N-type. Therefore, it is desirable that the first and second voltages are positive voltages,
Preferably, the third voltage is a negative voltage.

The drain and source regions are symmetric,
A relatively steep junction is formed with the well, thereby reducing manufacturing costs. Preferably, generating at least one of the first, second and third voltages comprises using a single or multiple charge pumping circuits. Alternatively, one or more of the first, second, and third voltages are supplied from an external power supply.

In another aspect of the invention, the invention relates to
The present invention relates to a method of manufacturing an electronic device having an electrically erasable memory. A method according to the invention includes forming a plurality of memory devices and draining a first voltage having a first polarity in a well, a second voltage having a first polarity and at least about 2V higher than the first voltage. In the area,
Forming an erase circuit for applying a third voltage having a second polarity to the control gate. The memory cell forming step preferably includes forming each cell in a well having a first conductivity type, and each memory cell is formed in the well and has a second conductivity type. Having source and drain regions spaced apart from each other defining a channel therebetween. Further, each cell includes a floating gate overlapping at least a portion of the channel, a first insulator layer extending between the channel and the floating gate, a control gate overlapping at least a portion of the floating gate, and a control gate. Formed by forming a second insulator layer extending between the gate and the floating gate.

The above description relates to one embodiment of the present invention, and those skilled in the art can consider various modifications of the present invention, but all of them are within the technical scope of the present invention. Is included.

[0041]

As described above, according to the present invention, an electrically erasable read only memory (EEPROM) having significantly improved read endurance characteristics is provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a stacked gate structure including a nonvolatile memory cell of an EEPROM and an associated erase circuit according to the present invention.

FIG. 2 is a cross-sectional view illustrating an embodiment of a split gate structure including a nonvolatile memory cell and an associated erase circuit of a digital signal processor according to the present invention.

FIG. 3 is a graph showing a relationship between a tunnel oxide film voltage and a well voltage when a drain-substrate voltage is kept constant according to the present invention.

FIG. 4 is a graph showing the relationship between read current and erase time in various bias arrangements according to the present invention.

FIG. 5 is a graph showing the drain voltage minus the well voltage as a function of the well voltage when the voltage applied to the tunnel oxide film is kept constant according to the present invention.

FIG. 6 is a graph showing the relationship between read current and erase cycle in various bias arrangements according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Electrically erasable memory device 11 Semiconductor substrate 15 Memory cell 16 P well 17 N well 20 Source region 21 Drain region 22 Channel 24 First insulator layer 25 Floating gate 26 Second insulator layer 27 Control gate 30 Bias power supply and switch Block 34 P + region 40 Digital signal processor 41 Semiconductor substrate 46 P well 47 N well 50 Source region 51 Drain region 52 Channel 54 First insulator layer 55 Floating gate 56 Second insulator layer 57 Control gate 60 Eraser circuit 61 Processor circuit 64 P + area

Continuation of front page (71) Applicant 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A. (72) Inventor Richard William Greger United States, 32789 Florida, Winter Park, Waterfall Lane 380 (72) Inventor Patrick J. Kelly United States, 32736 Florida, Orlando, Loose Court 10200 (72) Inventor Chun Wei Len United States, 32736 Florida, Orlando, Baycliff Court 9556 (72) Inventor Lambier Singh United States, 32819 Florida, Orlando, Sugar View Court 7867

Claims (26)

[Claims] A first conductive type well, a second conductive type source region and a drain region in the well, and a channel region therebetween; a first insulating layer on the channel region; Erasing an electrically erasable memory cell having a floating gate over the first insulating layer, a second insulating layer over the floating gate, and a control gate over the second insulating layer. The method comprises: (A) applying a first voltage of a first polarity to the well; and (B) applying a second voltage of a first polarity greater than the first voltage by 2V or more in absolute value to the drain region. And (C) applying a third voltage of a second polarity to the control gate. 2. A method of erasing an electrically erasable memory cell. 2. The method according to claim 1, wherein the absolute value of the step (A) is 2 to 2.
The method of claim 1, wherein a first voltage in the range of 3V is applied. 3. In the step (B), the absolute value is 5 to 5.
The method of claim 1, wherein a second voltage in the range of 9V is applied. 4. In the step (C), the absolute value is 3 to 3.
The method of claim 1, wherein a third voltage in the range of 8V is applied. 5. The method of claim 1, wherein the drain region and the source region are symmetric and define a sharp junction with the well. 6. The first conductivity type is a P type, and the second conductivity type is a P type.
The conductivity type is N-type, wherein the steps (A) and (B) apply positive first and second voltages, and the step (C) applies a negative third voltage. The method of claim 1, wherein: 7. The method of claim 1, further comprising the step of: (D) generating at least one of the first, second, and third voltages using a charge pump. 8. The method of claim 1, further comprising the step of: (E) receiving at least one of the first, second, and third voltages from an external source. 9. A method of manufacturing an electronic device including an electrically erasable memory, comprising: (A) forming a plurality of memory cells in a well of a first conductivity type; A source region and a drain region of two conductivity type and a channel region between them; a first insulating layer on the channel region; a floating gate on the first insulating layer; A second insulating layer, and a control gate on the second insulating layer, (B) applying a first voltage of a first polarity to the well,
Forming an erasing circuit for applying a second voltage of a first polarity greater than the voltage by 2 V or more to the drain region and applying a third voltage of the second polarity to the control gate. Method of manufacturing an electronic device including a possible memory. 10. The method according to claim 1, wherein the step (B) comprises:
10. The method of claim 9, wherein forming an erase circuit for applying a first voltage in the range of ~ 3V. 11. The method according to claim 1, wherein the step (B) comprises:
10. The method of claim 9 wherein forming an erase circuit for applying a second voltage in the range of ~ 9V. 12. The step (B) is performed in absolute value of 3
The method of claim 9 wherein forming an erase circuit for applying a third voltage in the range of ~ 8V. 13. The method according to claim 9, wherein the step (A) forms a memory cell having symmetrical source and drain regions and defining a steep junction with the well. Method. 14. The method of claim 9, wherein the step of (A) forms a memory cell wherein the first conductivity type is P-type and the second conductivity type is N-type. . 15. The method according to claim 14, wherein said step (B) forms an erase circuit that supplies first and second positive voltages and a third negative voltage. . 16. The method of claim 9, wherein said step (B) forms a charge pump. 17. The method according to claim 17, wherein the step (B) forms an erasing circuit having an external connection receiving at least one of the first, second, and third voltages from the external voltage. Item 10. The method according to Item 9. 18. A method of manufacturing an electronic device including an electrically erasable memory, comprising: (A) forming a plurality of memory cells in a well of a first conductivity type, wherein the source region and the drain region are symmetrical. And (B) a first voltage of a first polarity is applied to the well, and the first voltage is applied to the well.
Forming an erasing circuit for applying a second voltage of a first polarity larger than the voltage by 2 V or more to the drain region and applying a third voltage of the second polarity to the control gate. Of manufacturing an electronic device including a simple memory. 19. The method according to claim 1, wherein the step (B) comprises:
19. The method of claim 18, wherein forming an erase circuit for applying a first voltage in the range of ~ 3V. 20. The step (B) comprises:
19. The method of claim 18, wherein forming an erase circuit for applying a second voltage in the range of ~ 9V. 21. The step (B) is performed with an absolute value of 3
19. The method of claim 18, wherein forming an erase circuit for applying a third voltage in the range of ~ 8V. 22. The method according to claim 18, wherein the step (A) forms a memory cell having symmetrical source and drain regions and defining a steep junction with the well. Method. 23. The method of claim 18, wherein step (A) forms a memory cell wherein the first conductivity type is P-type and the second conductivity type is N-type. . 24. The method according to claim 23, wherein the step (B) forms an erase circuit that supplies first and second positive voltages and a third negative voltage. . 25. The method of claim 18, wherein step (B) forms a charge pump. 26. The method according to claim 26, wherein the step (B) forms an erasing circuit having an external connection receiving at least one of the first, second, and third voltages from the external voltage. Item 19. The method according to Item 18.