JP2000305752A - Divider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce physical quantity, to reduce a mounting area, to reduce the number of cycles necessary for division, and to quicken division in a divider which operates the division of a binary number. SOLUTION: This divider is provided with a pre-processing part 3 which executes the normalization of a dividend RR, the normalization of a divisor DD, the multiplication of a normalized divisor D by three, and the calculation of a difference SC between normalizing shift amounts necessary for the normalization of the dividend RR and normalizing shift amounts necessary for the normalization of the divisor DD, and a dividing part 4 which calculates this following formula; a normalized dividend R ÷ the normalized divisor D by using redundant binary expression with a code with a radix as 4, and outputs a quotient Q by dividing the quotient Q into a positive number value QP and a negative number value QM, and a post-processing part 5 which inputs the positive number value QP and the negative number value QM and the normalizing shift amounts SC, and certifies a quotient QQ calculated by this following formula; the dividend RR ÷ the divisor DD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a divider for dividing a binary number using a signed redundant binary representation having a radix of 4.

[0002]

2. Description of the Related Art Conventionally, as a divider for dividing a binary number, for example, a reciprocal of a divisor is calculated by using the Newton-Raphson method, and a convergence type divider for obtaining a quotient from a product of the reciprocal of the divisor and a dividend. Also, a recovery type divider using a pull-back method is known.

[0003]

A convergence type divider using the Newton-Raphson method is a ROM for quotient prediction.
In addition, a multiplier and an adder for improving the accuracy are required, and this alone has a problem that the physical quantity is increased.In addition, a large number of cycles are required for the division, and the speed can be increased. There was a problem that it was not possible.

A recovery type divider using the pull-back method can be composed of an adder and a comparator, and requires a small amount of data. There was a problem that it could not be achieved.

[0005] In view of the above, the present invention has a small physical quantity, can reduce the mounting area, can reduce the number of cycles required for division, and can speed up the division. It is intended to provide a divider.

[0006]

SUMMARY OF THE INVENTION A divider according to the present invention includes a divider for dividing a binary dividend by a binary divisor using a signed redundant binary representation having a radix of 4. That is.

According to the divider of the present invention, the division unit for dividing the dividend of a binary number by the divisor of a binary number using a signed redundant binary representation with a radix of 4 is provided. It does not require a ROM for quotient prediction as in the case of the divider, a multiplier and an adder for increasing the accuracy, and should be connected in stages compared to a recovery type divider using the pullback method. The number of basic division circuit rows can be halved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
One embodiment of the present invention will be described with an example in which the present invention is applied to a fixed-point divider.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an 8-bit dividend register for storing a dividend RR, and reference numeral 2 denotes an 8-bit divisor register for storing a divisor DD.

[0010] Further, 3 indicates that the dividend RR is 0.5 ≦ RR <1.
A normalized dividend R is generated by normalizing so that the divisor DD is normalized so that 0.5 ≦ DD <1, and a normalized divisor D is tripled. The difference SC (= SA−S) between the normalized shift amount SA required for generating the normalized divisor triple value 3D and for normalizing the dividend RR and the normalized shift amount SB required for normalizing the divisor DD.
This is a preprocessing unit that performs calculation of B) and the like.

Reference numeral 4 denotes a division using a normalized dividend R as a dividend and a normalization divisor D as a divisor using a signed redundant binary expression with a radix of 4 and the quotient Q as a positive value QP And a division unit that separates and outputs a negative value QM.

[0012] Here, signed redundant binary representation to 4 the radix is intended to be expressed as shown in Equation 4, the coefficient x _i possible value of each digit, -3 ₁₀ -2 ₁₀ , -1 ₁₀ , 0
₁₀ , 1 ₁₀ , 2 ₁₀ , or 3 ₁₀ .

[0013]

(Equation 4)

In this specification and the drawings, a binary negative
Numbers are expressed in square brackets []. But
For example, -3_TenIs [11]_TwoOr [1] [1]_Two,
-2 _TenIs [10]_TwoOr [1] 0_Two, -1_TenIs [01]_Two
Or 0 [1]_Two, 0_TenIs 00_Two, 1_TenIs 01_Two, 2_TenIs 1
0_Two, 3_TenIs 11_TwoAnd, for example, 0.6
25_TenIs 0.101_Two , 0.11 [1]_Two , 1. [1] 01_Two
And so on.

In FIG. 1, reference numeral 5 denotes a positive value QP, a negative value QM, and a normal value output from the preprocessing unit 3, which form a quotient Q of a division using the normalized dividend R as a dividend and the normalized divisor D as a divisor. Is input to the dividend RR and the divisor DD.
A post-processing unit 6 for determining a quotient QQ obtained by dividing by is a 8-bit quotient register for storing the quotient QQ output from the post-processing unit 5.

FIG. 2 is a circuit diagram showing the configuration of the preprocessing unit 3. In FIG. 2, reference numeral 7 denotes a normalized dividend generating unit that receives the dividend RR and generates a normalized dividend R by normalizing the dividend RR, and 8 stores the normalized dividend R output from the normalized dividend generating unit 7. This is an 8-bit normalized dividend register.

Reference numeral 9 denotes a normalized divisor generating unit that receives the divisor DD and generates a normalized divisor D by normalizing the divisor DD. 10 denotes a normalized divisor D output from the normalized divisor generating unit 9. An 8-bit normalized divisor register to be stored.

Numeral 11 denotes a normalized divisor triple which receives the normalized divisor D output from the normalized divisor generator 9 and generates a normalized divisor triple value 3D obtained by multiplying the normalized divisor D by three. The value generator 12 is a 10-bit normalized divisor triple value register that stores the normalized divisor triple value 3D output from the normalized divisor triple value generator 11.

Reference numeral 13 denotes a normalized shift amount SA of the dividend RR required for normalization of the dividend RR in the normalized dividend generator 7 and a divisor DD in the normalized divisor generator 9.
A normalized shift amount difference calculator for calculating a difference SC between the divisor DD and the normalized shift amount SB required for normalization as decimal point position information when the quotient QQ is determined, and 14 is a normalized shift amount difference calculator. 13 is a normalized shift amount difference SC
Is a three-bit normalized shift amount difference register.

FIG. 3 is a circuit diagram showing a configuration of the normalized dividend generation unit 7. In FIG. 3, reference numeral 15 denotes a normalized shift amount calculating circuit that detects the position of the decimal point of the dividend RR and calculates a normalized shift amount SA required to normalize the dividend RR. The left shifter shifts the dividend RR based on the output normalized shift amount SA to generate a normalized dividend R.

FIG. 4 is a circuit diagram showing the configuration of the normalized divisor generating unit 9. In FIG. 4, reference numeral 17 denotes a normalized shift amount calculating circuit for detecting a position of a decimal point of the divisor DD and calculating a normalized shift amount SB necessary for normalizing the divisor DD. Output normalized shift amount S
This is a left shifter that generates a normalized divisor D by shifting the divisor DD based on B.

FIG. 5 is a circuit diagram showing the configuration of the normalized divisor triple value generation unit 11. In FIG. 5, 19 is a normalized divisor D (=
D7D6... D0) is shifted to the left by one bit, and “0” is inserted into the least significant bit to obtain a normalized divisor double value 2D
(= D7D6... D00) A wire / one-bit left shifter, and 20 is a normalized value obtained by adding the normalized divisor double value 2D output from the wire / one-bit left shifter 19 and the normalized divisor D. This is a 9-bit adder that generates a divisor triple value 3D.

FIG. 6 is a circuit diagram showing the configuration of the normalized shift amount difference calculating section 13. In FIG. 6, reference numeral 21 denotes a normalized shift amount SA required for normalizing the dividend RR in the normalized dividend generating unit 7 as a minuend, and a normalized shift amount required for normalizing the divisor DD in the normalized divisor generating unit 9. A subtraction is performed by subtracting the amount SB, and the normalized shift amount difference SC (= SA−
SB) for calculating SB).

FIG. 7 is a circuit diagram showing a configuration of the division unit 4. In FIG. 7, reference numeral 23 denotes a normalized divisor D (= D7D6... D
0) shifted by 1 bit to the left, 2 ⁹ digit (bit 9) and 2 ⁰ digit (bit 0) to the normalized divisor twice value 2D of the inserted formed by 10 bits constituting each "0" (= 0
D7D6... D00).

Reference numeral 24 denotes a basic division circuit column connection unit for performing division using the normalized dividend R as a dividend and a normalization divisor D as a divisor. Reference numeral 25 denotes a basic division circuit column of the basic division circuit column stage connection unit 24 which will be described later. This is a quotient calculation unit that inputs a part of the dividend (division result) output from, and calculates the fractional part of the quotient Q of the division using the normalized dividend R as the dividend and the normalized divisor D as the divisor.

26 separates the fractional part of the quotient Q output from the quotient calculator 25 into a positive value and a negative value,
A quotient separation storage unit that separates and stores a positive value QP and a negative value QM that constitute the quotient Q. Reference numeral 27 denotes a basic division circuit column connection unit 2
4 is a division / quotient separation / storage control unit that performs division control and quotient separation / storage control of the quotient separation / storage unit 26.

FIG. 8 is a circuit diagram showing the configuration of the basic division circuit column stage connection unit 24. In FIG. 8, reference numerals 28-1 to 28-5 denote basic division circuit rows, and the basic division circuit row 28-1 converts a normalized dividend R into a minuend R7R6... R0, a normalized divisor D
Are subtracted as D7D6... D0.

The basic division circuit row 28-2 is composed of dividends R'7R'6... Output from the basic division circuit row 28-1.
The dividends R'7R'6... R'000, where R'0 is the upper 8 bits and lower 2 bits are 00, are the addends and subtractions R9R8.
... R0, normalized divisor D, normalized divisor double value 2
D, a divisor selected from the normalized divisor triple value 3D or zero is added and subtracted as D9D8... D0 to perform addition and subtraction.

The basic division circuit rows 28-3 to 28-5
Is the dividend R′9 output from the preceding basic division circuit row.
R'8 ... Lower 8 bits in R'0 R'7R'6 ...
The dividends R'7R'6... R'000, where R'0 is the upper 8 bits and lower 2 bits are 00, are the addends and subtractions R9R8.
... R0, normalized divisor D, normalized divisor double value 2
D, a divisor selected from the normalized divisor triple value 3D or zero is added and subtracted as D9D8... D0 to perform addition and subtraction.

In the basic division circuit row 28-1, calculation of an intermediate difference and an intermediate carry, which are intermediate values by subtraction, and calculation of a dividend from the intermediate difference and the intermediate carry are performed. In 2 to 28-5, the calculation of the intermediate sum as the intermediate value by addition or the intermediate difference and the intermediate carry by subtraction, and the calculation of the dividend from the intermediate sum or the intermediate difference and the intermediate carry are performed.

Here, the calculation of the intermediate difference as an intermediate value by subtraction is performed based on the calculation rules shown in Table 4, and the calculation of the intermediate sum as the intermediate value by addition is performed based on the calculation rules shown in Table 5. However, since the operation rules shown in Table 4 are included in the operation rules shown in Table 4, the basic division circuit column 28-1
28 to 5-5 may be provided with an intermediate value / intermediate carry calculation circuit for calculating an intermediate sum and an intermediate carry based on the arithmetic rules shown in Table 5.

[0032]

[Table 4]

[0033]

[Table 5]

Further, the calculation of the dividend from the intermediate sum or the intermediate difference and the intermediate carry is performed based on the operation rules shown in Table 6. Here, Kn-1 is an intermediate sum or an intermediate difference, and Cn-1.
Is an intermediate carry, and R'n-1 is a dividend.

[0035]

[Table 6]

FIG. 9 is a circuit diagram showing a configuration of the basic division circuit row 28-1. In FIG. 9, 33-h (where h = 7,
6,... 0. ) Represents the dividend Rh and the divisor Dh by N
NAND circuit for performing AND processing, 34 to 37 are basic A circuits forming an intermediate value / intermediate carry circuit, Kh is an intermediate difference, C8,
C6, C4 and C2 are intermediate carry.

Reference numerals 38 to 41 denote basic B circuits constituting a dividend calculation circuit, KSh denotes a code signal of an intermediate difference Kh, and RS'h
Is a code signal of the dividend R'h output from the basic A circuits 34 to 37, and 42-h is a basic division circuit sequence by performing a NAND process on the dividend R'h and the code signal RS'h output from the basic B circuit. 28-1 is a NAND circuit that generates a code signal RS'h to be output from 28-1.

The NAND circuits 33-7, 33-6,
42-7, 42-6, basic A circuit 34, and basic B circuit 38
And a basic division circuit are configured, and the NAND circuit 33-5,
33-4, 42-5, and 42-4, the basic A circuit 35, and the basic B circuit 39 form a basic division circuit, and the NAND circuits 33-3, 33-2, 42-3, and 42-2 and the basic A circuit A basic division circuit is composed of the circuit 36 and the basic B circuit 40.
The AND circuits 33-1, 33-0, 42-1 and 42-0, the basic A circuit 37 and the basic B circuit 41 constitute a basic division circuit.

FIG. 10 is a circuit diagram showing a configuration of the basic A circuits 34 to 37. These basic A circuits 34 to 37 are represented by the following equation (5).
Are executed for the operation in the positive case among the operations shown in Table 5.

[0040]

(Equation 5)

In FIG. 10, reference numeral 43 denotes a dividend Rn-1 (however,
n = 8, 5, 3, 1. ) And the divisor Dn-1 are EO
An EOR circuit 44 for performing an R (exclusive OR) process, a NAND 44 for performing a NAND process on the dividend Rn-1 and the divisor Dn-1
A circuit, 45, an inverter for inverting the output of the NAND circuit 44, 46, an EOR circuit for EORing the dividend Rn and the divisor Dn, and 47, an EOR circuit for EORing the output of the inverter 45 and the output of the EOR circuit 46; .

The reference numeral 48 represents the dividend Rn and the divisor Dn as N.
NAND circuit for AND processing, 49 is a NOR circuit for NOR processing the dividend Rn and divisor Dn, 50 is an OR circuit for ORing the output of the NOR circuit 49 and the output of the NAND circuit 44, 51 is the NAND circuit 48 and the OR circuit This is a NAND circuit that performs a NAND process on the output of F.50.

Reference numeral 52 denotes a dividend Rn-1 and a divisor Dn-
EOR circuit for performing EOR processing on 1; 53, an EOR circuit for performing EOR processing on the dividend Rn and the divisor Dn;
This is a NAND circuit that performs NAND processing on the outputs of the circuits 52 and 53.

Reference numeral 55 denotes a selector which outputs the output of the EOR circuit 43 or "1" as the intermediate difference Kn-1. The selector 55 is controlled by the output of the NAND circuit 54, and outputs when the output of the NAND circuit 54 is "0". Selects “1” and selects NA
When the output of the ND circuit 54 is “1”, the EOR circuit 4
The third output is selected.

A selector 56 outputs the output of the EOR circuit 47 or "0" as the intermediate difference Kn.
Controlled by the output of the AND circuit 54, when the output of the NAND circuit 54 is "0", "0" is selected, and when the output of the NAND circuit 54 is "1", the output of the EOR circuit 47 is selected. Is what you do.

A selector 57 outputs the output of the NAND circuit 51 or "1" as an intermediate carry Gn + 1. The selector 57 is controlled by the output of the NAND circuit 54, and when the output of the NAND circuit 54 is "0". Select “1” and select NA
When the output of the ND circuit 54 is “1”, the output of the NAND circuit 51 is selected.

FIG. 11 is a circuit diagram showing the structure of the basic B circuits 38 to 41. These basic B circuits 38 to 41 are given by
This is a circuit necessary for performing the operations shown in Table 6.

[0048]

(Equation 6)

In FIG. 11, reference numeral 58 denotes an inverter for inverting the intermediate difference Kn-1; 59, an EOR circuit for EOR-processing the output of the inverter 58 and the intermediate carry Gn-1 to output a dividend R'n-1. is there.

Reference numeral 60 denotes an inverter for inverting the intermediate carry Gn-1. Reference numeral 61 denotes a NAND processing of the sign signal KSn-1 and the output of the inverter 60 to perform a sign signal RS'n-1.
Are output from the NAND circuit.

Further, 62 is an inverter for inverting the intermediate difference Kn, 63 is an inverter for inverting the sign signal KSn-1, and 64 is NAND processing of the intermediate carry Gn-1 and the output of the inverter 63 and the intermediate value Kn-1. NAND circuit,
Reference numeral 65 denotes an EOR circuit that performs an EOR process on an output of the inverter 62 and an output of the NAND circuit 64 and outputs a dividend R′n.

Reference numeral 66 denotes a NAND circuit for performing NAND processing on the output of the NAND circuit 64 and the sign signal KSn;
Inverts the output of the NAND circuit 66 to generate the sign signal RS'n.
Is an inverter that outputs.

FIG. 12 shows a basic division circuit row 28-2 to 28-.
5 is a circuit diagram showing a configuration of FIG. In FIG. 12, 68-u (where u is 9, 8,... 0, but u = 7, 6,.
Is omitted from the drawing. ) Is the divisor selection signal sel
The selection operation is controlled by -D1, sel-D2, and sel-D3, and the normalized divisor Du of the bit u, the normalized divisor 2 times the bit u 2Du, or the normalized divisor 3 times the bit u 3
A selector for selecting a divisor for selecting Du, and 69 is a parallel addition / subtraction basic circuit sequence.

FIG. 13 is a circuit diagram showing the structure of the divisor selection selector 68-u. In FIG. 13, 70 is a normalized divisor D
N that performs NAND processing on u and the divisor selection signal sel-D1
An AND circuit 71 for performing NAND processing on the normalized divisor double value 2Du and the divisor selection signal sel-D2;
Reference numeral 72 denotes a normalized divisor triple value 3Du and a divisor selection signal sel-.
NAND circuit for performing NAND processing with D3, 73 is NAN
NA for NANDing outputs of D circuits 70, 71, 72
This is an ND circuit. Table 7 shows the divisor selection signal sel-
D1, sel-D2, sel-D3, and NAND circuit 7
3 shows the relationship with the output.

[0055]

[Table 7]

FIG. 14 is a circuit diagram showing a configuration of the parallel addition / subtraction basic circuit sequence 69. In FIG. 14, 74-u (where u =
Illustrations of parts 6 and 2 are omitted. ) Is a NAND circuit for performing NAND processing on the dividend Ru and the divisor Du, and 75-u
(However, the portion of u = 6 to 2 is not shown.) Is controlled by the addition / subtraction signal pm_, and the NAND circuit 74-
A selector for selecting the output of u or the divisor Du.

Also, 76-t (where t = 4, 3, 2,
Although 1, 0, the portion of t = 3, 2, 1 is not shown. ) Is a basic C circuit forming an intermediate value / intermediate carry circuit, and 77-t (however, t = 3, 2, 1 is omitted from the drawing) is a basic B circuit forming a dividend calculation circuit. .

Reference numeral 78-u (where u = 6 to 2 is not shown) denotes a NAND circuit for performing NAND processing on the dividend Ru and the divisor Du output from the basic B circuit. u (where u = 6 to 2 is not shown) is controlled by the addition / subtraction signal pm_, and the basic B
This is a selector that performs a NAND process on the divisor Du output from the circuit and the output of the NAND circuit 78-u to output the divisor Du.

The NAND circuits 74-9 to 74-0,
Reference numerals 78-9 to 78-0 denote circuits necessary for performing the subtraction. As will be described later, the addition / subtraction signal p is used during the subtraction.
m _ = “0”, and the addition / subtraction signal pm_ =
It becomes “1”.

FIG. 15 is a circuit diagram showing the structure of the basic C circuits 76-4 to 76-0. In FIG. 15, 80 is a basic A circuit, 81 is a basic D circuit, 82 is a code signal RSm-1 (where m is 9, 7, 5, 3, 1), and RSm is an NA.
This is a NAND circuit that performs ND processing.

A selector 83 selects the intermediate sum or intermediate difference Km-1 output from the basic A circuit 80 or the intermediate sum or intermediate difference Km-1 output from the basic D circuit 81. Is controlled by the output of
When the output of the circuit 82 is “1”, the intermediate sum or the intermediate difference Km−1 output from the basic A circuit 80 is selected, and NA
When the output of the ND circuit 82 is “0”, the basic D circuit 8
The intermediate sum or the intermediate difference Km-1 output from 1 is selected.

A selector 84 selects "0" or a code signal KSm-1 outputted from the basic D circuit 81. The selector 84 is controlled by the output of the NAND circuit 82, and the output of the NAND circuit 82 is "1". In this case, select "0"
When the output of the ND circuit 82 is “0”, the basic D circuit 8
1 is to select the code signal KSm-1 output from 1.

A selector 85 selects the intermediate sum or intermediate difference Km output from the basic A circuit 80 or the intermediate sum or intermediate difference Km output from the basic D circuit 81.
The NAND circuit 82 is controlled by the output of the NAND circuit 82
Is "1", the intermediate sum or intermediate difference Km output from the basic A circuit 80 is selected, and the NAND circuit 82 is selected.
Is "0", the intermediate sum or the intermediate difference Km output from the basic D circuit 81 is selected.

Reference numeral 86 denotes a selector for selecting "0" or the code signal KSm-1 output from the basic D circuit 81. The selector 86 is controlled by the output of the NAND circuit 82 and outputs "1" when the output of the NAND circuit 82 is "1". In this case, select "0"
When the output of the ND circuit 82 is “0”, the basic D circuit 8
This selects the code signal KSm output from 1.

A selector 87 selects an intermediate carry Gm + 1 output from the basic A circuit 80 or an intermediate carry Gm + 1 output from the basic D circuit 81.
Controlled by the output of the ND circuit 82, when the output of the NAND circuit 82 is "1", the intermediate carry Gm + 1 output from the basic A circuit 80 is selected, and when the output of the NAND circuit 82 is "0". Selects the intermediate carry Gm + 1 output from the basic D circuit 81.

FIG. 16 is a circuit diagram showing the configuration of the basic D circuit 81. The basic D circuit 81 performs the operation shown in Expression 7, and performs the operation shown in Table 5 when the operation is negative. It is necessary.

[0067]

(Equation 7)

In FIG. 16, reference numeral 88 denotes a dividend Rm-1 and a divisor D
An EOR circuit that outputs an intermediate sum or an intermediate difference Km-1 by performing EOR processing on m-1 and an inverter 89 that inverts the output of the EOR circuit 88, an inverter 90 that inverts the sign signal RSm-1, and an inverter 91 The output of 89 and 90 is N
NAND for performing AND processing and outputting code signal KSm-1
Circuit.

Reference numeral 92 denotes a dividend Rm-1 and a divisor Dm-
1 for performing NAND processing on 1 and the sign signal RSm-1
A circuit 93 is an EOR circuit that performs EOR processing on the dividend Rm and the divisor Dm.

A selector 94 selects the output of the EOR circuit 93 or the divisor Dm and outputs an intermediate sum or an intermediate difference Km. The selector 94 is controlled by the output of the NAND circuit 92.
When the output of the NAND circuit 92 is "0", the output of the EOR circuit 93 is selected, and the output of the NAND circuit 92 is "1".
In this case, the divisor Dm is selected.

Reference numeral 95 denotes a NAND circuit for performing NAND processing on the output of the NAND circuit 92 and the sign signal RSm to output a sign signal KSm, reference numeral 96 denotes a NAND circuit for performing NAND processing on the dividend Rm and the divisor Dm, and reference numeral 97 denotes a NAND circuit. 9
6 is an inverter that inverts the output of No. 6 and outputs an intermediate carry Gm + 1.

FIG. 17 is a circuit diagram showing the configuration of the quotient calculation unit 25 and the division / quotient separation / storage control unit 27. In FIG. 17, in the quotient calculation unit 25, reference numeral 98 denotes R'7 to R'5 among the dividends R'7 to R'0 output from the basic division circuit row 28-1.
And the quotient Q to be output from the division unit 4 is 2 ⁻¹
Digit values q9 and 2 ^-2 digit value q8 is a partial quotient calculation circuit for calculating a.

Reference numeral 99 denotes a quotient Q to be output from the division unit 4 by inputting R'7 to R'5 among the dividends R'9 to R'0 output from the basic division circuit row 28-2. of a partial quotient calculation circuit for calculating a ^2-3 digit value q7 and ^2-4 digit value q6.

Further, reference numeral 100 designates R'7 to R'5 among the dividends R'9 to R'0 output from the basic division circuit 28-3 and inputs the quotient Q to be output from the division unit 4. among a partial quotient calculation circuit for calculating the 2 ^-5 digit values q5 and ^2-6 digit values q4.

Reference numeral 101 denotes R'7 to R'5 among the dividends R'9 to R'0 output from the basic division circuit row 28-4.
Of the quotient Q to be output from the division unit 4, 2 ⁻⁷
Is a partial quotient calculation circuit for calculating the value q3 of the digit of and the value q2 of the digit of 2 ^-8 .

Reference numeral 102 denotes R'7 to R'5 of the dividends R'9 to R'0 output from the basic division circuit row 28-5.
Of the quotient Q to be output from the division unit 4, 2 ⁻⁹
Is a partial quotient calculation circuit that calculates the value q1 of the digit of and the value q0 of the digit of 2 ^-10 .

Reference numeral 103 denotes R'7 to R'5 among the dividends R'7 to R'0 output from the basic division circuit row 28-1.
And a divisor selection signal generation circuit that generates divisor selection signals sel-D1, sel-D2, and sel-D3 to be supplied to the basic division circuit row 28-2.

Reference numeral 104 denotes R'7 to R'5 among the dividends R'9 to R'0 output from the basic division circuit row 28-2.
And a divisor selection signal generation circuit that generates divisor selection signals sel-D1, sel-D2, and sel-D3 to be supplied to the basic division circuit row 28-3.

The reference numeral 105 designates R'7 to R'5 among the dividends R'9 to R'0 output from the basic division circuit row 28-3.
Is a divisor selection signal generation circuit that generates divisor selection signals sel-D1, sel-D2, and sel-D3 to be supplied to the basic division circuit row 28-4.

Reference numeral 106 denotes R'7 to R'5 among the dividends R'9 to R'0 output from the basic division circuit row 28-4.
Is a division selection signal generation circuit that generates divisor selection signals sel-D1, sel-D2, and sel-D3 to be supplied to the basic division circuit row 28-5.

Reference numeral 107 denotes RS'7 of the code signals RS'9 to RS'0 output from the basic division circuit row 28-1.
To RS'5 to generate addition / subtraction signals pm and pm_, and to add the addition / subtraction signal pm_ to the basic division circuit row 28-2.
, And supplies the addition / subtraction signal pm to the quotient separation storage unit 26. In addition,
The addition / subtraction signal pm supplied from the addition / subtraction signal generation circuit 107 to the quotient separation storage unit 26 is referred to as pm98.

Reference numeral 108 denotes RS'7 of the code signals RS'9 to RS'0 output from the basic division circuit row 28-2.
To RS'5 to generate addition / subtraction signals pm, pm_, and to add / subtract the addition / subtraction signal pm_ to the basic division circuit row 28-3.
, And supplies the addition / subtraction signal pm to the quotient separation storage unit 26. In addition,
The addition / subtraction signal pm supplied from the addition / subtraction signal generation circuit 108 to the quotient separation storage unit 26 is referred to as pm76.

Reference numeral 109 denotes RS'7 of the code signals RS'9 to RS'0 output from the basic division circuit row 28-3.
To RS'5 to generate addition / subtraction signals pm and pm_, and to add the addition / subtraction signal pm_ to the basic division circuit row 28-4.
, And supplies the addition / subtraction signal pm to the quotient separation storage unit 26. In addition,
The addition / subtraction signal pm supplied from the addition / subtraction signal generation circuit 109 to the quotient separation storage unit 26 is referred to as pm54.

Reference numeral 110 denotes RS'7 of the code signals RS'9 to RS'0 output from the basic division circuit row 28-4.
~ RS'5 to generate addition / subtraction signals pm, pm_, and to add / subtract the addition / subtraction signal pm_ to the basic division circuit row 28-5.
, And supplies the addition / subtraction signal pm to the quotient separation storage unit 26. In addition,
The addition / subtraction signal pm supplied from the addition / subtraction signal generation circuit 110 to the quotient separation storage unit 26 is referred to as pm32.

Reference numeral 111 denotes RS'7 of the code signals RS'9 to RS'0 output from the basic division circuit row 28-5.
~ RS'5 to generate an addition / subtraction signal pm, and supply the addition / subtraction signal pm to the quotient separation storage unit 26.
This is a subtraction signal generation circuit. Note that the addition / subtraction signal pm supplied from the addition / subtraction signal generation circuit 111 to the quotient separation storage unit 26 is referred to as pm10.

FIG. 18 is a circuit diagram showing a configuration of the partial quotient calculation circuits 98 to 102. In FIG. 18, 112 is the dividend R ′
7, a NAND circuit for performing NAND processing on R'6, and an inverter 113 for inverting the output of the NAND circuit 112 and outputting a partial quotient qm.

An inverter 114 inverts the dividend R′6, an AND circuit 115 performs an AND operation on the output of the inverter 114 and the dividend R′5, and 116 denotes an AND circuit.
N for NOR-processing the output of circuit 115 and dividend R'7
The OR circuit 117 is an inverter that inverts the output of the NOR circuit 116 and outputs a partial quotient qm-1.

Table 8 shows the dividends R'7, R'6, R '
5 and the partial quotients qm and qm-1.
= R'7 + R'6 and qm-1 = R'7 + / R'6 * R'5.

[0089]

[Table 8]

FIG. 19 shows the divisor selection signal generation circuits 103-1.
It is a circuit diagram which shows the structure of 06. In FIG. 19, reference numeral 118 denotes an inverter for inverting the dividend R′6, and 119 denotes a dividend R′7.
Is an NAN that NANDs the dividend R′5 and the outputs of the inverters 118 and 119.
The D circuit 121 is a NAND circuit that performs NAND processing on the dividend R′6 and the output of the inverter 119.

Reference numeral 122 denotes an inverter that inverts the output of the NAND circuit 120 and outputs a divisor selection signal sel-D1, 123 denotes an inverter that inverts the output of the NAND circuit 121 and outputs a divisor selection signal sel-D2, and 124
Inverts the output of the inverter 119 and outputs the divisor selection signal se
This is an inverter that outputs 1-D3. Table 9 shows the dividends R'7, R'6, R'5 and the divisor selection signal sel-D.
1, sel-D2 and sel-D3 are shown.

[0092]

[Table 9]

FIG. 20 shows the addition / subtraction signal generation circuits 107 to
FIG. 3 is a circuit diagram illustrating a configuration of a second embodiment. 20, reference numeral 125 denotes a NOR circuit that performs NOR processing on the code signals RS'7, RS'6, and RS'5 and outputs an addition / subtraction signal pm_. Reference numeral 126 denotes an addition / subtraction signal obtained by inverting the addition / subtraction signal pm_. It is an inverter that outputs pm.

Table 10 shows that the code signals RS'7, RS '
6, RS'5 and addition / subtraction signals pm, pm_,
This shows the relationship with the state of subtraction. However, the addition / subtraction signal generation circuit 111 does not output the addition / subtraction signal pm_.

[0095]

[Table 10]

FIG. 21 is a circuit diagram showing the configuration of the quotient separation storage unit 26. In Figure 21, 127 is bit 0 (2 ⁰ digit)
This is an 11-bit positive value register for storing a positive value QP constituting a quotient Q consisting of ^.about.bit -10 (2-10 digits). The bit 0 of the positive value register 127 is a basic division circuit 28. -1, the normalized dividend R-
Since the operation of the normalized divisor D is performed, it is fixed to "1", and positive bits q9 to q0 smaller than the decimal value of the positive value QP of the quotient Q are stored in bits -1 to -10. Is done.

Further, 128 is a negative value QM constituting the quotient Q.
Is stored in the bit 0 of the negative value register 128. In the basic division circuit 28-1, the operation of the normalized dividend R-normalized divisor D is always performed. The fixed value is fixed to 0 ", and negative values q9 to q0 smaller than a decimal value among the negative values QM of the quotient Q are stored in bits -1 to -10.

Further, 129-9 stores the partial quotient q9 or “0” output from the partial quotient calculation section 98 in the positive value register 12
7 is a selector that outputs to bit −1 of 7 and is controlled by an addition / subtraction signal pm98.
When "0", the partial quotient q9 is selected, and when the addition / subtraction signal pm98 = "1", "0" is selected.

129-8 stores the partial quotient q8 or "0" output from the partial quotient calculation section 98 in the positive value register 12
7 is a selector for outputting to bit-2 of the control signal 7 and controlled by an addition / subtraction signal pm98.
When "0", the partial quotient q8 is selected, and when the addition / subtraction signal pm98 = "1", "0" is selected.

Reference numeral 129-1 denotes the partial quotient q1 or "0" output from the partial quotient calculation unit 102 in the positive value register 1
This is a selector for outputting to bit -9 of 27, controlled by the addition / subtraction signal pm10, and the addition / subtraction signal pm10 =
When "0", the partial quotient q1 is selected, and when the addition / subtraction signal pm10 = "1", "0" is selected.

Further, 129-0 stores the partial quotient q0 or “0” output from the partial quotient calculation unit 102 in the positive value register 1
27 is a selector that outputs 27 bits-10.
Controlled by the subtraction signal pm10, the addition / subtraction signal pm10
When == "0", the partial quotient q0 is selected, and when the addition / subtraction signal pm10 = "1", "0" is selected.

The selector 129-7, which is controlled by the addition / subtraction signal pm76 and outputs the partial quotient q7 or "0" output from the partial quotient calculator 99 to bit-3 of the positive value register 127, and / Partial quotient q6 controlled by the subtraction signal pm76 and output from the partial quotient calculation unit 99
Alternatively, the selector 129-6 that outputs “0” to the bit -4 of the positive value register 127 is not shown.

Further, the selector 129-5 which is controlled by the addition / subtraction signal pm54 and outputs the partial quotient q5 or "0" output from the partial quotient calculation unit 100 to the bit -5 of the positive value register 127, and / Partial quotient q controlled by the subtraction signal pm54 and output from the partial quotient calculation unit 100
The selector 129-4 for outputting 4 or "0" to the bit -6 of the positive value register 127 is also not shown.

The selector 129-3, which is controlled by the addition / subtraction signal pm32 and outputs the partial quotient q3 or "0" output from the partial quotient calculation unit 101 to bit-7 of the positive value register 127, and / Partial quotient q controlled by subtraction signal pm32 and output from partial quotient calculation section 101
The selector 129-2 for outputting 2 or “0” to the bit -8 of the positive value register 127 is also not shown.

130-4 is an addition / subtraction signal pm9
Inverter 130-0 inverts addition / subtraction signal pm10, and inverter 1 inverts addition / subtraction signal pm76, pm54, pm32.
Illustrations of 30-3, 130-2, and 130-1 are omitted.

131-9 stores the partial quotient q9 or "0" output from the partial quotient calculating section 98 in the negative value register 12
8 is a selector for outputting to bit −1 of 8 and controlled by the output of the inverter 130-4. When the output of the inverter 130-4 is “1”, the partial quotient q9 is selected, and In the case of "0", "0" is selected.

The reference numeral 131-8 designates the partial quotient q8 or "0" output from the partial quotient calculation section 98 as the negative value register 12
8, which is controlled by the output of the inverter 130-4. When the output of the inverter 130-4 is "1", the partial quotient q8 is selected, and the output of the inverter 130-4 = In the case of "0", "0" is selected.

The reference numeral 131-1 denotes the partial quotient q1 or "0" output from the partial quotient calculation unit 102,
This is a selector that outputs to bit-9 of 28, controlled by the output of inverter 130-0,
When the output of the inverter 130-0 is "1", the partial quotient q1 is selected, and when the output of the inverter 130-0 is "0", "0" is selected.

Also, 131-0 stores the partial quotient q0 or “0” output from the partial quotient calculation unit 102 in the negative value register 1
This is a selector for outputting to bit-10 of 28, controlled by the output of inverter 130-0, and
When the output of 0 is "1", the partial quotient q0 is selected, and when the output of the inverter 130-0 is "0", "0" is selected.

The selector 131-7, which is controlled by the output of the inverter 130-3, outputs the partial quotient q7 or "0" output from the partial quotient calculation unit 99 to bit-3 of the negative value register 128, and The selector 131-6, which is controlled by the output of the inverter 130-3 and outputs the partial quotient q6 or "0" output from the partial quotient calculation unit 99 to bit-4 of the negative value register 128, is not shown. .

The selector 131-5, which is controlled by the output of the inverter 130-2 and outputs the partial quotient q5 or "0" output from the partial quotient calculation unit 100 to bit-5 of the negative value register 128, and The partial quotient q4 or “0” output from the partial quotient calculation unit 100 is controlled by the output of the inverter 130-2,
6 is also omitted from the figure.

A selector 131-3 controlled by the output of the inverter 130-1 to output the partial quotient q3 or "0" output from the partial quotient calculation unit 101 to bit-7 of the negative value register 128, and The partial quotient q2 or “0” output from the partial quotient calculation unit 101 is controlled by the output of the inverter
8 is also omitted from the illustration.

FIG. 22 is a circuit diagram showing a configuration of post-processing section 5. In FIG. 22, reference numeral 132 denotes a 3-bit normalized shift amount difference register for storing the normalized shift amount difference SC output from the normalized shift amount difference register 14 of the preprocessing unit 3.

Further, 133 is obtained by subtracting the negative value QM from the positive value QP constituting the quotient Q output from the division unit 4 to obtain a quotient Q.
The 134 shifts the output QP-QM of the subtractor 133 to the right by the amount indicated by the normalized shift amount difference SC output from the normalized shift amount difference register 132, and the dividend RR ÷ divisor It is a right shifter for calculating a quotient QQ of DD.

In one embodiment of the present invention configured as described above, the dividend RR is stored in the dividend register 1, normalized in the normalized dividend generation unit 7, and output from the normalized dividend generation unit 7. The normalized dividend R is stored in the normalized dividend register 8, and the divisor DD is
The normalized divisor D stored in the divisor register 2 and normalized by the normalized divisor generator 9 and output from the normalized divisor generator 9 is stored in the normalized divisor register 10.

The normalized divisor D output from the normalized divisor generating unit 9 is tripled in the normalized divisor triple value generating unit 11, and the normalized divisor D output from the normalized divisor triple value generating unit 11 is output. The normalized divisor triple value 3D is stored in the normalized divisor triple value register 12.

In the normalized shift amount difference calculator 13, the dividend RR output from the normalized dividend generator 7 is output.
Is subtracted from the normalized shift amount SA required for normalization of the divisor DD and the normalized shift amount SB required for normalization of the divisor DD output from the normalized divisor generating unit 9. SC (= SA−SB) is stored in the normalized shift amount difference register 14.

Here, the normalized dividend R, the normalized divisor D and the normalized divisor triple value 3D are supplied to the divider 4, where the wire / 1-bit left shifter 23 processes the normalized divisor D. A normalized divisor double value 2D is generated, and
The normalized shift amount difference SC is stored in the normalized shift amount difference register 132 of the post-processing unit 5.

Then, in the basic division circuit columns 28-1 to 28-5 of the basic division circuit column connection section 24, the normalized dividend R, the normalized divisor D, the normalized divisor double value 2D, the normalized divisor 3 Using the multiplication value 3D or zero, the division R ^{j + 1} = 4R ^j −q _j · D (where R ^j is the input dividend, q _j is the partial quotient, and R ^{j + 1} is the output dividend) Is performed).

In the quotient calculation section 25, the dividend R 'output from the basic division circuit rows 28-1 to 28-5 is output.
The fractions q9 to q0 of the quotient Q after the decimal point are calculated from 7 to R'5, and the quotient separation storage unit 26 separates the positive and negative values constituting the fractions q9 to q0 of the quotient Q below the decimal point. The positive value register 127 and the negative value register 128
And are stored respectively.

In the post-processing unit 5, the 11-bit subtractor 133 subtracts the positive value QP and the negative value QM constituting the quotient Q.
After being converted to a base number, the normalized shift amount difference register 132
Is shifted to the right by the right shifter 134 based on the normalized shift amount difference SC stored in, the quotient QQ of the dividend RR ÷ the divisor DD is calculated, the quotient QQ is stored in the quotient register 6, and the division ends. Will be.

FIGS. 23, 24 and 25 are diagrams for specifically explaining the operation of one embodiment of the present invention, where the normalized dividend R = 0.10011101 The normalized divisor D = 0.11100101 The case is taken as an example.

In FIG. 23, reference numeral 135-1 denotes dividends R'7 to R 'output from the basic division circuit row 28-1.
0 and 135-2 are dividends R'9 to R'0 output from the basic division circuit row 28-2, and 135-3 are basic division circuit rows 2
Dividends R'9 to R'0 output from 8-3, 135-4
Is the dividend R'9 output from the basic division circuit row 28-4.
R'0 and 135-5 indicate dividends R'9 to R'0 output from the basic division circuit row 28-5.

First, in the basic division circuit row 28-1, 0.101101101 (.R7 to R0) -0.1110
0101 (0D7 to D0) = 0.0 [1] [1] 1100
0 (0.R'7 to R'0) is subtracted.

Here, R'7 = 0, R'6 = [1], R'5
= [1], q9 = R'7 + R'6 = 0 + 1 = 1 q8 = R'7 + / R'6 * R'5 = 0 + 0 * 1 = 0.

In this case, the code signal RS'7 = 0,
Since RS'6 = 1 and RS'5 = 1, pm = RS'7 + RS'6 + RS'5 = 0 + 1 + 1 = 1 pm.sub .-- // pm = 0.

As described above, since q9q8 = 10 and pm = 1, in the quotient separation storage unit 26, 00 is stored in the bit-1 and bit-2 portions of the positive value register 127.
Is stored, and 10 is stored in the bit-1 and bit-2 portions of the negative value register 128.

Next, in the basic division circuit column 28-2, since pm_ = 0, the basic division circuit column 28-2
The dividend 0.0 [1] [1] 11000 (0.
R'7 to R'0) are shifted left by 2 bits and 00 is inserted in the lower 2 bits. [1]. [1] 11000000
(R9 to R0) will be added,
The dividend R6 ′ output from the basic division circuit row 28-1 =
Since [1], the normalized double value 2D is selected as the divisor.

Therefore, in the basic division circuit row 28-2, 0 [1]. [1] 1100000 (R9 to R0) +01.11
001010 (D9 to D0) = 0.1010101010
(00.R'7 to R'0) are added.

Here, R'7 = 1, R'6 = 0, R'5 =
Since it is 1, q7 = R'7 + R'6 = 1 + 0 = 1 q6 = R'7 + / R'6 * R'5 = 1 + 1 * 1 = 1.

In this case, the code signal RS'7 = 0,
Since RS'6 = 0 and RS'5 = 0, pm = RS'7 + RS'6 + RS'5 = 0 + 0 + 0 = 0 pm _ = / pm = 1.

As described above, since q7q6 = 11 and pm = 0, in the quotient separation storage unit 26, 11 is stored in the bit-3 and bit-4 portions of the positive value register 127.
Is stored, and 00 is stored in the bits -3 and -4 of the negative value register 128.

Next, in the basic division circuit column 28-3, since pm_ = 1, the basic division circuit column 28-3
The dividend output from 2 is 0.0010101010 (00.
R'7 to R'0) are shifted to the left by 2 bits, and 00 is inserted in the lower 2 bits.
(R9 to R0) will be subtracted,
The dividend R′7 output from the basic division circuit column 28-2 =
Since it is 1, the normalized triple value 3D is selected as the divisor.

Therefore, in basic division circuit row 28-3, 10.10101000 (R9 to R0) -10.1010
1111 (D9 to D0) = 0.0000000 [1] [1]
[1] A subtraction of (00.R′7 to R′0) is performed.

Here, R'7 = 0, R'6 = 0, R'5 =
Since it is 0, q5 = R'7 + R'6 = 0 + 0 = 0 q4 = R'7 + / R'6 * R'5 = 0 + 1 * 0 = 0.

In this case, the code signal RS'7 = 0,
Since RS'6 = 0 and RS'5 = 0, pm = RS'7 + RS'6 + RS'5 = 0 + 0 + 0 = 0 pm _ = / pm = 1.

As described above, since q5q4 = 00 and pm = 0, in the quotient separation storage unit 26, the bits -5 and -6 of the positive value register 127 are set to 00.
Is stored, and 00 is stored in the bits -5 and -6 of the negative value register 128.

Next, since pm_ = 1 in the basic division circuit row 28-4, the basic division circuit row 28-
The dividend output from 3 is 0.0000000 [1] [1] [1]
The subtraction is performed on the dividend 0.000 [1] [1] [1] 00 (R9-R0) obtained by shifting (00.R'7-R'0) two bits to the left. Circuit row 2
The dividend R′7 = 0, R′6 = 0 output from 8-3,
Since R′5 = 0, the divisor is 0.0000000
00 is selected.

Therefore, in the basic division circuit row 28-4, 0.000 [1] [1] [1] 00 (R9 to R0) −00.
00000000 (D9-D0) = 0.000 [1]
[1] [1] A subtraction of 00 (00.R'7 to R'0) is performed.

Here, R'7 = 0, R'6 = 0, R'5 =
Since it is 0, q3 = R'7 + R'6 = 0 + 0 = 0 q2 = R'7 + / R'6 * R'5 = 0 + 1 + 1 * = 0.

In this case, the code signal RS'7 = 0,
Since RS'6 = 0 and RS'5 = 0, pm = RS'7 + RS'6 + RS'5 = 0 + 0 + 0 = 0 pm _ = / pm = 1.

As described above, since q3q2 = 00 and pm = 0, in the quotient separation storage unit 26, 00 is stored in the bit-7 and bit-8 portions of the positive value register 127.
Is stored, and 00 is stored in the bits -7 and -8 of the negative value register 128.

In the basic division circuit row 28-5, since pm_ = 1, the basic division circuit row 28-5
Dividend output from 4 0.000 [1] [1] [1] 00
Dividend 0 obtained by shifting (R9 to R0) two bits to the left
0.0 [1] [1] [1] Subtraction is performed for 0000 (R9 to R0), but the dividends R′7 = 0 and R′6 = output from the basic division circuit row 28-4. 0, R'5 = 0
Therefore, 0.0000000000 is selected as the divisor.

Therefore, in the basic division circuit row 28-5, 0 [1] [1] [1] 0000 (R9 to R0) -00.
00000000 (D9 to D0) = 0.0 [1] [1]
[1] A subtraction of 0000 (00.R'7 to R'0) is performed.

Here, R'7 = 0, R'6 = [1], R'5
= [1], q1 = R'7 + R'6 = 0 + 1 = 1 q0 = R'7 + / R'6 * R'5 = 0 + 0 * 1 = 0.

In this case, the code signal RS'7 = 0,
Since RS'6 = 1 and RS'5 = 1, pm = RS'7 + RS'6 + RS'5 = 0 + 1 + 1 = 1 = 1

As described above, since q1q0 = 00 and pm = 0, in the quotient separating section 26, 00 is stored in the bits -9 and -10 of the positive value register 127, and the negative value register 10 is stored in 128 bits-9 and -10.

Therefore, the positive value register 127 contains
As a positive value QP constituting the quotient Q, it is 1.00011000
000 is stored in the negative value register 128, and 0.1000000010 is stored as a negative value constituting the quotient Q. Therefore, in the 11-bit subtractor 133 of the post-processing unit 5, Q = QP− QM = 1.10010
00000-0.10000000000 = 0.10101
11110 is calculated, the quotient Q is shifted according to the normalized shift amount difference SC, and the quotient QQ is calculated.

As described above, according to one embodiment of the present invention, the division in which the normalized dividend R is the dividend and the normalized divisor D is the divisor is performed using the signed redundant binary representation in which the radix is 4. Since a division unit 4 is provided, a ROM for quotient prediction, a multiplier and an adder for improving accuracy are not required unlike a convergence type divider, and a pull-back method is used. Compared with a recovery type divider, the number of division circuits to be connected in stages can be halved. Therefore, since the division can be performed with a small amount of material and with a small number of cycles, the mounting area can be reduced and the division can be speeded up.

In the embodiment of the present invention, the case where the basic division circuit row 28-1 is configured to perform only the subtraction has been described. In the case of being expressed in base numbers, it is possible to cope with this by configuring the basic division circuit row 28-1 so that addition and subtraction can be performed in the same manner as the basic division circuit rows 28-2 to 28-5. it can.

In the embodiment of the present invention, the case where the present invention is applied to a fixed-point divider has been described. In addition, the present invention can be applied to a floating-point divider.

[0152]

As described above, according to the divider of the present invention, the division unit for dividing a binary number by using a signed redundant binary expression having a radix of 4 is provided.
Unlike a convergence type divider, it does not require a ROM for quotient prediction, a multiplier and an adder for improving accuracy, and is compared with a recovery type divider using a pullback method.
Since the number of division circuits to be connected in stages can be halved, a small quantity is sufficient and the division can be performed with a small number of cycles. As a result, the mounting area is reduced and the division speed is increased. be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a pre-processing unit included in an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a normalized dividend generation unit included in an embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a configuration of a normalized divisor generation unit included in an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a normalized divisor triple value generation unit included in an embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a configuration of a normalized shift amount calculation unit included in an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a configuration of a division unit included in an embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a basic division circuit column stage connection portion provided in one embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a basic division circuit column included in an embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a basic A circuit included in an embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating a configuration of a basic B circuit included in an embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a basic division circuit column included in an embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of a divisor selection selector provided in an embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a parallel addition / subtraction basic circuit sequence included in an embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a basic C circuit included in an embodiment of the present invention.

FIG. 16 is a circuit diagram illustrating a configuration of a basic D circuit included in an embodiment of the present invention.

FIG. 17 is a circuit diagram illustrating a configuration of a quotient calculation unit and a division / quotient separation / storage control unit included in an embodiment of the present invention.

FIG. 18 is a circuit diagram illustrating a configuration of a partial quotient calculation circuit included in an embodiment of the present invention.

FIG. 19 is a circuit diagram illustrating a configuration of a divisor selection signal generation circuit included in an embodiment of the present invention.

FIG. 20 is a circuit diagram illustrating a configuration of an addition / subtraction signal generation circuit included in an embodiment of the present invention.

FIG. 21 is a circuit diagram illustrating a configuration of a quotient separation storage unit included in an embodiment of the present invention.

FIG. 22 is a circuit diagram illustrating a configuration of a post-processing unit included in an embodiment of the present invention.

FIG. 23 is a diagram for specifically explaining the operation of the embodiment of the present invention.

FIG. 24 is a diagram for specifically explaining the operation of the embodiment of the present invention.

FIG. 25 is a diagram for specifically explaining the operation of the embodiment of the present invention.

[Explanation of symbols]

 (Fig. 1) 1 dividend register 2 divisor register 3 preprocessor 4 divider 5 postprocessor 6 quotient register

Claims (10)

[Claims] 1. A divider comprising a division unit for dividing a binary dividend by a binary divisor using a signed redundant binary representation having a radix of 4. 2. The divider according to claim 1, wherein the dividend and the divisor are a normalized normalized dividend and a normalized divisor. 3. The method according to claim 1, wherein the division unit includes first to k-th stages connected.
(Where k is an integer of 2 or more), and j-th one of the first to k-th basic division circuit rows is provided.
j is an integer of 1 to k. ) Is divided by R ^{j + 1} = 4 × R ^j −q _j × D (where R ^j is the dividend input to the j-th basic division circuit row, and q _j is the j-th basic division) 3. The partial quotient output by the circuit sequence, D is a normalized divisor, and R ^{j + 1} is the dividend output by the j-th basic division circuit sequence.) The divider as described. Wherein said first basic division circuit column calculation rule shown in Table 1 (provided that a representation of the [1] -1 _2, is the same in Tables 2 and 3.) To An intermediate value / intermediate carry calculation circuit that calculates an intermediate difference and an intermediate carry based on the intermediate value, or an intermediate value that calculates an intermediate difference and an intermediate carry based on the calculation rules shown in Table 1. An intermediate carry calculating circuit for calculating an intermediate sum and an intermediate carry, which are intermediate values, based on an arithmetic rule shown in Table 2 and an arithmetic rule shown in Table 3. (Where Kn-1 is an intermediate value, Cn-1 is an intermediate carry, and R'n-1 is a dividend to be output), a dividend for calculating a dividend to be output from the intermediate value and the intermediate carry. And a calculation circuit, wherein the second to k-th basic division circuit rows are arranged in the manner shown in Table 1. An intermediate value / intermediate carry calculation circuit for calculating an intermediate difference and an intermediate carry based on arithmetic rules, and an intermediate sum and an intermediate carry as intermediate values based on the arithmetic rules shown in Table 2. An intermediate value / intermediate carry calculation circuit, and a dividend calculation circuit for calculating a dividend to be output from the intermediate value and the intermediate carry based on the calculation rule shown in Table 3. 4. The divider according to claim 3, wherein: [Table 1] [Table 2] [Table 3] 5. The intermediate value / intermediate carry calculation circuit sequence of the first basic division circuit sequence is a first basic operation circuit for performing the operation shown in Expression 1, or the first basic operation circuit and the number 2. A second basic operation circuit for performing the operation shown in FIG. 2 is provided.
5. The divider according to claim 4, further comprising a third basic operation circuit that performs the operation described in (3). (Equation 1) (Equation 2) (Equation 3) Here, Rn and Rn-1 are the bit n and the dividend of the bit (n-1), RSn and RSn-1 are the code signals of the dividend Rn and Rn-1, Dn and Dn-1 are the bit n and the bit (n-1) ), Kn, Kn-1 are bits n, intermediate values of bits (n-1), KSn, KSn-1 are code signals of intermediate values Kn, Kn-1, and n is a bit width of 4 or more. 6. The intermediate value / intermediate carry calculation circuit sequence of the second to k-th basic division circuit sequences includes the first basic operation circuit and the second basic operation circuit. The dividend calculation circuit of the k-th basic division circuit row is
6. The divider according to claim 5, further comprising the third basic operation circuit. 7. The normalized dividend and the normalized divisor are:
If the decimal point is i bits (where i is an integer of 4 or more), and if the least significant bit of the dividend output from the j-th basic division circuit row is bit 0, the j-th And the bit (i-1), bit (i-2), and bit (i-3) of the dividend output from the basic division circuit sequence of (i) are used to calculate the partial quotient of the j-th basic division circuit sequence. 7. The divider according to claim 6, further comprising a partial quotient calculation circuit. 8. A normalized divisor double value generating unit for generating a normalized divisor double value obtained by doubling the normalized divisor, and a normalized divisor 3 obtained by doubling the normalized divisor. A divisor triple generation unit for generating a double value, wherein the first basic division circuit sequence performs subtraction with the normalized dividend as a minuend and the normalization divisor as a divisor, or The normalized dividend is the addend and subtraction, and the normalization divisor is configured to perform addition and subtraction.The second to k-th basic division circuit trains the dividend output from the preceding basic division circuit train. 8. The method according to claim 7, wherein the addition and subtraction are performed by using zero, the normalized divisor, the normalized divisor double value, or the normalized divisor triple value as the augend. Divider. 9. The adder / subtractor of the (j + 1) -th basic division circuit row among the dividends output from the j-th basic division circuit row, bit (i-1) and bit (i-
2), characterized in that it is configured to select zero, the normalized divisor, the normalized divisor double value or the normalized divisor triple value based on the dividend of bit (i-3). The divider according to claim 8, wherein 10. The bit (i−1) and the bit (i−1) among the dividends output from the j-th basic division circuit row.
2) A control circuit for setting the (j + 1) -th basic division circuit row to an addition circuit row or a subtraction circuit row based on a code signal of a dividend of bit (i-3). The divider according to claim 9.