JP2000305517A - Drive method for plasma display pannel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive method capable of driving a plasma display pannel(PDP) without decreasing the display quality even if an erroneous discharge cell by which an excessive wall charge is formed after the selective elimination discharge exists in the PDL by shortening the width of maintenance pulse applied at first in a luminance maintaining step than another pulse applied thereafter. SOLUTION: A second satin driver applies positive polartity maintenance pulses IPY1-IPYj to a line electrode X1-n of PDP in order at a luminance maintenance step 1c. Further, a first satin driver applies positive polarity maintenance pulses IPX1-IPXj to the line electrode X in order during each non-application period of the maintenance pulses IPX1-IPXj. In this case, the maintenance pulse IPY1 applied at first to a line electrode pair X, Y is of a relatively short pulse width which is shorter than the pulse width W2 of maintenance pulse IPX1 applied thereafter and each of the pulse widths of IPY2-IPYj, IPX2-IPXj.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a matrix display type plasma display panel.

[0002]

2. Description of the Related Art In recent years, as display devices have become larger, thinner display devices have been required, and various thin display devices have been put into practical use. An AC (AC discharge) type plasma display panel (hereinafter, referred to as a PDP) has attracted attention as one of such thin display devices. FIG. 1 is a diagram showing a schematic configuration of a plasma display device that performs image display using such a PDP.

[0003] PD as a plasma display panel
P10 is, m-number of column electrodes D ₁ to D _m as address electrodes
And n each of which is arranged to cross each of these column electrodes.
And a number of row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n.
At this time, the row electrode X and the row electrode Y
One line at P10 is formed. The column electrodes D and the row electrodes X and Y are covered with a dielectric layer with respect to the discharge space, and have a structure in which a discharge cell corresponding to one pixel is formed at an intersection between each row electrode pair and a column electrode. ing.

[0004] At this time, each discharge cell has only two states of "light emission" and "non-light emission" depending on whether or not a discharge is generated in the discharge cell. That is, the lowest brightness
(Non-light emitting state) and luminance of two gradations of maximum luminance (light emitting state) can be expressed. Therefore, in order to obtain a halftone luminance corresponding to the input video signal, the driving device 100 is required for the PDP 10 having such a light emitting element.
Implements gradation driving using a subfield method.

In the subfield method, an input video signal is converted into N-bit pixel data corresponding to each pixel, and a display period of one field is set to N number of bits corresponding to each of the N bits. Divide into subfields.
Each subfield is assigned a discharge execution number corresponding to the weight of the subfield, and the discharge is selectively generated only in the subfield corresponding to the video signal. At this time, the halftone luminance corresponding to the video signal is obtained by the total number of discharges generated in each subfield (within one field display period).

A selective erase address method is known as a method of actually driving a PDP in gradation by using the subfield method. FIG. 2 shows a configuration of the driving device 100 when performing the gradation driving based on the selective erase address method.
FIG. 3 is a diagram showing application timings of various drive pulses applied to column electrodes and row electrodes of the PDP 10 within one subfield.

[0007] First, the driving device 100 simultaneously applies a negative reset pulse RP _x row electrodes X ₁ to X _n, further a positive reset pulse RP _Y to the row electrodes Y ₁ to Y _n, respectively
(Simultaneous reset process Rc). These reset pulses RP _x
And in response to the application of RP _Y, all the discharge cells in the PDP10 is reset discharge, uniform predetermined amount of wall charge in each discharge cell is formed. As a result, all the discharge cells are initially set to “light emitting cells”.

[0008] Next, the driving device 100
Pixel data pulse group DP for each row corresponding to the signal₁~
DP_nAre sequentially applied to the column electrode D_1-mAnd apply each image
The scanning pulse S is applied at the application timing of the elementary data pulse group DP.
P is generated, and this is ₁~ Y_nTo the line
(Pixel data writing process Wc). At this time, the scanning pulse SP
Is applied to the “row” and the high-voltage pixel data pulse is applied
Discharge only to the discharge cell at the intersection with the "column"
Discharge), and the wall charges remaining in the discharge cell
Selectively erased. This allows the simultaneous reset line
In step Rc, the discharge cell initialized to the “light emitting cell” state
Changes to a “non-light emitting cell”. On the other hand, the scanning pulse SP
Is applied, but a low-voltage pixel data pulse is applied
Cells formed crossing the "rows" and "columns"
Does not cause the selective erase discharge as described above,
The state initialized in the reset process Rc, that is, "light emission"
The state of the cell "is maintained.

[0009] Next, the drive apparatus 100 repeats the row electrodes X ₁ ~ sustain pulse IP _X of but such positive polarity shown in FIG. 2
X _n and the sustain pulse IP _X is applied to the row electrode X
₁ During the application that has not been period to to X _n, the row electrodes Y ₁ to Y repeated sustain pulse IP _Y of positive polarity as shown in FIG. 2
_n (light emission sustaining step Ic). Incidentally, the number of times that these sustain pulses IP _X and IP _Y are applied, a number set in advance in accordance with the weighting of each subfield. Here, only the discharge cells in which the wall charges remain, that is, the “light-emitting cells” are those sustain pulses IP.
Discharge every time _{the X} and IP _Y are alternately applied to (sustain discharge). That is, only the discharge cells set as "light emitting cells" in the pixel data writing process Wc repeat light emission accompanying the sustain discharge by the number of times corresponding to the weight of the subfield, and maintain the light emitting state. .

[0010] Next, the drive apparatus 100 applies an erase pulse EP, such is shown in Figure 2 to the row electrodes X ₁ to X _n (erasing step E). As a result, all the discharge cells are simultaneously erase-discharged, and the wall charges remaining in each discharge cell are extinguished. As described above, when the gradation drive is performed by employing the selective erase address method, first, wall charges are formed in all the discharge cells (simultaneous resetting process Rc), and then the wall charges are generated in accordance with the video signal. A selective erase discharge is generated only in the discharge cells to selectively erase the wall charges (pixel data writing process W
c). By such a series of operations, each discharge cell is set to a state (“light-emitting cell” or “non-light-emitting cell”) according to the video signal, and only the “light-emitting cell” is sustained by the number of times corresponding to the subfield weighting. Then, the state of the light emission is maintained (light emission maintaining step Ic).

However, there is a case where there is a discharge cell in which the selective erase discharge is generated more strongly than a predetermined value due to a variation in quality in manufacturing the PDP 10.
At this time, even if the selective erasure discharge is generated in the discharge cells, wall charges of the opposite polarity are formed as excess charges on one of the row electrodes X and Y. That is, the wall charges to be erased originally remain. Such a discharge cell in which excess charges are formed may cause erroneous sustain discharge light emission in the light emission sustain step Ic, and thus has a problem of deteriorating display quality.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. For example, a defective discharge cell in which an excessive wall charge is formed after a selective erase discharge exists in a PDP. It is an object of the present invention to provide a method of driving a plasma display panel that can drive the PDP without deteriorating display quality.

[0013]

A driving method of a plasma display panel according to the present invention comprises a plurality of row electrode pairs arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrode pairs. A method of driving a plasma display panel in which a discharge cell corresponding to one pixel is formed at each intersection, wherein a reset pulse is applied to each of the row electrode pairs to cause each of the discharge cells to perform a reset discharge. A reset step of forming wall charges in the discharge cells, and applying a pixel data pulse corresponding to pixel data to the column electrodes and simultaneously applying a scan pulse to one of the row electrode pairs to select each of the discharge cells. A plurality of sustain pulses are alternately applied to each of the row electrode pairs, and a plurality of sustain pulses are alternately applied to each of the row electrode pairs. Performing a light emission sustaining step of repeatedly generating sustain discharge light emission only in the discharge cells in which wall charges remain, and applying the pulse width of the sustain pulse applied first in the light emission sustaining step thereafter. It is shorter than the pulse width of the sustain pulse.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel based on a driving method according to the present invention. As shown in FIG. 3, the plasma display device includes a PDP 10 as a plasma display panel, an A / D
It comprises a converter 1, a drive control circuit 2, a memory 4, an address driver 6, and a drive unit including a first sustain driver 7 and a second sustain driver 8.

The PDP 10 has m column electrodes D _{1 to} D _m as address electrodes, and n row electrodes X _{1 to} X _n and a row electrode Y ₁ arranged so as to cross each of the column electrodes. ~
Y _n . At this time, a pair of the row electrode X and the row electrode Y forms a row electrode corresponding to one row in the PDP 10. The column electrodes D and the row electrodes X and Y are covered with a dielectric layer with respect to the discharge space, and have a structure in which a discharge cell corresponding to one pixel is formed at an intersection between each row electrode pair and a column electrode. I have.

The A / D converter 1 samples an input analog input video signal in accordance with a clock signal supplied from the drive control circuit 2 and converts the sampled analog video signal into N-bit pixel data corresponding to each pixel. D and convert it to memory 4
To supply. The memory 4 sequentially writes the pixel data D according to a write signal supplied from the drive control circuit 2.
By such a writing operation, one screen (n
When writing for (row, m columns) is completed, the memory 4 divides the pixel data D _11-nm for one screen into each bit digit according to the read signal supplied from the drive control circuit 2, and The data read from the first row to the n-th row for each row are sequentially supplied to the address driver 6 as drive pixel data bit groups DB _{1 to} DB _n .

The drive control circuit 2 responds to the horizontal synchronizing signal and the vertical synchronizing signal in the input video signal by
A clock signal for the / D converter 1 and a write and read signal for the memory 4 are generated. Further, the drive control circuit 2 sets one field period in the input video signal to N.
The sub-fields are divided into sub-fields, and various driving pulses as shown in FIG.
, A first sustain driver 7 and a second sustain driver 8
To each of the

In FIG. 4, first, the simultaneous reset process R
c, the first sustain driver 7 resets the negative polarity.
TP Pulse_xTo row electrode X₁~ X_nIs applied. Such re
Set pulse RP_xAnd the second sustained
Driver 8 has positive reset pulse RP_YIs the row electrode Y₁~
Y_nIs applied. These reset pulses RP_xAnd RP _Y
, All the discharge cells in the PDP 10
Reset discharge occurs. After the end of such reset discharge, discharge
The row electrodes X and Y in the cell are shown in FIG.
Thus, a predetermined amount of wall charge Q⁺And wall charge Q^-Formed
It is. As a result, the discharge cells are initially set in the “light emitting cell” state.
Is set.

In the next pixel data writing step Wc, the address
The driver 6 reads the drive sequentially read from the memory 4.
Video elementary data bit group DB₁~ DB_nPixel corresponding to each
Data pulse group DP₁~ DP_nThat occur sequentially,
Column electrode D_1-mTo be applied. The address driver 6
Represents one data bit in the driving pixel data bit group DB.
If the bit is at a logic level “0”, for example,
Generates an elementary data pulse while at logic level "1"
In this case, a low voltage (0 volt) pixel data pulse is generated.
Column electrode D_1-mIs applied. That is, address dry
The bus 6 applies one row (m) of the pixel data pulses to the above-described image.
Column electrode D as raw data pulse group DP_{1- m}To apply
It is. In the pixel data writing process Wc, the second
The stin driver 8 is provided for the pixel data pulse group DP.
In synchronization with the application timing, the scanning pattern as shown in FIG.
And a row electrode Y is generated.₁~ Y_nSequentially applied to
Go.

At this time, the "row" to which the scanning pulse SP is applied
As shown in FIG. 5 (B ₀ ), a selective erase discharge is generated only in the discharge cell at the intersection of the “column” to which the high-voltage pixel data pulse is applied and remains in the discharge cell. Wall charges disappear. That is, this discharge cell changes to a “non-light emitting cell” state. However, in the discharge cells in which the selective erasure discharge due to variations in quality in the manufacturing will be occurring stronger than predetermined, after completion of the selective erasing discharge, the row electrode Y side, it is shown in FIG. 5 (C ₀₎ As a result, wall charges Q ⁺ as excess charges are formed.

Meanwhile, although the scan pulse SP is applied, since the discharge cells where a low-voltage pixel data pulse is applied, selective erasure discharge as shown in FIG. 5 (B ₁₎ is not caused, the pixel data The state shown in FIG. 5A is maintained during the execution period of the writing process Wc. That is, FIG.
As shown in (B ₁ ) and FIG. 5 (C ₁ ), the state of the “light emitting cell” as shown in FIG. 5 (A) is maintained as it is.

Next, in the light emission sustaining step Ic, the second sustain
The driver 8 has j positive electrodes as shown in FIG.
Sex maintenance pulse IP_Y1~ IP_YjTo PDP10
Pole X _1-nTo be applied. Further, the sustain pulse IP
_Y1~ IP_YjDuring each non-application period, the first sustain
The iva 7 maintains the positive polarity of j pieces as shown in FIG.
Pulse IP_X1~ IP_XjTo the row electrode X of the PDP 10 sequentially._1-n
To be applied. In addition, the sustain pulse IP_XAnd IP_YApplication of
The number of times (2j) depends on the weight of this subfield.
Is set in advance.

Here, in the light emission sustaining process Ic,
And the sustain pulse applied first to the row electrode pairs X and Y
IP_Y1Is a relatively short pulse width, and its pulse width W1
Is the sustain pulse IP applied thereafter_X1Pulse width W
2, and sustain pulse IP_Y2~ IP _Yj, Sustain pulse IP_X2
~ IP_XjEach pulse width is shorter than W3. or,
Second sustain pulse applied to row electrode pair X, Y
IP_X1Is a relatively long pulse width, and its pulse width W2
Is the sustain pulse IP applied thereafter_X2~ IP_Xj, Wei
Pulse IP_Y2~ IP_YjLonger than each pulse width W3
I have.

At this time, in the discharge cell which should be in the "non-light-emitting cell" state (state in which no wall charge is present), but an excessive charge is formed as shown in FIG. 5 (C ₀ ), the application of the sustain pulse IP _Y1, FIG 5 (D ₀₎
As shown in FIG. 2, an erase discharge is generated between the row electrodes X and Y. After such an erase discharge, the excess charge disappears as shown in FIG. 5 (E ₀ ). Therefore, this discharge cell changes to a good "non-light emitting cell" in which no excess charge exists.

On the other hand, in a discharge cell in a "light emitting cell" state as shown in FIG. 5 (C ₁ ), even if the above-mentioned sustain pulse IP _Y1 is applied to the row electrode Y, it is shown in FIG. 5 (D ₁ ). like,
No sustain discharge is generated. This is because the polarity of the sustain pulse IP _Y1 is opposite to the polarity of the wall charges remaining on the row electrode Y, and as a result, the potential difference between the row electrodes X and Y becomes equal to or less than the firing voltage. However, as shown in FIG. 4, when the second sustain pulse IP _X1 is applied to the row electrode X, as shown in FIG. 5 (E ₁ ), the voltage of the sustain pulse IP _X1 becomes the voltage value due to the wall charges. The voltages are added and the row electrodes X,
The potential difference between Y becomes equal to or higher than the discharge starting voltage, and the first sustain discharge is generated between the row electrodes X and Y. Thereafter, the sustain pulses IP _Y2 , IP _X2 ,..., IP _Yj , IP _Xj ,
Sustain discharge every time the sustain pulse IP _Y and the sustain pulses IP _X are alternately applied is occurring, repeat the light emission accompanying the sustain discharge.

The sustain pulse IP_X1Of the pulse width W2 of
Sustain pulse IP applied thereafter _X2~ IP_XjEach pa
The reason why the length is longer than the loose width W3 is as follows.
To generate sustain discharge quickly, a certain amount of prime
Particles must remain in the discharge cells. Heel
Priming particles in the simultaneous reset process Rc
It is generated in the discharge cell by the reset discharge.
Since the amount decreases with time, the sustain pulse IP_X1Mark
There is a delay between the application and the occurrence of the sustain discharge.
You. At this time, even after the sustain discharge has occurred,
Tte sustain pulse IP_X1If you do not continue to apply
The wall charges in the cell cannot be kept well. There
In the light emission sustaining process Ic, the row electrode X is first
Sustain pulse IP applied to_X1The pulse width of
is there.

Finally, in the erasing step E, the second sustain driver 8 generates an erasing pulse EP and applies it to each of the row electrodes Y _{1 to} Y _n . By the application of the erasing pulse EP, an erasing discharge is generated in all the discharge cells of the PDP 10, and the wall charges remaining in all the discharge cells disappear. That is, by such an erase discharge, the PD
All the discharge cells at P10 become "non-light-emitting cells".

By performing the above-described series of operations in each subfield, an image having a luminance corresponding to the input video signal is displayed on the screen of the PDP 10.

[0029]

As described in detail above, in the present invention,
In the light emission sustaining step, the pulse width of the sustain pulse applied first is shorter than the pulse width of the sustain pulse applied thereafter. Therefore, even if there are discharge cells in the plasma display panel where excessive wall charges are formed after the selective erase discharge, the excessive sustain charges are erased by the first sustain pulse. Therefore, the predetermined display quality can be maintained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a plasma display device.

FIG. 2 is a diagram showing application timings of various drive pulses applied to column electrodes and row electrodes of a PDP within one subfield.

FIG. 3 is a diagram showing a schematic configuration of a plasma display device according to the present invention.

FIG. 4 is a diagram showing application timings of various driving pulses applied to column electrodes and row electrodes of the PDP 10 based on the driving method according to the present invention.

FIG. 5 is a diagram showing a state transition in a discharge cell.

[Explanation of Signs of Main Parts]

 2 Drive control circuit 6 Address driver 7 First sustain driver 8 Second sustain driver 10 PDP

Claims (2)

[Claims] 1. A discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrode pairs arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrode pair. A reset step of applying a reset pulse to each of the row electrode pairs to cause each of the discharge cells to perform a reset discharge, thereby forming wall charges in the discharge cells. A pixel data pulse for erasing the wall charges by applying a pixel data pulse corresponding to data to the column electrode and simultaneously applying a scan pulse to one of the row electrode pairs to selectively erase and discharge each of the discharge cells. And applying a plurality of sustain pulses alternately to each of the row electrode pairs to repeatedly generate sustain discharge light emission only in the discharge cells in which the wall charges remain. A plasma display panel, wherein a pulse width of the sustain pulse applied first in the light emission sustaining step is shorter than a pulse width of the sustain pulse applied thereafter. Drive method. 2. The plasma display according to claim 1, wherein a pulse width of the sustain pulse applied second in the light emission sustaining step is longer than a pulse width of the sustain pulse applied thereafter. Panel driving method.