JP2000299378A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve accuracy in manufacturing of a wiring, while keeping a current density in wiring. SOLUTION: After a wiring forming conductive film is formed on a semiconductor wafer 1, a resist film 12a is formed thereon. With an etching mask of this resist film 12a, the conductive film is etched and thinned to a halfway through in thickness in an isotropic dry-etching step. Then, by switching the etching treatment from isotropic dry etching to anisotropic dry etching, a wiring 11L is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a wiring processing technique for a semiconductor device.

[0002]

2. Description of the Related Art Wiring processing techniques are roughly classified into two processing techniques, namely, a wet etching technique and a dry etching technique. In the case of the wet etching technique, it is difficult to control the processing dimensions because the etching proceeds isotropically. Also, since it is necessary to perform incidental work such as light asher and post bake before and after wet processing,
It takes time, lowers throughput and delays automation.

On the other hand, in the case of the dry etching technique, anisotropic patterning is possible by optimizing conditions, so that fine processing of wiring is possible. Further, the processing is simpler and more automated than the wet etching technique. However, in the case of the dry etching technique, since the etching selectivity with a photoresist (hereinafter simply referred to as a resist) film serving as an etching mask is about 2 which is lower than that in the case of the wet etching process, a conductor which can be processed with good dimensional accuracy is obtained. The thickness of the film is up to about 1 μm. This is mainly due to the insufficient thickness of the resist film serving as an etching mask, but the limit of the thickness of the resist film that can be patterned is about 2 μm from the viewpoint of resolution and throughput. Therefore, from the viewpoint of processing dimensional accuracy, the conductor film for forming the wiring cannot be made too thick. However, for example, a power MOSFET (Metal Oxide Semiconductor Field Effe
In a semiconductor device requiring a large current, such as a ct transistor, it is necessary to form a thick wiring to secure a current density in the wiring. In particular, in recent years, since the width dimension of the wiring tends to be reduced in accordance with the demand for miniaturization of the wiring, it is required that the dimension in the thickness direction of the wiring be further increased from the viewpoint of securing the current density in the wiring. ing. As described above, as the thickness of the wiring increases, in a region where a plurality of wirings are arranged adjacent to each other, voids are formed between adjacent wirings in the insulating film covering the wiring, or the insulating film is formed. In this case, there is a problem that a crack is formed at a corner formed by the wiring and the base.

As a technique for solving such a problem,
In the technique studied by the present inventors, after removing a part of the thickness of the wiring conductor film by wet etching using the resist film as an etching mask, the remaining wiring conductor film is removed by dry etching. I have to. According to this technique, the taper is formed at the upper corner of the wiring without lowering the precision of the wiring width dimension, and the wiring thickness is secured, thereby significantly reducing the current density of the wiring. Without inviting, it is possible to improve the coverage of the insulating film covering the wiring and suppress the generation of the voids and cracks.

[0005] For wiring technology, see, for example, Plus Journal Inc., published on November 20, 1994, “Monthly Semiconductor World December 1994”, p.
152-188, there is a description of the possibility of aluminum wiring.

[0006]

However, the present inventor has found that the wiring processing technology studied by the inventor has the following problems.

That is, since wet etching is performed at the time of wiring processing, necking is generated at a predetermined position in the longitudinal direction of the wiring so as to be depressed in the width direction of the wiring.
There is a problem that wiring is corroded, and additional work such as light asher and post-bake requires time, which lowers throughput and delays automation.

An object of the present invention is to provide a technique capable of improving the processing accuracy of wiring.

An object of the present invention is to provide a technique capable of improving the processing accuracy of a wiring while securing the current density of the wiring.

Another object of the present invention is to provide a technique capable of suppressing corrosion of wiring and improving the reliability of wiring.

It is another object of the present invention to provide a technique capable of improving the throughput of wiring processing.

Another object of the present invention is to provide a technique capable of promoting automation of wiring processing.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor device according to the present invention, (a) a step of forming a conductor film for forming a wiring on a semiconductor substrate, and (b) a mask film is formed on the conductor film for forming the wiring. Step (c) After the step (b), the isotropic dry etching process is performed on the wiring-forming conductor film using the mask film as an etching mask, thereby forming the wiring-forming conductor film. (D) after the step (c), performing an anisotropic dry etching process on the remaining conductive film for forming a wiring, using the mask film as an etching mask. And removing the conductive film for forming the wiring to form the wiring.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. In the present embodiment, a p-channel type MISFET (Me
tal Insulator Semiconductor Field Effect Transisto
r) is abbreviated as pMIS, and an n-channel MISFET is abbreviated as nMIS.

(Embodiment 1) In Embodiment 1, although not particularly limited, a case where the present invention is applied to, for example, a method of manufacturing a power MISFET for mobile satellite communication will be described. FIG. 1 shows a manufacturing flow chart of the semiconductor device, and FIGS. 2 to 6 show cross-sectional views of main parts of a semiconductor wafer (semiconductor substrate) 1 during the manufacturing process. FIG. 7 shows the dependence of the etching rate and selectivity of aluminum and the resist film on the high frequency (RF) output. The power MISFET formation region is shown on the left side of FIGS. 2 to 6, and other regions are shown on the right side.

The semiconductor wafer 1 shown in FIG. 2 is made of, for example, a p-type silicon single crystal having a substantially circular planar shape, and an epitaxial layer 1E made of, for example, a p ^- type silicon single crystal is formed on the main surface thereof. ing. A substrate electrode is formed on the back side.

On the main surface of such a semiconductor wafer 1, for example, 5
A horizontal n-channel power MISFET QL of GHz is formed. The power MISFET QL is an element that operates when carriers move along the main surface of the semiconductor wafer 1.

The power MISFET QL includes a p-type semiconductor region 2, a pair of source / drain semiconductor regions 3, 4, a gate insulating film 5, a gate electrode 6, and extraction electrodes 7, 8. I have.

The p-type semiconductor region 2 has a power MISFE
It has a function of setting the threshold voltage of TQL, and the impurity distribution of the semiconductor region 2 is formed at least in the epitaxial layer 1E immediately below the gate electrode 5. This p-type semiconductor region 2 is a p ⁺ -type semiconductor region 2
a, and is electrically connected to the extraction electrode 7. The p-type semiconductor region 2 and the p ⁺ -type semiconductor region 2a
For example, boron or boron difluoride is introduced.

The semiconductor region 3 forms the source of the power MISFETQL is, n ⁺ -type semiconductor region 3a and the n ⁺
Semiconductor region 3b, and both regions are formed so as to be surrounded by the p-type semiconductor region 2 and the p ⁺ -type semiconductor region 2a. Both the n ⁺ -type semiconductor region 3a and the n ⁺ -type semiconductor region 3b are, for example, doped with phosphorus or arsenic, and are electrically connected to each other. The n ⁺ -type semiconductor region 3a is formed adjacent to the channel of the power MISFET QL. On the other hand, the n ⁺ type semiconductor region 3b is formed at a plane position separated from the channel by the plane dimension length of the n ⁺ type semiconductor region 3a, and is electrically connected to the extraction electrode 7.

The semiconductor region 4 forming the drain of the power MISFET QL is an n ⁻ type semiconductor region 4.
a and an n ⁺ -type semiconductor region 4b. Both the n ⁻ type semiconductor region 4a and the n ⁺ type semiconductor region 4b are, for example, doped with phosphorus or arsenic and are electrically connected to each other. The n ^- type semiconductor region 4a is formed adjacent to the channel of the power MISFET QL. On the other hand, the n ⁺ type semiconductor region 4b has n ⁻
It is formed at a plane position separated from the channel by the plane dimension length of the semiconductor region 4a of the mold, and is electrically connected to the extraction electrode 8.

The gate insulating film 5 is made of, for example, a silicon oxide film. The gate electrode 6 is made of, for example, a single film of a low-resistance polysilicon film. However, the gate electrode 6 is not limited to a single film of a low-resistance polysilicon film but can be variously modified. For example, a laminated film formed by laminating a silicide film such as tungsten silicide on a low-resistance polysilicon film. Alternatively, a laminated film formed by laminating a metal film such as tungsten on a low-resistance polysilicon film via a barrier film such as tungsten nitride or the like may be used.

Further, both the extraction electrodes 7 and 8 are made of, for example, a low-resistance polysilicon film. The extraction electrode 7 is connected to the p ⁺ -type semiconductor region 2a and the n ⁺ -type semiconductor region 3 through the connection hole 10a formed in the interlayer insulating film 9a as described above.
b, and the extraction electrode 8 is electrically connected to the interlayer insulating film 9a.
Is electrically connected to the n ⁺ -type semiconductor region 4b through the connection hole 10b formed as described above. The interlayer insulating film 9a is made of, for example, a silicon oxide film, and an interlayer insulating film 9b made of, for example, a silicon oxide film is formed thereon so as to cover the extraction electrodes 7 and 8. Connection holes 10c and 10d are formed in the interlayer insulating film 9b so that the extraction electrodes 7 and 8 are exposed.

First, as shown in FIG. 3, a conductor film 11 for forming a wiring is formed on such a semiconductor wafer 1 by a sputtering method or the like (step 100 in FIG. 1). The conductor film 11 is made of, for example, aluminum, an aluminum-silicon alloy, an aluminum-copper alloy, an aluminum-silicon-copper alloy, or the like, and is electrically connected to the extraction electrodes 7, 8 through the connection holes 10c, 10d. Silicon added to the aluminum alloy has, for example, a function of improving alloy spike resistance, and is added at about 1%. Further, copper added to the aluminum alloy has a function of improving, for example, electromigration resistance. This conductor film 11 is made of a power MISFET QL
Is formed relatively thick in order to improve the current density in the wiring, and its thickness is, for example, 1.5 μm or more. In the first embodiment, the thickness of the conductor film 11 is, for example, about 1.75 μm.

Subsequently, a resist film 12 is formed on the conductor film 11.
is patterned by a usual exposure technique (step 102 in FIG. 1). For the resist film 12a, for example, an organic substance mainly containing cinnamic acid-based polyvinyl or phenol novolak-based resin is used. The resist film 12a after patterning may be irradiated with ultraviolet rays (UV) for the purpose of improving the heat resistance of the resist film against a rise in temperature during the later-described dry etching process. The thickness of the resist film 12a is thin from the viewpoint of resolution, throughput, and the like, and is, for example, about 2 μm or less. The technical idea of the present invention is particularly effective when applied to the case where it is necessary to make the resist film 12a thin and the conductor film 11 for wiring formation thick. According to the study of the present inventor, it is preferable to apply the technical idea of the present invention when the thickness of the conductor film 11 for forming a wiring is half or more of the thickness of the resist film 12a.

Thereafter, the following dry etching process is performed on the semiconductor wafer 1 (step 10 in FIG. 1).
3). That is, first, isotropic dry etching is performed on the semiconductor wafer 1 using the resist film 12a as an etching mask, so that a portion of the conductor film 11 is etched away as shown in FIG. Step 103a). In this etching process, the conductor film 11 is isotropically dry-etched, so that the conductor film 11 below the end of the resist film 12a is also partially scraped.
However, at this stage, etching is performed up to the middle thickness position of the conductor film 11, and the etching process is performed until the upper surface of the lower interlayer insulating film 9b is not exposed. The etching depth (thickness) at this time is such that when a protective film (insulating film) covering the wiring to be described later is formed, no void is formed between adjacent wirings, and the base of the wiring (the side surface of the wiring and the semiconductor). In the vicinity of (a corner formed by the substrate), cracks do not occur in the protective film, and current density of the wiring is secured. In the first embodiment, the depth (thickness: taper etching amount) is, for example, 0.8 μm.
It is about. Therefore, the etching end point at the time of this isotropic dry etching process is determined by the time for digging the depth (thickness). Assuming that the depth (thickness) to be dug is Y and the etching rate is X, the etching end point time can be obtained by Y / X (min).

As a specific example of the dry etching process at this time, the etching process is performed by discharging plasma in a state where chlorine gas is supplied into the etching process chamber and causing plasma ions to enter the main surface of the semiconductor wafer 1. A so-called reactive ion etching process (or reactive sputter etching) was performed. The etching pressure is, for example, about 8 mTorr, and the microwave output is, for example, 350 mTorr.
The measurement was performed at about mA, RF output was about 5 W, and the flow rate of chlorine gas was about 200 sccm, for example. Under these conditions, the conductor film 11 was almost isotropically etched away, and an etching selectivity with the resist film 12a of 8 or more was obtained. Therefore, even if the resist film 12a is thinned, it is possible to suppress a problem that the resist film 12a is scraped during the dry etching process, so that a decrease in pattern formation accuracy can be reduced. Also, the etching rate is
For example, it was 2.3 μm / min.

Here, it is considered that the reason why the conductive film 11 is isotropically etched and the resist selectivity is drastically improved is as follows. FIG. 7 shows, among the etching conditions, in particular, the RF applied output for controlling the energy at which ions enter the semiconductor wafer 1 and the conductive film 11.
4 shows the dependence on the etching rate and the etching selectivity of the resist film 12a. The RF output applied in dry etching of an aluminum-based (aluminum or the above aluminum alloy) conductor film in a normal semiconductor device is 40 W or more, and the etching selectivity is 2. If the RF output is decreased below this, the etching rate of the resist film 12a decreases, and conversely, the etching rate of the aluminum-based conductor film increases. FIG. 7 shows that the etching selectivity is improved.

It is known that in order to process an aluminum-based conductor film anisotropically, it is essential that a deposit is supplied from the resist film 12a and a sidewall deposit is formed on the side wall. An improvement in the selectivity with respect to the resist film 12a is nothing but a reduction in the supply of the deposit. Therefore, the formation of the sidewall becomes insufficient, and the aluminum-based conductor film is isotropically etched. The reason why the etching of the aluminum-based conductor film does not progress when the RF output is 0 (zero) W is that a deposit deposited in the etching chamber adheres to the semiconductor wafer, covers the surface of the aluminum-based conductor film, and activates radicals and the like. This is for inhibiting the reaction between the seed and the aluminum-based conductor film. That is, it is necessary to at least inject ions necessary to sputter and remove the deposits on the surface of the conductive film.
In the first embodiment, the RF output is 5 W or more,
Good results were obtained below W. This corresponds to an energy density of about 0.16 W / cm ^{2 to} 0.32 W / cm.
Equivalent to ² .

In the first embodiment, the reason that the conductor film 11 is not completely patterned is that the conductor film 11 is patterned only by the isotropic dry etching process. This is because the dimensional shift is large as compared with the case where the film is patterned, and it is impossible to cope with miniaturization. Therefore, in the first embodiment, after the isotropic dry etching process as described above, before the just etching, the process is switched to the anisotropic dry etching process (step 103b in FIG. 1). Thereby, the remaining conductor film 1 exposed from the resist film 12a
1 is removed, and a wiring 11L is formed as shown in FIG. The upper corner of the wiring 11L is shaved off to have a corner. That is, the upper corner of the wiring 11L is tapered. The line / space dimension of the wiring 11L is, for example, 2 /
It is about 2 μm. The condition of this anisotropic dry etching treatment is that the RF output is
For example, it was obtained by changing to 5 to 50 W. Detection of the end point of the anisotropic dry etching process can be performed by measuring a normal emission spectrum. According to such a method, it is possible to suppress the deterioration of the dimensional accuracy of the wiring 11 due to the removal of the resist film 12a during the etching process for forming the wiring pattern, so that the dimensional accuracy of the wiring 11L is improved. be able to.

Then, after the resist film 12a is removed by etching (step 104 in FIG. 1), as shown in FIG. 6, for example, a silicon oxide film alone or a silicon oxide film is formed on the main surface of the semiconductor wafer 1. A protective film 13 made of a laminated film with a silicon film is formed by a CVD method or the like. In the first embodiment, the taper is formed at the upper corner of the wiring 11L, so that the coverage of the protective film 13 on the wiring 11L can be improved. Thereby, the formation of voids between the adjacent wirings 11L can be suppressed. In addition, it is possible to suppress the occurrence of cracks at the base of the wiring 11L in the protective film 13. Therefore, it is possible to improve the reliability of the semiconductor device.

Next, an example of an etching apparatus used in the anisotropic dry etching process will be described. The magnetic field microwave dry etching apparatus 14 shown in FIG. 8 shows one example thereof. Between the loader cassette section 15A and the unloader cassette section 15B, each of a supply-side vacuum chamber 16, a dry etching processing chamber (discharge tube) 17, a transfer chamber 18, a resist ashing chamber 19, and a discharge-side vacuum chamber 20 are illustrated. 8 are arranged in order from left to right. Between the supply-side vacuum chamber 16 and the discharge-side vacuum chamber 20, the processing chambers are interconnected via shutters 21a to 21d. In each of the processing chambers, the degree of vacuum and the processing atmosphere can be independently controlled.

A cassette 22a accommodating a plurality of unprocessed semiconductor wafers 1 is mounted on the loader cassette section 15A, and the unprocessed semiconductor wafers 1 are supplied from the cassette 22a to the supply-side vacuum chamber 16. Has become.
The unprocessed semiconductor wafer 1 at this stage is in the state shown in FIG. The supply-side vacuum chamber 16 temporarily arranges the unprocessed semiconductor wafer 1 supplied from the loader cassette unit 15A on the table 24 through the opening / closing shutter 23, and then transfers the unprocessed semiconductor wafer 1 arranged on the table 24 to the unprocessed semiconductor wafer 1. The wafer can be transferred to the next stage dry etching chamber 17 via the swing arm 25.
In the dry etching processing chamber 17, the unprocessed semiconductor wafer 1 supplied from the supply-side vacuum chamber 16 is arranged on a table 26 in the dry etching processing chamber 17, and is formed on the main surface of the unprocessed semiconductor wafer 1. Conductive film 11 for wiring formation
(See FIG. 3 etc.) is subjected to the above dry etching treatment. The table 26 is electrically connected to an AC power supply 27 and is also used as an electrode. The high-frequency power value that can be applied to the table 26 can be changed to various values. Dry etching processing room 1
Reference numeral 7 is connected to each of a turbo pump 28 and a rotary pump 29 via a control valve 27. Further, the dry etching chamber 17 is connected to a gas supply system 30, and the gas supply system 30 is a chlorine-based gas capable of etching the conductive film 11, for example, Cl ₂ , BCl ₃ , S
Each of iCl ₄ is supplied by a predetermined amount (set value). Further, the microwave from the magnetron 32 is supplied to the dry etching processing chamber 17 through a hollow resonance tube surrounded by a solenoid coil 31. In such a dry etching chamber 17, it is possible to independently generate and control plasma and ion energy.

The transfer chamber 18 includes the dry etching chamber 1
The semiconductor wafer 1 that has been subjected to the dry etching process at 7 can be transferred to the next-stage resist ashing processing chamber 19 via the swing arm 33. The transfer chamber 18 is connected to each of a turbo pump 35 and a rotary pump 36 via a control valve 34. The turbo pump 35 connected to the transfer chamber 19
Is also used as a pump for the subsequent resist ashing processing chamber 19.

In the resist ashing processing chamber 19, the processed semiconductor wafer 1 transferred from the preceding dry etching processing chamber 17 is arranged on a table 38 containing a heater 37, and the conductive film on the processed semiconductor wafer 1 is removed. The residue is removed and the resist film 12 on the conductor film 11 is removed.
a (see FIG. 5 and the like) can be removed by a resist ashing process. The resist ashing processing chamber 19 is connected to a turbo pump 35 via a control valve and to a rotary pump 40 via a control valve 39. This resist ashing processing chamber 19 is connected to a gas supply system 41. The gas supply system 41 includes oxygen, CF ₄ and CHF ₃
Etc. can be supplied. In the resist ashing processing chamber 19, the resist film 12a (see FIG. 5 and the like)
The processed semiconductor wafer 1 from which the gas has been removed is placed in the vacuum chamber 2 on the discharge side.
0. Discharge side vacuum chamber 20
Has a structure in which the processed semiconductor wafer 1 transported from the resist ashing processing chamber 19 is temporarily disposed on a table 42, and is transported from the table 42 to the unloader cassette section 15B through the opening / closing shutter 43. The unloader cassette section 15B has a structure in which the processed semiconductor wafers 1 are sequentially stored in a cassette 22b mounted therein.

FIG. 9 shows another dry etching apparatus 44 that can be used in the first embodiment, and includes a central transfer chamber 45 and a loader / unloader chamber 46 disposed around the transfer chamber 45. And an anisotropic dry etching chamber 48. The transfer chamber 45 holds the semiconductor wafer 1 in a state where the semiconductor wafer 1 is held on a transfer member 45A installed in the chamber.
Is a mechanism for transporting to the respective chambers. The loader / unloader chamber 46 is a loading / unloading mechanism for loading / unloading the semiconductor wafer 1 into / from the dry etching apparatus 44.

The isotropic dry etching processing chamber 47 is a processing section for performing the above-mentioned isotropic etching processing, and here, an ordinary parallel plate type etching apparatus is used.
The semiconductor wafer 1 is arranged on the lower electrode 47A. This lower electrode 47A is grounded. Also, the lower electrode 47
A high-frequency power supply 4 is connected to the upper electrode 47B facing in parallel with A.
7C is electrically connected. That is, the upper electrode 4
High frequency power can be applied to the 7B side.

The anisotropic dry etching processing chamber is a processing section for performing the above-described anisotropic etching processing, and an ordinary parallel plate type etching apparatus is used. Lower electrode 48
The semiconductor wafer 1 is arranged on A. This lower electrode 48
A high-frequency power supply 48C is electrically connected to B, so that high-frequency power can be applied. A high frequency power supply 48C is electrically connected to the upper electrode 48B opposed to the lower electrode 48A in parallel. This upper electrode 48
A is grounded.

When the dry etching apparatus 44 is used, the existing dry etching technique can be used as it is in terms of both hardware and software, and a new manufacturing apparatus and software are developed to realize the technical idea of the present invention.
Since it is not necessary to create the semiconductor device, the technical idea of the present invention can be easily introduced into a specific semiconductor device manufacturing line.

FIG. 10 shows still another dry etching apparatus 49 that can be used in the first embodiment. The dry etching device 49 is basically a parallel plate type etching device. The semiconductor wafer 1 is arranged on the lower electrode 49A. Lower electrode 49A and upper electrode 49 arranged so as to face parallel thereto
B is a high-frequency power source 4 via a splitter 49C.
9D. The splitter 49C is a component that selectively supplies the high-frequency power from the high-frequency power supply 49D to either the lower electrode 49A or the upper electrode 49B, thereby making the etching process isotropic (or anisotropic). It is possible to switch from anisotropic to isotropic). For example, when it is desired to perform an isotropic dry etching process, high-frequency power may be applied to the upper electrode 49B. In the case of performing an anisotropic dry etching process, the lower electrode 49A on which the semiconductor wafer 1 is disposed is used.
High-frequency power may be applied to the power supply. Processing chamber forming body 49E
Is a component forming the etching chamber and is grounded.

The use of the dry etching apparatus 49 is equivalent to the use of a parallel plate type dry etching apparatus having a relatively simple structure, and therefore has the effect of being small in size and easy to use.

As described above, in the first embodiment, the following effects can be obtained.

(1) In a semiconductor device having a power MISFET, the wiring 1 is kept while keeping the thickness of the wiring 11L.
1L processing dimensional accuracy can be improved. Therefore, it is possible to promote downsizing of the semiconductor device while securing the current density of the wiring 11L.

(2) In a semiconductor device having a power MISFET, wet etching is not used when processing a relatively thick wiring 11L, so that corrosion of the wiring can be suppressed and the reliability of the wiring can be improved. It is possible to do. Therefore, the yield and reliability of the semiconductor device having the power MISFET can be improved.

(3) In a semiconductor device having a power MISFET, a wet etching process is not used when processing a relatively thick wiring 11L, so that it is possible to improve the wiring processing throughput. Therefore,
Since the mass productivity of the semiconductor device can be improved, cost reduction of the semiconductor device having the power MISFET can be promoted.

(4) In a semiconductor device having a power MISFET, since a wet etching process is not used when processing a relatively thick wiring 11L, automation of wiring processing can be promoted. Therefore, the mass productivity of the semiconductor device can be improved, so that the power M
It is possible to promote cost reduction of a semiconductor device having an ISFET.

(Embodiment 2) In Embodiment 2, a power MISFET and a CMIS (Complimentary MI
S) A case where the technical concept of the present invention is applied to a semiconductor device having a circuit and a bipolar transistor on the same semiconductor substrate will be described. 11 to 16 are main-portion cross-sectional views of the semiconductor device during a manufacturing step thereof. Note that FIG.
FIG. 13 is an enlarged sectional view of a main part of the semiconductor wafer at the time of the step of FIG. 12;

As shown in FIG. 11, in the semiconductor wafer 1, boundary regions between the formation region of the power MISFET, the formation region of the CMIS circuit, and the formation region of the bipolar transistor have p ^{+ +} for isolation between elements or within the element.
A semiconductor region 50 is formed.

In the region where the power MISFET is formed, for example, a vertical n-channel power MISFET QV is formed. The power MISFET QV is an element that operates when carriers move in the thickness direction of the semiconductor wafer 1. In the formation region of the power MISFET, n ⁺
The type semiconductor region 51a is a region for forming the drain of the power MISFET QV, and is formed, for example, by dispersing phosphorus or arsenic at the bottom of the p-type epitaxial layer 1E and in the vicinity thereof. The p-type epitaxial layer 1E and the p-type semiconductor region 52 above the p-type epitaxial layer 1E are regions for forming the channel of the power MISFET QV, and both are formed by introducing, for example, boron or boron difluoride. The impurities in the p-type semiconductor region 52 are
Are distributed over a predetermined depth from the main surface of the. Also,
A part of the p-type semiconductor region 52 has a power M
It is formed so as to overlap the gate electrode 53 of the ISFET QV. Gate electrode 53 is formed on the main surface of semiconductor wafer 1 via gate insulating film 54. Since the structures and materials of the gate electrode 53 and the gate insulating film 54 are the same as those of the gate electrode 6 and the gate insulating film 5 of the first embodiment, the description is omitted. The n ⁺ -type semiconductor region 55 included in the p-type semiconductor region 52 has a power MISFE
This is a region for forming a source of TQV, for example, phosphorus or arsenic is introduced. Further, the n ⁺ type semiconductor region 5
5 is formed so that a part thereof slightly overlaps the end of the gate electrode 53 in a plane. The n ⁺ -type semiconductor region 56 is a region for forming the drain of the power MISFET QV.
Are formed over the n ⁺ -type semiconductor region 51a from the main surface. Thereby, the n ⁺ type semiconductor region 5
Reference numeral 6 is electrically connected to the n ⁺ type semiconductor region 51a.

In the area where the CMIS circuit is formed,
The n ⁺ type semiconductor region 51b is formed by, for example, distributing phosphorus or arsenic at the bottom of the p-type epitaxial layer 1E and in the vicinity thereof. An n-well 57 is formed in the p-type epitaxial layer 1E. For example, phosphorus or arsenic is introduced into the n-well 57.
In this n-well 57, pMISQP is formed. The pMISQP has a pair of p ⁺ -type semiconductor regions 58 for source and drain formed in the n-well 57, a gate insulating film 59, and a gate electrode 60. p
For example, boron or boron difluoride is introduced into the ⁺ type semiconductor region 58. Since the structures and materials of the gate insulating film 59 and the gate electrode 60 are the same as those of the gate insulating film 5 and the gate electrode 6 of the first embodiment, the description is omitted. An nMISQN is formed in the p-type epitaxial layer 1E in the region where the CMIS circuit is formed. The nMISQN is an n ⁺ type semiconductor region 61 for source / drain formed in the epitaxial layer 1E.
And a gate insulating film 59 and a gate electrode 60. For example, phosphorus or arsenic is introduced into the n ⁺ type semiconductor region 61. pMISQP and nMISQN
Is a horizontal type, and its channel is the gate electrode 6
Directly below 0, it is formed between the source / drain semiconductor regions.

Further, in the formation region of the bipolar transistor, for example, a lateral npn bipolar transistor Q
BL is formed. The n ⁺ type semiconductor region 61 has np
a collector region of the n bipolar transistor QBL;
It is electrically connected to the n ⁺ type semiconductor region 62 and is drawn out to the main surface of the semiconductor wafer 1. n ⁺ type semiconductor region 6
For example, phosphorus or arsenic is introduced into 1, 62. A p-type semiconductor region 63 is formed in the p-type epitaxial layer 1E on the n ⁺ -type semiconductor region 61.
The p-type semiconductor region 63 is a base region of the npn bipolar transistor QBL, and is formed by introducing, for example, boron. Further, an n-type semiconductor region 64 is formed in the p-type semiconductor region 63 for the base region. The n-type semiconductor region 64 is an emitter region of the npn bipolar transistor QBL, and is formed by, for example, introducing phosphorus or arsenic.

On the main surface of such a semiconductor wafer 1,
A field insulating film 65 is formed. The field insulating film 65 is made of, for example, a silicon oxide film and is formed relatively thick. Furthermore, on the main surface of the semiconductor wafer 1, an interlayer insulating film 9c made of, for example, a silicon oxide film is formed, thereby covering the gate electrodes 53 and 60 and the field insulating film 65. This interlayer insulating film 9
c, connection holes 10e to 10e reaching the semiconductor wafer 1
k, 10 m are perforated. N ⁺ from the connection hole 10e
The semiconductor region 56 of the mold is exposed. From the connection hole 10f, the n ⁺ type semiconductor region 55 and the p type semiconductor region 5
2 are exposed. From the connection hole 10g, p ⁺ for separation is used.
The semiconductor region 50 of the mold is exposed. A p ⁺ type semiconductor region 58 for the source and drain of pMISQP is exposed from the connection hole 10h. NM from the connection hole 10i
N ⁺ type semiconductor region 6 for source / drain of ISQN
1 is exposed. From the connection holes 10j, 10k, and 10m, an n ⁺ -type semiconductor region 62 for the collector, a p-type semiconductor region 63 for the base, and an n-type semiconductor region 64 for the emitter of the bipolar transistor QBL are exposed. .

First, as shown in FIGS. 12 and 13, a conductor film 11 for forming a wiring is formed on a semiconductor wafer 1 by a sputtering method or the like. In the second embodiment,
As shown in FIG. 13, the conductor film 11 is
a and a conductive film 11b thereon. The conductor film 11b corresponds to the conductor film 11 of the first embodiment. The barrier conductor film 11a has a function of suppressing the diffusion of aluminum atoms in the conductor film 11b to the semiconductor wafer 1 side. For example, a silicide film such as molybdenum silicide (MoSi), titanium, titanium nitride, or the like is used. It is composed of a single film or a laminated film of titanium and titanium nitride. The thickness of the conductive film 11 is, for example, about 2.5 μm.

Subsequently, as in the first embodiment, after forming a resist film 12b on the conductive film 11, as shown in FIG. 14, using the resist film 12b as an etching mask, An etching process is performed by isotropic dry etching similarly to the first embodiment.
Here, similarly to the first embodiment, the conductor film 11 is not completely patterned, but is etched away to a depth (thickness) position in the middle of the conductor film 11. The depth (thickness: taper etching amount) is, for example, about 1.6 μm.

Thereafter, as shown in FIG. 15, the dry etching is switched from isotropic to anisotropic as in the first embodiment, so that the conductive film 11 is completely formed using the resist film 12b as an etching mask. To form wirings 11L1 to 11L8 (11L). In the second embodiment, the wiring 11L is formed of a laminated film of the barrier conductor film 11a and the conductor film 11b. C
The width of the wiring in the MIS circuit region is, for example, 4 μm, and the adjacent distance is, for example, about 2 μm. The wiring 11L1 is n ⁺
Wiring 11L2 electrically connected to the semiconductor region 56 of
Are a p-type semiconductor region 52 and an n ⁺ -type semiconductor region 53
The wiring 11L3 is electrically connected to the p-type semiconductor region 50 for isolation, and the wiring 11L4 is
The source / drain semiconductor region 58 of pMISQP is electrically connected, the wiring 11L5 is electrically connected to the source / drain semiconductor region 61 of nMISQN, and the wirings 11L6, 11L7 and 11L8 are respectively connected to the bipolar transistor QBL. Are electrically connected to an n ⁺ -type semiconductor region 62 for collector, a p-type semiconductor region 63 for base, and an n-type semiconductor region 64 for emitter.

After the formation of the wiring 11L in this manner, FIG.
As shown in FIG. 6, by forming a protective film 13 on the semiconductor wafer 1, the wiring 11L is covered and the power MIS is formed.
A semiconductor device having an FET, a CMIS circuit, and a bipolar transistor in the same semiconductor chip is manufactured. The arrows shown in the region where the power MISFET QV is formed indicate the direction in which the carriers of the power MISFET QV move.

In the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

(1) Power MISFE on semiconductor wafer 1
In addition to TQV, CMIS circuit and bipolar transistor Q
Even in the case of having BL, the same effect as in the first embodiment can be obtained.

(2) The same effect as in the first embodiment can be obtained when the wiring 11L is a laminated film of the barrier conductor film 11a and the conductor film 11b.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, in the first and second embodiments,
The case where a magnetic field type microwave plasma etching apparatus or a parallel plate type etching apparatus is used has been described, but the present invention is not limited to this, and various modifications can be made, for example, a coil wound around a dielectric chamber. A so-called inductively coupled plasma (Inductively coupled plasma) is used to perform etching by generating high-density plasma with inductively coupled energy in a chamber by applying a high frequency.
A coupled plasma etching apparatus or a surface wave plasma etching apparatus may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to a semiconductor device having a power MISFET, which is a field of application as a background, has been described. However, the present invention is not limited to this. (Dynamic Random Access Memory), SRAM
(Static Random Access Memory) or flash memory (EEPROM (Electrically Erasable Programm
The present invention can also be applied to the manufacturing technology of semiconductor memory products such as capable ROM)) and logic circuit products such as microprocessors.

[0065]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) It is possible to improve the processing dimensional accuracy of the wiring of the semiconductor device. Therefore, miniaturization of the semiconductor device can be promoted.

(2) While maintaining the thickness of the wiring of the semiconductor device, it is possible to improve the processing dimensional accuracy of the wiring. Therefore, it is possible to promote downsizing of the semiconductor device while securing the current density of the wiring.

(3) Since the wet etching is not used in processing the wiring of the semiconductor device, the corrosion of the wiring can be suppressed, and the reliability of the wiring can be improved. Therefore, the yield and reliability of the semiconductor device can be improved.

(4) Since the wet etching process is not used in processing the wiring of the semiconductor device, the throughput of the wiring processing can be improved. Accordingly, mass productivity of the semiconductor device can be improved, so that cost reduction of the semiconductor device can be promoted.

(5) Since wet etching is not used in processing the wiring of the semiconductor device, automation of wiring processing can be promoted. Accordingly, mass productivity of the semiconductor device can be improved, so that cost reduction of the semiconductor device can be promoted.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a manufacturing process of a semiconductor device of the present invention.

2 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device of FIG. 1 following FIG. 2;

4 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device of FIG. 1 subsequent to FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device of FIG. 1 following FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device of FIG. 1 following FIG. 5;

FIG. 7 is a graph showing the dependence of an etching rate and a selectivity of aluminum and a resist film on a high frequency (RF) output.

FIG. 8 is an explanatory diagram of an example of a dry etching apparatus used in a manufacturing process of the semiconductor device of FIG. 1;

FIG. 9 is an explanatory diagram of another example of the dry etching apparatus used in the manufacturing process of the semiconductor device of FIG. 1;

FIG. 10 is a diagram illustrating an example of a dry etching apparatus used in the manufacturing process of the semiconductor device of FIG. 1;

FIG. 11 is a fragmentary cross-sectional view of a semiconductor wafer during a manufacturing step of a semiconductor device according to another embodiment of the present invention;

12 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 11;

13 is an enlarged cross-sectional view of a main part of a semiconductor wafer during a manufacturing step of the semiconductor device of FIG. 12;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIGS. 12 and 13;

15 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 15;

[Explanation of symbols]

Reference Signs List 1 semiconductor wafer 1E epitaxial layer 2 p-type semiconductor region 2a p ⁺ -type semiconductor region 3 semiconductor region 3an ⁺ -type semiconductor region 3b n ⁺ -type semiconductor region 4 semiconductor region 4a n ^-- type semiconductor region 4b n ⁺ -type 5 gate insulating film 6 gate electrode 7 lead electrode 8 lead electrode 9a, 9b, 9c interlayer insulating film 10a to 10d connection hole 11 conductive film 11L, 11L1 to 11L8 wiring 12a, 12b resist film 13 protective film Reference Signs List 14 magnetic field microwave dry etching apparatus 15A loader cassette section 15B unloader cassette section 16 supply side vacuum chamber 17 dry etching processing chamber 18 transfer chamber 19 resist ashing chamber 20 discharge side vacuum chambers 21a to 21d shutters 22a, 22b cassette 23 open / close shutter 24 Table 25 Sin Arm 26 Table 27 AC power supply 28 Turbo pump 29 Rotary pump 30 Gas supply system 31 Solenoid coil 32 Magnetron 33 Swing arm 34 Control valve 35 Turbo pump 36 Rotary pump 37 Heater 38 Table 39 Control valve 40 Rotary pump 41 Gas supply system 42 Table 43 Opening / closing shutter 44 Dry etching apparatus 45 Transfer chamber 45A Transfer member 46 Loader / unloader chamber 47 Isotropic dry etching processing chamber 47A Lower electrode 47B Upper electrode 47C High frequency power supply 48 Anisotropic dry etching processing chamber 48A Lower electrode 48B Upper electrode 48C High frequency Power supply 49 Dry etching apparatus 49A Lower electrode 49B Upper electrode 49C Splitter 49D High frequency power supply 49E Processing chamber formation 50 p ⁺ -type semiconductor region 51a n ⁺ -type semiconductor region 52 p-type semiconductor region 53 a gate electrode 54 a gate insulating film 55 n ⁺ -type semiconductor region 56 n ⁺ -type semiconductor region 57 n-well 58 p ⁺ -type semiconductor Region 59 gate insulating film 60 gate electrode 61 n ⁺ type semiconductor region 62 n ⁺ type semiconductor region 63 p type semiconductor region 64 n type semiconductor region QL power MISFET QP pMIS QN nMIS QBL bipolar transistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yushi Hirokawa 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. No. 20-1 F-term in Hitachi Semiconductor Co., Ltd. Semiconductor Group 5F033 HH08 JJ01 KK01 KK04 PP15 QQ08 QQ11 QQ22 QQ35 XX03

Claims (6)

[Claims] (A) forming a conductive film for forming a wiring on a semiconductor substrate; (b) forming a mask film on the conductive film for forming a wiring; and (c) forming the (b) step. Thereafter, by using the mask film as an etching mask, performing a isotropic dry etching process on the conductive film for forming the wiring, thereby removing a halfway position of the conductive film for forming the wiring, (D) After the step (c), the remaining conductor film for forming a wiring is subjected to anisotropic dry etching using the mask film as an etching mask, so that the conductor film for forming the wiring is Removing the wiring to form a wiring. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the wiring-forming conductor film is at least half the thickness of the mask film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching end point time in the step (b) is determined by setting a target thickness of the conductor film for forming a wiring to be removed in the step (b). A method for manufacturing a semiconductor device, wherein the semiconductor device is obtained by dividing by a isotropic etching rate of a conductive film for use. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the isotropic and anisotropic dry etching is performed by a dry etching apparatus capable of independently controlling plasma and ion energy. A method of manufacturing a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the conductor film for forming the wiring is a simple conductor film of aluminum or an aluminum alloy or a barrier conductor film. A method for manufacturing a semiconductor device, wherein the semiconductor device is a laminated conductor film stacked on top. 6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a power field effect transistor on said semiconductor substrate.