JP2000298989A - Sram read-out circuit and sram read-out method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a SRAM read-out circuit and a SRAM read-out method in which a cell can be constituted with the minimum transistor size and high speed operation and high sensitivity of a sense amplifier can be realized. SOLUTION: This read-out circuit has such circuit constitution that potentials of digit lines Dj, Djb of four transistor cells are held at approximately a power source potential Vcc, an input potential of a sense amplifier is set to a sensitive first potential (=power source potential Vcc-threshold potential Vtp), and the digit lines Dj, Djp and an input (differential amplifier circuit input dj, Djp) of the sense amplifier are capacity-coupled by capacitances Cj, Cjb.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory reading technique, and more particularly, to an SR capable of forming a cell with a minimum transistor size and realizing high speed and high sensitivity of a sense amplifier.
The present invention relates to an AM read circuit and an SRAM read method.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram for explaining a first conventional SRAM reading circuit, and FIG. 11 is a circuit diagram for explaining a second conventional SRAM reading circuit. 10 or 11, V _GND is a ground potential, D _j and D _jb are digit lines, V _cc is a power supply potential, and Φ _s , Φ _sb , and Φ _ec are timing signals, respectively. In FIG. 10, _dj and _djb function as input / output lines of the differential amplifier circuit, and in FIG. 11, _dj and _djb function as output lines of the differential amplifier circuit. Conventionally, in an SRAM having a 6-transistor configuration (6Tr configuration), FIGS.
As shown in, there is no need to increase the digit lines _{D j,} the potential of the _{D jb} to the power supply potential _{V cc,} the power supply potential _{V c} c -V
_tn (V _tn is the threshold potential of the n-channel MOS transistor), and the digit lines D _j ,
Reading is performed by directly amplifying the potential difference of D _jb .

Further, as a prior art of a 6Tr cell SRAM comprising four transistors for memory and two transistors for resistance, for example, Japanese Patent Application Laid-Open No. 10-1
No. 62580 is disclosed. That is, the related art includes a main bit line pair and a plurality of memory blocks connected to the main bit line pair. Each of the memory blocks includes a local bit line pair and a static memory connected to the local bit line pair. , An amplifier for amplifying the potential difference between the pair of local bit lines, and a data transfer gate for transferring data between the pair of local bit lines and the pair of main bit lines. This describes an effect that a decrease in read speed due to an increase in capacity can be reduced and an operation region on a low voltage side can be widened. In such 6-transistor SRAM cell (different from the pseudo-SRAM), a digit line Dj, for Djb to share the power supply line of the cell (the potential Vcc), read, except write digit line _{D j,} the potential of the _{D jb} Power supply potential _Vcc
Must be kept.

[0004]

[SUMMARY OF THE INVENTION However, in such a SRAM cell, the digit line Dj, for Djb to share the power supply line of the cell (the potential Vcc), read, except write digit line _{D j,} the _{D jb} Since the potential needs to be kept at the power supply potential _Vcc , there is a problem that the potentials of the digit lines D _j and D _jb cannot be lowered for the amplifier circuit. Therefore, the SR of the 6Tr configuration
If the sense amplifier of the AM cell system is used as it is for the sense amplifier of the SRAM cell system of the 4Tr configuration, the digit lines D _j and D _jb are pulled up to the power supply potential V _cc before reading. _j , D
_Since any one of _jb decreases from the power supply potential _Vcc , the transistor of the sense amplifier becomes a dead zone until the first potential (= _Vcc − _Vtp ) ( _Vtp is the threshold potential of the p-channel MOS transistor). However, there is a problem that the sensitivity of the sense amplifier is lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide an SRAM read circuit which can form a cell with a minimum transistor size and can realize a high-speed and high-sensitivity sense amplifier. An object of the present invention is to provide an SRAM reading method.

[0006]

The gist of the present invention is to provide an SRAM read circuit capable of forming a cell with a minimum transistor size and realizing high speed and high sensitivity of a sense amplifier, comprising a digit line. And a four-transistor SRAM cell as a storage element unit connected to a word line, a sense amplifier for detecting the potential of the digit line of the four-transistor SRAM cell, and a potential of the digit line of the four-transistor SRAM cell during standby. Means for holding near the power supply potential and setting the input potential of the sense amplifier to the first potential with high sensitivity; capacitance for connecting the digit line and the input of the sense amplifier by capacitive coupling; At the time of reading, the potential of the word line is changed from the first potential to the second potential.
And a means for setting a potential. According to another aspect of the present invention, the sense amplifier input pair is temporarily short-circuited by a predetermined timing signal before cell selection and set to the same potential by a predetermined timing signal, and a predetermined potential difference occurs when reading the four-transistor cell. 2. The SRAM read circuit according to claim 1, further comprising means for activating said sense amplifier to amplify the potential of said sense amplifier input pair. According to a third aspect of the present invention, there is provided an SRAM readout circuit capable of forming a cell with a minimum transistor size and realizing a high-speed and high-sensitivity sense amplifier, comprising a memory connected to a digit line and a word line. A four-transistor SRAM cell as an element unit and the four-transistor SRA
A sense amplifier for detecting the potential of the digit line of the M cell; a standby transistor for holding the potential of the digit line of the four-transistor SRAM cell close to a power supply potential during standby and lowering the potential of the four-transistor SRAM cell by a threshold potential of a transistor from the power supply potential; Means for setting the input potential of the sense amplifier to one potential, capacitance for connecting the digit line and a differential amplifier circuit input constituting the input terminal of the sense amplifier by capacitive coupling, and reading the four-transistor cell. Means for changing the potential of the word line from the first potential to the second potential. According to another aspect of the present invention, a sense amplifier input pair is temporarily short-circuited by a predetermined timing signal before cell selection and set to the same potential by a predetermined timing signal, and a predetermined potential difference occurs when reading the four-transistor cell. 4. The device according to claim 3, further comprising means for activating said differential amplifier circuit to amplify the potential of said digit line.
It exists in the RAM read circuit. According to a fifth aspect of the present invention, there is provided a four-transistor SRAM cell which is a storage element unit connected to a digit line and a word line, and a sense amplifier for detecting a potential of the digit line of the four-transistor SRAM cell. Can be configured with a minimum transistor size for an SRAM read circuit provided with
An M read method, wherein the potential of the digit line of the four-transistor SRAM cell is kept close to a power supply potential when the four-transistor cell is on standby, and the input potential of the sense amplifier is set to a first potential with high sensitivity. A step of connecting the digit line and the input of the sense amplifier by capacitive coupling, and a step of changing the potential of the word line from the first potential to the second potential when reading the four-transistor cell. SR characterized by
It is in the AM reading method. The gist of claim 6 of the present invention is that the sense amplifier input pair is temporarily short-circuited by a predetermined timing signal before cell selection and set to the same potential, and a predetermined potential difference occurs when reading the four-transistor cell. 6. The SRAM reading method according to claim 5, further comprising a step of activating said sense amplifier to amplify the potential of said sense amplifier input pair. The gist of the present invention is that a four-transistor SRAM cell, which is a storage element unit connected to a digit line and a word line, and the four-transistor SRAM cell
In contrast to an SRAM readout circuit having a sense amplifier for detecting the potential of the digit line of a cell, a cell can be configured with a minimum transistor size, and the sense amplifier can operate at high speed.
An SRAM reading method capable of realizing high sensitivity,
During standby of the four-transistor cell, the potential of the digit line of the four-transistor SRAM cell is held close to the power supply potential, and the input potential of the sense amplifier is lowered from the power supply potential to a first potential lower by the threshold potential of the transistor. Setting, connecting the digit line and a differential amplifier circuit input constituting the input terminal of the sense amplifier by capacitive coupling, and setting the potential of the word line to the first potential when reading the four-transistor cell. From the second
And a step of setting a potential. According to another aspect of the present invention, the sense amplifier input pair is temporarily short-circuited with a predetermined timing signal before cell selection and set to the same potential, and a predetermined potential difference occurs when reading the four-transistor cell. 8. The method according to claim 7, further comprising the step of activating said differential amplifier circuit to amplify the potential of said digit line.
In the SRAM reading method described above.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION
The first characteristic of the M read circuit is that the four-transistor SR
The potential of the digit line of the AM cell (4TrSRAM cell) is held close to the power supply potential, the input potential of the sense amplifier is set to the first potential (= power supply potential−threshold potential) with high sensitivity, and the digit line and the sense amplifier are set. Second, a cell can be formed with a minimum transistor size by a circuit configuration in which the input (differential amplifier circuit input) is capacitively coupled by a capacitance, and by changing the word potential from the first potential to the second potential at the time of reading. Before a cell is selected, the sense amplifier input pair is temporarily short-circuited to the same potential by a predetermined timing signal, and when a certain potential difference occurs when reading out the 4Tr SRAM cell, the differential amplifier circuit is activated to set the potential of the sense amplifier input pair. Is to increase the speed of the sense amplifier to increase the speed and sensitivity.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
SRAM reading circuit according to the embodiment will be described.
FIG. SRAM reading of this embodiment
The circuit, as shown in FIG._jAnd digit
Line D_jbAnd the word line W_i4TrS connected to
For the RAM cell 20, the differential amplifier circuit input d_jAnd differential
Amplifier circuit input d_jbSense amplifier 10 connected between
(P channel MOS transistor Q₁₀₁, N channel
MOS transistor Q₁₀₂, P-channel MOS transistor
Jista Q_{10 3}, N-channel MOS transistor Q
₁₀₄, N-channel MOS transistor Q ₁₀₅, And
And p-channel MOS transistor Q₁₁₂)
Jit line D _jAnd differential amplifier circuit input d_jCapacitor between
C_jCapacitance coupling with digit line D_jbAnd differential amplification times
Road input d_jbBetween the capacitance C_jbWith capacitive coupling
Digit line D_jAnd digit line D_jbSensea during
In this configuration, the amplifier 10 is connected. Sense amplifier 1
0 indicates two CMOS (complementary metal oxide semiconductor)
Barter (p-channel MOS transistor Q₁₀₁And n
Channel MOS transistor Q₁₀₂CM composed of
OS inverter and p-channel MOS transistor Q
₁₀₃And n-channel MOS transistor Q₁₀₄Composed with
Input and output of a CMOS inverter)
The circuit configuration of the differential amplifier circuit and the gate terminal
No.Φ_ecP-channel MOS transistor Q to which
₁₁₂, CMOS inverter and ground potential V_GNDBetween
N-channel MOS transistor as a provided constant current source
TA Q₁₀₅And the ground potential V_GNDThe timing signal
No.Φ _s-Channel MOS transistor Q controlled by
₁₀₅Through the ground potential V_{GN D}Connected to two CMs
OS inverter (p-channel MOS transistor Q_10
1And n-channel MOS transistor Q₁₀₂And composed of
CMOS inverter and p-channel MOS transistor
Jista Q₁₀₃And n-channel MOS transistor Q
₁₀₄Input contact of CMOS inverter)
(Differential amplifier circuit input d)_j, D
_jbIs the digit line D_j, Digit line D_jbTo each
Capacitance C_j, C_jbConnected through. difference
Dynamic amplifier circuit input d_j, D_jbIs the input end and
It is also a force end.

FIG. 2 is a circuit diagram for explaining a 4Tr SRAM cell 20 and a digit line charging circuit 22 for digit lines D _j and D _jb . Word line W _i , digit lines D _j , D
4TrSRAM cell 20 of Figure 1 connected to _jb, as shown in FIG. 2, the digit lines _{D j} - n-channel MOS transistor _{Q 110} connected between the ground potential _{V GND,}
N connected between digit line D _jb and ground potential V _GND
Channel MOS transistor _{Q 111,} n-channel logic value of the word line _{W i} MOS transistor _{Q 11} 0, Q
₁₁₁ has become connected to each other in the two p-type selection transistor for transferring (p-channel MOS transistor _{Q 108, Q 109)} to.

On the other hand, the digit lines _{D j,} the digit line charge circuit 22 of the _{D jb} is the digit lines _{D j,} 2 single charging transistor (p between each and the power supply potential _{V cc} of _{D jb}
The channel MOS transistors Q ₁₀₆ and Q ₁₀₇ ) are connected, and the charge control signal _Vp is input to the respective gate terminals of the two charge transistors (p-channel MOS transistors Q ₁₀₆ and Q ₁₀₇ ).

Next, the operation of the SRAM read circuit of FIG.
Will be described with reference to FIG. FIG. 3 shows the first or second fruit.
In order to explain the operation of the SRAM read circuit of the embodiment
6 is a timing chart of FIG. First, the word line W_i(Figure
W shown in 3_iIs selected, the first potential (= V
_cc-V_tp) (V shown in FIG. 3)_cc-V_tpSee)
Source potential V_cc(V shown in FIG. 3_ccSee)) to word potential
V_b(Also, the ground potential V_{G ND}), 4TrS
When the RAM cell 20 is selected, a p-type selection transistor
(P channel MOS transistor Q₁₀₈, Q₁₀₉)
Are going from low resistance to high resistance (4TrSRA in FIG. 2).
(See M cell 20). At this time, in the 4Tr SRAM cell 20
Part of two n-channel MOS transistors Q₁₁₀, Q
₁₁₁Transitions to the conducting state and goes low.
The n-channel MOS transistor at the low level
Star Q₁₁₀(Or Q₁₁₁Selection of p type that selected)
Transistor (p-channel MOS transistor Q₁₀₉
(Or Q₁₀₈)) Through which current flows,
Digit line D_j(Or digit line D_jb) (Shown in FIG. 3)
D_j/ D_jb) Drops. 4TrSRA
Two n-channel MOS transistors inside M cell 20
Q₁₁₀, Q₁₁₁The other Q₁₁₁(Or Q ₁₁₀)
Is non-conducting, so digit line D_jb(Or digit line
D_j) Is the power supply potential V_ccLevel.

Digit line D_jIs the differential amplifier input d_jTo
Digit line D with capacitive coupling_jbIs the differential amplifier input d
_jbDigit line D because it is capacitively coupled to_j(Also
Is digit line D_jb), The differential amplification circuit
Road input d_jOf the differential amplifier circuit input d_jbSame potential as
So that the timing signal Φ_ec(Φ shown in FIG. 3_ec
P) in the sense amplifier 10 controlled by
MOS transistor Q ₁₀₁(Or Q₁₀₃) Is non
The state transits to the conductive state, and the differential amplifier circuit input d_j(Or differential
Amplifier circuit input d_jb(Of the first embodiment shown in FIG. 3)
d_j/ D_jb) Also decreases.

The differential amplifier circuit input d_j(Or differential amplification times
Road input d_jb1), the first potential shown in FIG.
Sense amplifier 10 of SRAM read circuit of embodiment
Then, the differential amplifier circuit input d_jbSide (or differential amplifier circuit
Input d_jSide), the power supply potential V _ccPulled up to
p channel MOS transistor Q₁₀₃(Q₁₀₁)But
The state transits to the conductive state, and the differential amplifier circuit input d_j(Or difference
Dynamic amplifier circuit input d_jb) Is the first potential (= V_cc−
V_tp) To the power supply potential V_ccGoing up.

Thereafter, when the potential difference between the inputs d _j and d _jb of the differential amplifier circuit is secured to some extent, the timing signal Φ _s
The sense amplifier 10 by ([Phi see _s shown in FIG. 3) is activated, the potential of the differential amplifier input d _{j (or} differential amplifier circuit input d _jb) is rapidly amplified to the ground potential V _GND, simultaneously potential of the differential amplifier circuit inputs _{d jb} (or differential amplifier circuit input _{d j)} is rapidly amplified to the power source potential _{V cc.}

Thereafter, the word line _Wi is set to the first potential (= V
_cc -V _tp) returns to the charge control signal _{V p} of the potential low-level (digit line to the ground potential _{V GND)} charging circuit 2
The digit line D _j (or digit line D _jb ) also transitions to the power supply potential V _cc by causing the digit lines D _j and D _jb to rapidly charge by causing 2 to transition to the conductive state.

After the output of the sense amplifier 10 is latched by a data latch circuit or the like, the timing signal Φ
_ec , the timing signal Φ _s returns to the initial state.

At this time, when the potential of the differential amplifier input _dj (or the differential amplifier input _djb ) transitions from the ground potential V _GND to the first potential (= _Vcc - _Vtp ), as shown in FIG. Since the potential of the sense amplifier 10 of the first embodiment rises to half of the power supply potential _Vcc , the digit line D
_j (or digit line D _jb ) slightly rises (about 0.2-0.3 V) from power supply potential _Vcc . As a result, the resistances of the p-channel MOS transistors Q ₁₀₈ and Q ₁₀₉ of the 4Tr SRAM cell 20 connected to the digit line D _j (or the digit line D _jb ) become lower by about one digit, and the digit line D _j (or the digit line D _j ). During the period in which the potential of _jb ) is lower than the power supply potential _Vcc, it is possible to replenish the charge of the 4TrSRAM cell 20 that has stopped being charged a little.

FIG. 4 shows an SR according to each embodiment of the present invention.
FIG. 2 is a configuration diagram of a memory device using an AM read circuit.
The memory device of the present embodiment has a digit line charging circuit 2
2. X decoder 30, write signal generation circuit 40, timing signal generation circuit 50, write circuit 60, predetermined number of sense amplifiers 10, and predetermined number of 4Tr SRAM cells 2.
0 is provided. In the figure, WE is a write enable _{signal, D in} writing data, ATD, CE is a chip enable _{signal, W i,} W i _{+ 1} word _{lines, A} 0,
/ A ₀ ,..., / A _m indicate address signals. Further illustrating the circuit of the X-decoder 30 including a voltage control circuit of the word line W _i in Figure 5. FIG. 6 shows an example of the capacitance of the depletion transistor.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
FIG. 3 is a circuit diagram for explaining an SRAM read circuit according to the first embodiment. The same portions as those already described in the first embodiment are denoted by the same reference numerals, and duplicate description will be omitted. SRA of the present embodiment
The M read circuit includes a p-channel MOS on the power supply potential _Vcc side in addition to the SRAM read circuit of the first embodiment.
The transistor Q ₂₀₁ can be controlled by the timing signal Φ _{s b} and the differential amplifier circuit inputs d _j and d
_jb potential can be made close to the highest potential of the amplification degree, that is, the impedance of the differential amplification circuit inputs _dj and _djb is high during standby.
High resistance of the transistor between such that the impedance to the power supply potential V _cc and ground potential V _GND (p-channel M
OS transistors Q ₂₀₂ , Q ₂₀₅ and n-channel MOS transistors Q ₂₀₃ , Q ₂₀₆ ) are provided, and の of the power supply potential _Vcc (= V
_cc / 2) high-resistance transistor (p-channel M
The feature is that the input contacts of the OS transistors Q ₂₀₂ and Q ₂₀₅ and the n-channel MOS transistors Q ₂₀₃ and Q ₂₀₆ ) are maintained. In the present embodiment, p-channel MOS transistors Q forming two CMOS inverters in sense amplifier 10 are provided.
_101, a _{Q 103} to ON / OFF depending on the logic value of the timing signal [Phi _{e c} p-channel MOS transistor Q
₂₀₄ , a p-channel MOS transistor Q ₂₀₇ for turning on / off the n-channel MOS transistors Q ₁₀₂ and Q ₁₀₄ constituting the two CMOS inverters in accordance with the logic value of the timing signal _Φecb .

Next, the operation of the SRAM read circuit of FIG.
Will be described with reference to FIG. FIG. 3 shows the first or second fruit.
In order to explain the operation of the SRAM read circuit of the embodiment
6 is a timing chart of FIG. First, the word line W_i(Figure
W shown in 3_iIs selected, the first potential (= V
_cc-V_tp) (V shown in FIG. 3)_cc-V_tpSee)
Source potential V_cc(V shown in FIG. 3_ccSee)) to word potential
V_b(Also, the ground potential V_{G ND}), 4TrS
When the RAM cell 20 is selected, a p-type selection transistor
(P channel MOS transistor Q₁₀₈, Q₁₀₉)
Are going from low resistance to high resistance (4TrSRA in FIG. 2).
(See M cell 20). At this time, in the 4Tr SRAM cell 20
Part of two n-channel MOS transistors Q₁₁₀, Q
₁₁₁Transitions to the conducting state and goes low.
The n-channel MOS transistor at the low level
Star Q₁₁₀(Or Q₁₁₁Selection of p type that selected)
Transistor (p-channel MOS transistor Q₁₀₉
(Or Q₁₀₈)) Through which current flows,
Digit line D_j(Or digit line D_jb) (Shown in FIG. 3)
D_j/ D_jb) Drops. 4TrSRA
Two n-channel MOS transistors inside M cell 20
Q₁₁₀, Q₁₁₁The other Q₁₁₁(Or Q ₁₁₀)
Is non-conducting, so digit line D_jb(Or digit line
D_j) Is the power supply potential V_ccLevel.

Thereafter, the digit line D_jIs the differential amplifier circuit input
Force d_jDigit line D capacitively coupled to _jbIs a differential amplifier circuit
Input d_jbDigit line D because it is capacitively coupled to_j
(Or digit line D_jb) When the potential drops, the differential
Amplifier circuit input d_jOf the differential amplifier circuit input d_jbSame as
Timing signal Φ_ecb(Shown in FIG. 3
Φ_ecbIn the sense amplifier 10 controlled by
P-channel MOS transistor Q₁₀₁(Or Q
₁₀₃) Changes to the non-conductive state, and the differential amplifier circuit input d_j
(Or differential amplifier circuit input d_jb(The second one shown in FIG. 3)
D of the embodiment_j/ D_jb) Also decreases.

Thereafter, the differential amplifier circuit input d_j(Or difference
Dynamic amplifier circuit input d_jbFIG. 7 shows that the potential of
The sense amplifier of the SRAM read circuit according to the second embodiment
In the amplifier 10, a high-resistance transistor (p-channel MO
S transistor Q₂₀₂, Q ₂₀₅And n channel M
OS transistor Q₂₀₃, Q₂₀₆Power by
Rank V_ccOf the potential (= V_cc/ 2) Closely held
Input d of the differential amplifier circuit_j(Or with differential amplifier circuit
Force d_jb) Is the power supply potential V_ccOf the potential (= V
_cc/ 2) It decreases from a nearby potential.

Thereafter, when the potential difference between the inputs d _j and d _jb of the differential amplifier circuit is secured to some extent, the timing signal Φ
_sb (refer to Φ _sb shown in FIG. 3) to sense amplifier 1
0 is activated, the potential of the differential amplifier circuit input d _j (or the differential amplifier circuit input d _jb ) is rapidly amplified to the ground potential V _GND , and at the same time, the differential amplifier circuit input d _jb (or the differential amplifier circuit input d _jb ). The potential of the circuit input _dj ) is rapidly amplified to the power supply potential _Vcc .

Thereafter, the word line _Wi is set to the first potential (= V
_cc -V _tp) returns to the charge control signal _{V p} of the potential low-level (digit line to the ground potential _{V GND)} charging circuit 2
The digit line D _j (or digit line D _jb ) also transitions to the power supply potential V _cc by causing the digit lines D _j and D _jb to rapidly charge by causing 2 to transition to the conductive state.

Then, after the output of the sense amplifier 10 is further latched by a data latch circuit or the like, the timing signals Φ _ecb and Φ _sb return to the initial state.

At this time, when the potential of the differential amplifier circuit input _dj (or the differential amplifier circuit input _djb ) transitions from the ground potential _VGND to the first potential (= _Vcc - _Vtp ), as shown in FIG. Since the potential of the sense amplifier 10 of the second embodiment rises to half of the power supply potential _Vcc , the digit line D
_j (or digit line D _jb ) slightly rises (about 0.2-0.3 V) from power supply potential _Vcc . As a result, the resistances of the p-channel MOS transistors Q ₁₀₈ and Q ₁₀₉ of the 4Tr SRAM cell 20 connected to the digit line D _j (or the digit line D _jb ) become lower by about one digit, and the digit line D _j (or the digit line D _j ). During the period in which the potential of _jb ) is lower than the power supply potential _Vcc, it is possible to replenish the charge of the 4TrSRAM cell 20 that has stopped being charged a little.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
SRAM reading circuit according to the embodiment will be described.
FIG. In addition, in the first and second embodiments,
Are the same as those already described in
The reference numerals are used, and the repeated description is omitted. Of this embodiment
The SRAM read circuit is the SRAM read circuit of the second embodiment.
A high-resistance transistor (p-channel M
OS transistor Q₂₀₂, Q₂₀₅And n-channel
MOS transistor Q₂₀₃, Q₂₀₆) Circuit
And the timing signal Φ_s, Timing signal
Φ_sb, The timing signal Φ_ecAnd the timing signal Φ
_ecbIn data latch mode even during standby.
The chip is activated and the address signal changes.
Timing signal Φ_sAnd the timing signal Φ_sb
At power supply potential V_ccAnd ground potential V_GNDFrom two C
MOS inverter (p-channel MOS transistor Q
₁₀₁And n-channel MOS transistor Q₁₀₂Composed with
CMOS inverter and p-channel MOS transistor formed
Transistor Q₁₀₃And n-channel MOS transistor Q
₁₀₄CMOS inverter composed of
And the timing signal Φ_ecAnd the timing signal Φ_e
cbAnd the differential amplifier input d_j, D_jbConnected to the same potential
The power supply potential V _ccCan be reduced to half of
Circuit configuration.

Next, the operation of the SRAM read circuit of FIG. 8 will be described with reference to FIG. FIG. 9 is a timing chart for explaining the operation of the SRAM read circuit according to the third embodiment. The sense amplifier 10 according to the third embodiment shown in FIG. 8 includes the high-resistance transistors (p-channel MOS transistors Q ₂₀₂ and Q _{2) according to} the second embodiment.
₀₅ and n-channel MOS transistors Q ₂₀₃ , Q
₂₀₆ ) is removed so that the differential amplifier circuit inputs _dj and _djb can be held at half the power supply potential _Vcc (= _Vcc / 2) in the standby mode. Thereby, a high-resistance transistor (p-channel M
The current flowing through the OS transistors Q ₂₀₂ and Q ₂₀₅ and the n-channel MOS transistors Q ₂₀₃ and Q ₂₀₆ during the standby mode can be eliminated.

[0029] However, as shown in FIG. 9, the timing signal [Phi _s, timing signal [Phi _sb, timing signal [Phi _ec, the sense amplifier 10 to operate the sense amplifier 10 during standby using the timing signal [Phi _ecb
Is used as a data latch circuit, and before reading the 4Tr SRAM cell 20, the sense amplifier 10 is temporarily deactivated to input the differential amplifier circuit inputs _dj and _djb (the third embodiment shown in FIG. 9). _dj / _djb ) is set to a half of the power supply potential _Vcc (= _Vcc / 2). Subsequent operations are the same as those already described in the first and second embodiments. Therefore, the same portions are denoted by the same reference numerals, and redundant description will be omitted.

(Fourth Embodiment) The p-type and n-type of the 4Tr SRAM cell 20 and all peripheral circuits shown in the first to third embodiments are inverted, and the power supply potential _{Vcc is set.}
To the ground potential V _GND and the ground potential V _GND to the power supply potential V
Even if it is replaced with _cc , the same operation and effect are exhibited.

As described above, according to each of the above embodiments, the following effects can be obtained. First, the first effect is
That is, high speed and high sensitivity of the sense amplifier 10 can be realized. The second effect is that current consumption can be reduced. A third effect is that a circuit can be configured with a minimum transistor size. And the fourth effect is 4
That is, the cell size of the TrSRAM cell 20 can be minimized.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0033]

Since the present invention is configured as described above, the following effects can be obtained. First, the first effect is that high speed and high sensitivity of the sense amplifier can be realized.
The second effect is that current consumption can be reduced.
A third effect is that a circuit can be configured with a minimum transistor size. A fourth effect is that the cell size of a 4-transistor SRAM cell can be minimized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining an SRAM read circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a 4Tr SRAM cell and a digit line charging circuit of a digit line of FIG. 1;

FIG. 3 is a timing chart for explaining an operation of the SRAM read circuit according to the first or second embodiment;

FIG. 4 is a configuration diagram of a memory device using an SRAM read circuit according to each embodiment of the present invention.

FIG. 5 is a circuit example of an X decoder.

FIG. 6 is an example of capacitance by a depletion transistor.

FIG. 7 is a circuit diagram illustrating an SRAM read circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram for explaining an SRAM read circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the SRAM read circuit according to the third embodiment;

FIG. 10 is a circuit diagram illustrating an SRAM read circuit according to a first related art.

FIG. 11 is a circuit diagram illustrating an SRAM read circuit according to a second related art.

[Reference Numerals] 10 ... a sense amplifier 20 ... 4TrSRAM cell 22 ... digit line charge circuit 30 ... X-decoder 40 ... write signal generating circuit 50 ... timing signal generation circuit 60 ... write circuit C _j, C _{jb ...} capacitance d _j, d _{jb ...} differential amplifier circuit inputs V _{GND ...} ground potential D _j, D _{jb ...} digit line V b _... wordline potential V _{cc ...} power source potential V _cc -V _{tp ...} first potential V p _... charging control signal W i _... wordline Φ _s , Φ _sb , Φ _ec , Φ _ecb ... timing signal

Claims (8)

[Claims] 1. An SRA capable of forming a cell with a minimum transistor size and realizing high speed and high sensitivity of a sense amplifier.
An M read circuit, comprising: a four-transistor SRAM cell as a storage element unit connected to a digit line and a word line; a sense amplifier for detecting a potential of the digit line of the four-transistor SRAM cell; While keeping the potential of the digit line of the SRAM cell close to the power supply potential,
Means for setting the input potential of the sense amplifier to a first potential with high sensitivity; capacitance for connecting the digit line and the input of the sense amplifier by capacitive coupling; and potential of the word line when reading the four-transistor cell. Means for changing the potential from the first potential to the second potential. 2. A sense amplifier input pair is temporarily short-circuited before a cell is selected by a predetermined timing signal and set to the same potential, and the sense amplifier is activated when a predetermined potential difference occurs when reading the four-transistor cell. 2. The SRAM read circuit according to claim 1, further comprising means for amplifying the potential of said sense amplifier input pair. 3. An SRA capable of forming a cell with a minimum transistor size and realizing high speed and high sensitivity of a sense amplifier.
An M read circuit, comprising: a four-transistor SRAM cell as a storage element unit connected to a digit line and a word line; a sense amplifier for detecting a potential of the digit line of the four-transistor SRAM cell; While keeping the potential of the digit line of the SRAM cell close to the power supply potential,
Means for setting the input potential of the sense amplifier to a first potential lower than the power supply potential by a threshold potential of a transistor; and capacitive coupling between the digit line and a differential amplifier circuit input constituting an input terminal of the sense amplifier. And a means for changing the potential of the word line from the first potential to the second potential when reading the four-transistor cell. 4. A sense amplifier input pair is temporarily short-circuited by a predetermined timing signal before cell selection and set to the same potential, and when a predetermined potential difference occurs at the time of reading the four-transistor cell, the differential amplifier circuit is activated. 4. The SRAM read circuit according to claim 3, further comprising means for activating and amplifying the potential of the digit line. 5. An SRAM read circuit comprising: a four-transistor SRAM cell as a storage element unit connected to a digit line and a word line; and a sense amplifier for detecting a potential of the digit line of the four-transistor SRAM cell. , An SRA capable of forming a cell with a minimum transistor size and realizing high speed and high sensitivity of the sense amplifier
M readout method, wherein the potential of the digit line of the four-transistor SRAM cell is kept close to a power supply potential when the four-transistor cell is on standby, and the input potential of the sense amplifier is set to a first potential with high sensitivity. Connecting the digit line and the input of the sense amplifier by capacitive coupling; and changing the potential of the word line from the first potential to the second potential when reading the four-transistor cell. An SRAM reading method characterized by the above-mentioned. 6. A sense amplifier input pair is temporarily short-circuited by a predetermined timing signal before cell selection and set to the same potential, and the sense amplifier is activated when a predetermined potential difference occurs during reading of the four-transistor cell. 6. The SRAM read method according to claim 5, further comprising the step of: amplifying the potential of the input pair of the sense amplifier. 7. An SRAM read circuit comprising a four-transistor SRAM cell as a storage element unit connected to a digit line and a word line, and a sense amplifier for detecting a potential of the digit line of the four-transistor SRAM cell. , An SRA capable of forming a cell with a minimum transistor size and realizing high speed and high sensitivity of the sense amplifier
An M read method, wherein the potential of the digit line of the four-transistor SRAM cell is kept close to a power supply potential during standby of the four-transistor cell, and the first potential is lowered from the power supply potential by a threshold potential of the transistor. Setting the input potential of the sense amplifier; connecting the digit line and a differential amplifier circuit input constituting the input terminal of the sense amplifier by capacitive coupling; and setting the word line when reading the four-transistor cell. Changing the potential of the SRAM from the first potential to the second potential. 8. A sense amplifier input pair is temporarily short-circuited by a predetermined timing signal before cell selection and set to the same potential, and the differential amplifier circuit is activated when a predetermined potential difference occurs when reading the four-transistor cell. 8. The SRAM reading method according to claim 7, further comprising a step of activating and amplifying the potential of the digit line.