JP2000298451A5 - - Google Patents

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JP2000298451A5
JP2000298451A5 JP1999106439A JP10643999A JP2000298451A5 JP 2000298451 A5 JP2000298451 A5 JP 2000298451A5 JP 1999106439 A JP1999106439 A JP 1999106439A JP 10643999 A JP10643999 A JP 10643999A JP 2000298451 A5 JP2000298451 A5 JP 2000298451A5
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discharge
electrodes
electrode
row
mother
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次に、「アドレス期間」では、マトリックスの選択により表示すべき放電セルのみを選択的に放電させて、その放電セルに「アドレス放電」を形成する。具体的には、図13に示すように、まず、行電極Xiに順次にスキャンパルスVxgを印加していき、点灯すべき放電セルにおいては列電極Wjに画像データに基づく電圧パルスVwDを印加することによって、列電極Wjと行電極Xiとの間で「書き込み放電」を発生させる。なお、アドレス期間中、行電極Yには副走査パルスVyscを印加する。このとき、行電極Xiと行電極Yiとの間には電位差(Vxg+Vysc)が印加される。この電位差(Vxg+Vysc)は、それ自身では放電を開始しないが、先の書き込み放電をトリガにして直ちに行電極Xi,Yi間に「書込み維持放電」を発生しうる(転移しうる)電位差である。かかるアドレス放電によって、既述のように、当該放電セルの誘電体層106A(図10参照)の表面上に、後の維持パルスVsの印加のみで維持放電を行うことが可能な量の正又は負の壁電荷が蓄積する。 Next, in the "address period", only the discharge cells to be displayed are selectively discharged by selecting the matrix, and the "address discharge" is formed in the discharge cells. Specifically, as shown in FIG. 13, first, the scan pulse Vxg is sequentially applied to the row electrode Xi, and in the discharge cell to be lit, the voltage pulse VwD based on the image data is applied to the column electrode Wj. As a result, a "write discharge" is generated between the column electrode Wj and the row electrode Xi. During the address period, a sub-scanning pulse Vysc is applied to the row electrode Y. At this time, a potential difference (Vxg + Vysc) is applied between the row electrode Xi and the row electrode Yi. This potential difference (Vxg + Vysc) is a potential difference that does not start discharge by itself, but can immediately generate (transfer) “write maintenance discharge” between the row electrodes Xi and Yi triggered by the previous write discharge. By such address discharge, as described above, a positive or positive amount capable of performing maintenance discharge only by applying the subsequent maintenance pulse Vs on the surface of the dielectric layer 106A (see FIG. 10) of the discharge cell. Negative wall charges accumulate.

電極Xi,Wj間の書込み放電に引き続いて、当該書込み放電をトリガとして行電極Xiと左側用行電極YLiとの間に「書込み維持放電」が発生する。かかる書込み放電から書込み維持放電への転移も電極対Xi,YLi間の電位差に依存する。左側用行電極YLiに印加されている副走査パルスVay1=60Vのとき、電極対Xi,YLi間の電位差は240V(=60V−(−180V))であるため、上記放電の転移を十分に生じさせることができる。これに対して、右側用行電極YRiは接地電位であため、電位差180Vが印加されている電極対Xi,YRi間では上記放電の転移は起こらない。 Following the write discharge between the electrodes Xi and Wj, a “write maintenance discharge” is generated between the row electrode Xi and the left row electrode YLi triggered by the write discharge. The transition from the write discharge to the write maintenance discharge also depends on the potential difference between the electrode pair Xi and YLi. When the sub-scanning pulse Bay1 = 60V applied to the left row electrode YLi, the potential difference between the electrode and Xi and YLi is 240V (= 60V- (-180V)), so that the above discharge transition is sufficiently generated. Can be made to. In contrast, since the right-side row electrodes YRi Ru der ground potential, the electrode pairs Xi potential difference 180V is applied, is between YRi not occur transition of the discharge.

なお、行電極X1〜Xn用の駆動回路16,17を1カ所に、例えばAC−PDP61の左側に配置しても良い。但し、行電極X1〜Xnの駆動回路16,17を一カ所に、例えばAC−PDP61の左側に集中して配置すると、AC−PDP61の左側の設置スペースの実装密度が高くなってしまう。このため、図1に示すように、プラズマディスプレイ装置60では、行電極X1〜Xn用の駆動回路を分割した上で、それぞれをAC−PDP61の左右に配置している。 The drive circuits 16 and 17 for the row electrodes X1 to Xn may be arranged at one place, for example, on the left side of the AC-PDP61. However, if the drive circuits 16 and 17 of the row electrodes X1 to Xn are arranged in one place, for example, concentrated on the left side of the AC-PDP61, the mounting density of the installation space on the left side of the AC-PDP61 becomes high. Therefore, as shown in FIG. 1, in the plasma display device 60, the drive circuits for the row electrodes X1 to Xn are divided and arranged on the left and right sides of the AC-PDP61.

詳細には、AC−PDP101と同様に、背面ガラス基板103の放電空間111側の表面上に列電極W1〜Wm(図10中の列電極108に相当)が、当該表面に平行な第1方向D1に沿って延在しつつ、第1方向D1と当該表面内で直交する第2方向D2において等ピッチで配置されている。ここで、第1及び第2方向D1,D2はそれぞれAC−PDP71の表示画面における縦方向及び方向とする。また、隔壁10は、図10中の隔壁110と同様に、第1方向D1に沿ってストライプ状に配置されている。そして、背面ガラス基板103の上記表面及び隣接する隔壁10の対面する両側壁面で以て規定されるU字型溝には、当該U字型溝単位で、各発光色用の蛍光体層109R,109G,109Bのいずれかの蛍光体層が配置されている。なお、列電極W1〜Wmを覆うように背面ガラス基板103の上記表面上に誘電体層を設けて、当該誘電体層上に隔壁10及び蛍光体層109が配置しても良い。 Specifically, similarly to the AC-PDP 101, the row electrodes W1 to Wm (corresponding to the row electrodes 108 in FIG. 10) are placed on the surface of the back glass substrate 103 on the discharge space 111 side in the first direction parallel to the surface. It extends along D1 and is arranged at equal pitches in the second direction D2, which is orthogonal to the first direction D1 in the surface. Here, the first and second directions D1 and D2 are the vertical direction and the horizontal direction on the display screen of the AC-PDP71, respectively. Further, the partition walls 10 are arranged in a stripe shape along the first direction D1 like the partition walls 110 in FIG. Then, in the U-shaped groove defined by the surface of the back glass substrate 103 and the opposite side wall surfaces of the adjacent partition walls 10, the phosphor layer 109R for each emission color is formed in the U-shaped groove unit. The phosphor layer of any of 109G and 109B is arranged. A dielectric layer may be provided on the surface of the back glass substrate 103 so as to cover the column electrodes W1 to Wm, and the partition wall 10 and the phosphor layer 109 may be arranged on the dielectric layer.

他方、前面ガラス基板102において、行電極Xi,Yiは、当該基板102の放電空間111側の表面上に第2方向D2に沿って延びる帯状の母電極Xbi,Ybiと、それぞれの一端が母電極Xbi,Ybiの所定の位置(後述する)に接続されたm個の例えば四角形の透明電極Xt,Yt(特に必要な場合には「透明電極Xti,Yti」のように添え字iを付して、母電極Xbi,Ybiとの帰属関係を明らかにする)とから成る。このとき、それぞれn本の母電極Xb1〜Xbn,Yb1〜Ybnは互いに平行に且つ第1方向D1に関して等ピッチで交互に配置されている。母電極Xbi,Ybiは、透明電極Xt,Ytよりもインピーダンスが低いことが望ましい。なお、図4及び図5では、透明電極Xt,Ytが前面ガラス基板102の放電空間側の表面上に配置され、当該透明電極Xti,Ytiの端部を覆うように母電極Xbi,Ybiが上記表面上に配置された構造を図示しているが、両電極の積層順序が逆の構造であっても構わない。 On the other hand, in the front glass substrate 102, the row electrodes Xi and Yi are strip-shaped mother electrodes Xbi and Ybi extending along the second direction D2 on the surface of the substrate 102 on the discharge space 111 side, and one end of each is a mother electrode. M pieces of, for example, quadrangular transparent electrodes Xt and Yt connected to predetermined positions (described later) of Xbi and Ybi (if necessary, a subscript i such as "transparent electrodes Xti and Yti" are added. , Clarify the attribution relationship with the mother electrodes Xbi and Ybi). At this time, the n mother electrodes Xb1 to Xbn and Yb1 to Ybn are arranged in parallel with each other and alternately at equal pitches in the first direction D1. It is desirable that the mother electrodes Xbi and Ybi have lower impedances than the transparent electrodes Xt and Yt. In FIGS. 4 and 5, the transparent electrodes Xt and Yt are arranged on the surface of the front glass substrate 102 on the discharge space side, and the mother electrodes Xbi and Ybi cover the ends of the transparent electrodes Xti and Yti. Although the structure arranged on the surface is shown, the stacking order of both electrodes may be reversed.

透明電極Xtiのそれぞれは、その一端が母電極Xbiに接続されると共に、当該母電極Xbiを挟んで第1方向D1に隣接する2つの単位領域ARの内の一方の領域内に張り出している。しかも、当該m個の透明電極Xtのそれぞれは第1方向D1に対して互い違いの方向に張り出して形成されている。即ち、隣接する透明電極Xtは同一へは側の張り出すことなく形成されている。同様に、透明電極Ytiを成すm個の透明電極Ytのそれぞれは、その一端が母電極Ybiに接続されると共に、その張り出し方向が第1方向D1に対して互い違いになるように単位領域AR内に張り出した形状を有する。特に、図5に示すように、透明電極Xt及び透明電極Ytの各張り出した側のエッジは同一の単位領域AR内において所定の間隙(後述のように、放電ギャップに該当)DGを介して互いに対峙している。なお、対峙する透明電極Xt,Yt間の間隔(又は距離)を「(間隙DGの)間隔(又は距離)dgl」と呼び、同透明電極Xt,Ytの各エッジの対峙する部分の長さを「間隙DGの幅(又は長さ)dgw」と呼ぶことにする。これに対して、隣接する2本の母電極の対峙する各エッジ間の間隙(後述のように、非放電ギャップに該当)を「間隙NG」と呼ぶと共に、当該両エッジ間の間隔(又は距離)を「(間隙NGの)間隔(又は距離)ngl」と呼ぶことにする。 One end of each of the transparent electrodes Xti is connected to the mother electrode Xbi and projects into one of the two unit regions AR adjacent to the first direction D1 with the mother electrode Xbi in between. Moreover, each of the m transparent electrodes Xt is formed so as to project in alternating directions with respect to the first direction D1. That is, the adjacent transparent electrodes Xt are formed so as not to project to the same side. Similarly, each of the m transparent electrodes Yt forming the transparent electrode Yti is connected to the mother electrode Ybi at one end thereof, and in the unit region AR so that its overhanging directions are staggered with respect to the first direction D1. It has an overhanging shape. In particular, as shown in FIG. 5, the edges of the transparent electrode Xt and the transparent electrode Yt on the overhanging side are connected to each other via a predetermined gap (corresponding to a discharge gap as described later) DG in the same unit region AR. We are facing each other. Incidentally, opposed to the transparent electrode Xt, the spacing between Yt (or distance) is referred to as "(gap DG) spacing (or distance) dgl", the transparent electrodes Xt, the length of the opposed portions of each edge of Yt It will be referred to as "width (or length) dgw of the gap DG". On the other hand, the gap between the opposite edges of the two adjacent mother electrodes (corresponding to the non-discharge gap as described later) is called "gap NG", and the distance (or distance) between the two edges is called "gap NG". ) Will be referred to as "interval (or distance) ngl (of gap NG)".

列電極WW1〜WWm/2のそれぞれを駆動IC182の所定の1つの出力端子に接続することによって、AC−PDP72を、AC−PDP71と同様の駆動方法によって駆動可能である。このとき、隔壁10を挟んで隣接する2つの放電空間111にまたがって列電極WW1〜WWm/2のそれぞれが配置されていても、AC−PDP72では第1及び第2方向D1,D2に沿って放電セルCと非放電セルNCとが交互に配置されているので、誤放電を発生させることなくAC−PDP72を駆動することができる。 By connecting each of the column electrodes WW1 to WWm / 2 to a predetermined output terminal of the drive IC 182, the AC-PDP 72 can be driven by the same drive method as the AC-PDP 71. At this time, even if the column electrodes WW1 to WWm / 2 are arranged across the two adjacent discharge spaces 111 with the partition wall 10 in between, the AC-PDP 72 is provided along the first and second directions D1 and D2. Since the discharge cells C and the non-discharge cells NC are arranged alternately, the AC-PDP 72 can be driven without causing an erroneous discharge.

その他の変形例
上述の実施の形態1及び2に係る各駆動方法は、AC−PDP61,71,72以外に、従来のAC−PDP201(図11及び図12参照)にも適用可能である。即ち、共通の電圧供給される複数の放電セルCのそれぞれにおける放電を、個々の放電セルCに対して独立して供給される電圧(電位差)によって制御可能なAC−PDPは、上述の各駆動方法により駆動することができる。
< Other variants >
Each of the driving methods according to the above-described first and second embodiments can be applied to the conventional AC-PDP201 (see FIGS. 11 and 12) in addition to the AC-PDPs 61, 71 and 72. That is, the AC-PDPs capable of controlling the discharge in each of the plurality of discharge cells C to which a common voltage is supplied by the voltage (potential difference) independently supplied to each discharge cell C are described above. It can be driven by a driving method.

JP10643999A 1999-04-14 1999-04-14 Method for driving alternating-current type plasma display panel, plasma display device, and alternating- current type plasma display panel Pending JP2000298451A (en)

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JP10643999A JP2000298451A (en) 1999-04-14 1999-04-14 Method for driving alternating-current type plasma display panel, plasma display device, and alternating- current type plasma display panel
TW89120632A TW498299B (en) 1999-04-14 2000-10-04 Drive method for AC plasma display panel, plasma display unit and AC plasma display panel

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JP10643999A JP2000298451A (en) 1999-04-14 1999-04-14 Method for driving alternating-current type plasma display panel, plasma display device, and alternating- current type plasma display panel

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JP2000298451A JP2000298451A (en) 2000-10-24
JP2000298451A5 true JP2000298451A5 (en) 2005-07-14

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Publication number Priority date Publication date Assignee Title
WO2002025683A1 (en) * 2000-09-21 2002-03-28 Koninklijke Philips Electronics N.V. Plasma display panel electrode structure and method of driving a plasma display panel
US6787978B2 (en) 2000-11-28 2004-09-07 Mitsubishi Denki Kabushiki Kaisha Plasma display panel and plasma display device
JP2002279900A (en) * 2001-03-22 2002-09-27 Toray Ind Inc Triple electrode plasma display
JP2003208848A (en) 2002-01-16 2003-07-25 Mitsubishi Electric Corp Display device
TWI319558B (en) 2004-11-19 2010-01-11 Lg Electronics Inc Plasma display device and method for driving the same
JP4496991B2 (en) * 2005-02-28 2010-07-07 ソニー株式会社 Plasma display panel, plasma display device, and driving method of plasma display device

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