JP2000295309A - Channel coding and decoding device and base station - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily cope with system change, etc., about a channel coding and decoding device performing baseband processing of plural channels and a base station. SOLUTION: This channel coding and decoding device is provide with an outgoing transmission line interface part 11 having a 1st memory 22, an outgoing encoding part 12 having a 2nd memory 23, a coding processing part and a 3rd memory 26, an outgoing transmission line interface part 13 having a 4th memory 27, an incoming transmission line interface part 14 having a 5th memory 32, an incoming decoding processing part 15 having a 6th memory 33, a decoding processing part and a 7th memory 36, an incoming transmission line interface part 16 having a 8th memory 37 and a central operating part 17 which performs the detailed operation mode setting of each part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel code decoding device for performing baseband processing of a plurality of channels between a wired line and a wireless line in a mobile communication system, and a channel code decoding device. It relates to the base station used.

[0002]

2. Description of the Related Art A mobile communication system is a PDC (Persona).
l Digital Cellular (CDMA) system and CDMA (Code Div
Various methods, such as an ision Multiple Access method, are known. In each method, a plurality of base stations and an exchange or a control station are connected by a wired line, and mobile stations such as a mobile phone and a portable data terminal device communicate with each other via the base station by a wireless line. .

A base station in such a mobile communication system includes, for example, as shown in FIG. 26, a radio transmission / reception unit 201 for modulating / demodulating and amplifying radio transmission / reception signals, and a channel for performing baseband processing of a plurality of channels. A code decoding device 202 and a wired processing unit 2 connected to a wired line
03 is included.

A channel code decoding device 202
Is the interface unit 20 for the wireless transmitting / receiving unit 201
4, an interface unit 206 for the wired processing unit 203, and an encoding / decoding processing unit 205 for encoding and decoding data (audio data, image data, etc.) corresponding to the channel.

[0005] For example, in the case of a CDMA base station, the coding / decoding processing unit 205 performs downlink transmission for performing, for example, turbo coding, interleaving processing, information length matching processing, and the like on data from a wired line. It has a configuration of a path system and a configuration of an uplink transmission path system for performing information length matching processing, deinterleaving processing, turbo decoding, and the like of data received via a wireless line. Then, communication is performed on a channel assigned between a mobile station such as a mobile phone or a portable data terminal device (not shown) and the wireless transmitting / receiving unit 201 of the base station.

[0006]

A channel code decoding device of a base station in a mobile communication system needs to process data of a large number of channels at a high speed, and is generally constituted by hardware. . But,
In the case of an increase in the number of processing channels or a change in the format of data, it is necessary to add or change hardware. Therefore, there is a problem that it is not possible to flexibly deal with system expansion, system change, and the like.

A digital signal processor (D
A configuration in which baseband processing is performed using an arithmetic function of a processor such as SP) is conceivable. In this case, the processing function of the encoding / decoding processing unit 205 in FIG. 26 is realized by an arithmetic function using software of a processor. Can be dealt with. However, there is a problem of a long processing time and a problem of an increase in memory capacity due to the need for a large work area. An object of the present invention is to provide a configuration that can easily cope with a system change or the like.

[0008]

The channel code decoding apparatus according to the present invention comprises: (1) a downlink transmission line interface unit 11 having a first memory 22 for storing data subjected to termination processing; The first memory 22
To temporarily store the data transferred from
Encoding unit 12 having a memory 23 for storing the data processed by the encoding processing unit and a third memory 26 for storing data processed by the encoding processing unit.
A downlink transmission line interface unit 13 having a fourth memory 27 for storing data transferred from the third memory 26 and transmitting the data to a downlink transmission line; and processing data from an uplink transmission line. An uplink transmission line interface unit 14 having a fifth memory 32 for storing data, and a sixth memory 33 for temporarily storing data transferred from the fifth memory 32 for input to a decoding processing unit. , A seventh memory 3 for storing data processed by the decoding processing unit
6 and the seventh memory 3
6. An upstream transmission line interface unit 16 having an eighth memory 37 for storing the data transferred from 6 and transmitting the data to the upstream transmission line, and a central unit for controlling the transfer between the memories and the operation control of each unit. And an operation unit 17.

(2) The central processing unit 17 includes a processor such as a DSP and a program memory, and has a configuration for setting detailed operation mode information of each unit according to a program stored in the program memory. Further, an interface unit for transferring a program from the program group storage memory of the central management unit that performs call control and resource management to the program memory of the central processing unit 17 can be provided. Further, a quality management unit 18 for monitoring and managing the quality of the transmitted data and notifying the central processing unit can be provided.

(3) The first and second memories 22 and 23 and the seventh and eighth memories 36 and 37 are interconnected by a bus, and the third and fourth memories 26 and 27 and Fifth
The sixth memories 32 and 33 are mutually connected by a bus,
A configuration in which a folding circuit is formed by controlling the address of the memory and the timing of the bus by the central processing unit 17 can be provided. Also, when the central processing unit 17 updates the setting information, the central processing unit 17 can be provided with a function of notifying the start timing of the processing according to the new setting information.

(4) The downstream encoding unit 12 includes a second memory 23, a third memory 26, and a code processing unit that performs an encoding process according to the encoding control information set by the central processing unit 17. An information length matching processing unit for performing insertion and deletion according to the information length matching control information set from the central processing unit 17, and an interleave processing unit for performing interleaving processing according to the interleave pattern information set from the central processing unit 17. be able to. Also, the uplink decoding unit 15
A sixth memory 33, a seventh memory 36, a deinterleave processing unit for performing deinterleave processing according to the interleave pattern information set from the central processing unit 17, and information length matching control information set from the central processing unit 17 Information length control processing unit for performing insertion and deletion according to
7 that performs a decoding process in accordance with the decoding control information set from Step 7.

(5) The downlink transmission line interface unit 11 including the first memory 22 and the second and third memories 23,
26, a downlink transmission line interface unit 13 including a fourth memory 27, and a fifth memory 3
2, an uplink transmission line interface unit 14 including the second and third memories 33 and 36, and an eighth
A plurality of upstream transmission line interface sections 16 each including a memory 37 are provided, and a multiplexing configuration in which the memories are connected by a bus can be provided. Further, it is possible to provide a configuration in which the central processing unit 17 controls the same functional parts of the multiplexing configuration to operate in parallel according to the amount of processing information. In addition, the memory of each unit of the multiplex configuration may be a shared memory, and the central processing unit 17 may perform the area allocation control corresponding to the processing amount.

(6) The base station according to the present invention comprises the above-described channel code decoding device, a radio transmission / reception unit connected to the downlink transmission line interface unit 13 and the uplink transmission line interface unit 14, and a downlink transmission line interface unit. 11 and an upstream transmission line interface unit 16 are provided with a wired unit for connecting a wired line.

(7) Further, a multiplexing configuration in which a plurality of units of the channel code decoding device are provided and memories of the respective units are connected by a bus can be employed. Also, a central management unit for downloading from the host device to the program memory of the central processing unit 17 can be provided. Also, a configuration may be adopted in which a plurality of channel code decoding devices are connected to the wireless transmission / reception unit to perform load distribution.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a main part of a channel code decoding apparatus according to an embodiment of the present invention. Reference numeral 11 denotes a downlink transmission line interface, 12 denotes a downlink encoder, 1
Reference numeral 3 denotes a downlink transmission line interface unit, 14 denotes an uplink transmission line interface unit, 15 denotes an uplink decoding unit, 16 denotes an uplink transmission line interface unit, 17 denotes a central processing unit, and 18 denotes a quality management unit.

Reference numeral 21 denotes a transmission line terminator, 22, 23, and 2
6, 27 are first to fourth memories (RAM1, RAM2,
RAM3, RAM4), 24 are encoders, 25 is an information length matching interleaver, 28 is an interleave frame multiplexing unit, 29 is a memory (RAM 9), 30 is a quality monitoring controller, 31 is a frame separation deinterleaver, and 32 and 3
3, 36, and 37 are fifth to eighth memories (RAM 5, RA
M6, RAM7, RAM8), 34 is a deinterleave information length matching unit, 35 is a decoder, and 38 is a transmission path termination unit.

The downlink transmission line interface unit 13 and the uplink transmission line interface unit 14 are connected to a radio transmission / reception unit (not shown).
The upstream transmission path interface unit 16 is connected to a switching center or a control station via a wired line via a wired processing unit or the like. The central processing unit 17 includes a digital signal processor (DSP) and a program memory, and performs detailed operation mode setting and the like for each unit.

Adjacent units of the downstream transmission line system and the upstream transmission line system are connected to each other via a memory, and according to a predetermined timing controlled by the central processing unit 17 or a processing end notification from each unit. At this time, the data is transferred to the next stage via the memory, so that each unit can perform processing independently. An encoder 24 is formed by the encoder 24 of the downlink encoder 12 and the information length matching interleaver 25, and a decoding processor is formed by the deinterleave information length matching unit 34 and the decoder 35 of the uplink decoder 15. Is forming.

The transmission line termination unit 21 of the downlink transmission line interface unit 11 terminates the data input via the downlink transmission line, and stores the data in the memory 22. For example,
When the downstream transmission line and the upstream transmission line are ATM lines, the transmission line termination unit 21 can terminate the input ATM cell and assemble it into a frame.
Can be configured to assemble a frame into an ATM cell and transmit it to an upstream transmission line.

The data of the processing result in units of data blocks or frames is stored in the memory 22 and is transferred to the memory 23 of the downlink encoder 12. The encoder 23 encodes data in units of data blocks or frames from the memory 23 into, for example, a turbo code or the like, and the information length matching interleave unit 25 extracts or inserts bits so that the encoded data has a predetermined length. The length of the information is matched by the above method, and the data indicating the end of processing is stored in the memory 26.

When the processing result in the downstream encoding section 12 is stored in the memory 26, the result is transferred from the memory 26 to the memory 27 of the downstream transmission path interface section 13, and the interleave frame multiplexing section 28 performs the interleave processing and multiplexing. Then, for example, the data is transferred to a wireless transmitting / receiving unit (not shown).

The data input via the upstream transmission line is transmitted to the upstream transmission line interface unit 14 and the quality management unit 18.
Entered as The upstream transmission path interface unit 14 includes:
The frame separation deinterleave unit 31 performs a process reverse to the process of the downlink transmission line interface unit 13 and stores it in the memory 32. The data is transferred from this memory to the memory 33 of the uplink decoding unit 15 in data block units or frame units.

The deinterleave information length matching unit 34 of the uplink decoding unit 15 performs a process reverse to the process of the information length matching interleave unit 25 to restore the data subjected to the matching process to the original data.
The data is decoded by the decoder 35 and stored in the memory 36. When the decoding process in units of data blocks or frames is completed, the data is transferred from the memory 36 to the memory 37 of the upstream transmission line interface unit 16, and the data is transmitted to the upstream transmission line by the transmission line termination unit 38 in a format suitable for the upstream transmission line. I do.

The first to eighth memories 22, 23,
26, 27, 32, 33, 36 and 37 have a two-sided configuration,
When writing the data of the processing result on one side, read the data from the other side and transfer it to the next stage,
The operation of each unit can be performed continuously even in the processing in units of data blocks or frames.

Then, the downlink transmission path interface unit 11
Between the downlink encoding unit 12 and the downlink encoding unit 12 and the downlink transmission line interface unit 13, processing data is transferred by data transfer between memories, and similarly, the uplink transmission line interface unit 14 and uplink decoding unit 1
5, and between the uplink decoding unit 15 and the uplink transmission line interface unit 16, processing data is transferred by data transfer between memories.

Thus, each unit independently performs a processing operation, and transfers a processing result to the next stage by transferring between memories.
Then, the downlink transmission line system and the uplink transmission line system are realized by a hardware configuration to enable high-speed operation, and the central processing unit 17 sends each unit to a system change such as a change in the number of processing channels or a change in transmission format. Can be dealt with by setting the detailed operation mode. That is, it is possible to realize a configuration capable of flexibly responding without lowering the processing speed.

FIG. 2 is an explanatory view of a main part of a base station according to an embodiment of the present invention, wherein 1 is a radio transmitting / receiving section, 2 is a channel code decoding device, 3 is a wired processing section, and 4, 5, 7,. 8
Is a memory, 6 is an encoding / decoding processing unit, 9 is a central processing unit,
Reference numeral 10 denotes an antenna, 2a and 2c denote transmission line interface units, and 2b denotes an encoding / decoding unit.

The radio transmission / reception unit 1 can apply various known configurations corresponding to radio frequency bands, and includes a modulator, a power amplifier, and the like for transmitting from the antenna 10 to the mobile station. In addition, a configuration including a low-noise amplifier, a demodulator, and the like for amplifying a signal received from a mobile station via the antenna 10 is provided.

The central processing unit 9 of the channel code decoding device 2 corresponds to the central processing unit 17 in FIG. 1, and the memory 4 is the first and eighth memories 22, 37 in FIG.
(RAM1, RAM8), and the memory 5 is the second and seventh memories 23, 36 (RAM2, RAM8) in FIG.
7), the memory 7 corresponds to the third and sixth memories 26 and 33 (RAM3, RAM6) in FIG. 1, and the memory 8 corresponds to the fourth and fifth memories 27 and 27 in FIG. 32 (R
AM4, RAM5). The encoding / decoding processing unit 6 includes the encoder 24, the information length matching interleave unit 25, the deinterleave information length matching unit 34, and the decoder 3 in FIG.
5 or the like.

The central processing unit 9 sets detailed operation modes in the transmission line interface units 2a, 2c and the encoding / decoding unit 2b, and performs processing corresponding to a channel. The processing can be easily speeded up by performing the processing by hardware. The setting of the detailed operation mode from the central processing unit 9 can easily cope with a change in the number of processing channels.

FIG. 3 is an explanatory diagram of an embodiment of the present invention, in which a channel code connected between a wired network and a wireless network is used.
A decoding device is shown, 50 is a channel code decoding device, 51 is a downlink cable interface unit, 52 is a downlink encoding unit, 53 is a downlink radio frame multiplexing unit, 54 is an uplink radio frame separation unit, and 55 is uplink decoding. , 56 is an upstream wired interface unit, 57 is a central processing unit, 58 is a quality information calculation unit, and 59 is a quality information control unit.

Reference numeral 60 is a work memory, 61 is a check code addition multiplexing unit, and 62, 63, 66, and 68 are first to fourth.
Memory (RAM1, RAM2, RAM3, RAM
4) and 64 are turbo convolutional encoders, 65 is an information length matching interleaver, 67 is a setting table, 69 is a frame multiplexer, 70 is a logical channel multiplex interleaver, 7
1, 74, 77, 79 are fifth to eighth memories (RAM
5, RAM 6, RAM 7, RAM 8), 72 is a logical channel separation deinterleave section, 73 is a synchronization detection frame separation section, 75 is an information length matching deinterleave section, 76 is a turbo Viterbi decoder, 78 is a setting table, and 80 is separation information. A check unit, 81 is a program memory, 82 is a quality information memory, 83 is an alarm monitoring unit, 84 is an interface unit, 85 is a digital signal processor (DSP), and 86 is a central management unit composed of a processor (CPU). Show. The setting tables 67 and 78 are constituted by registers and a random access memory, and set detailed operation modes and the like.

The term "wireless network" refers to the side of the wireless line including the above-mentioned wireless transmitting / receiving unit, and the term "wired network" refers to the side of the wired line such as an exchange. Down indicates the transmission direction from the mobile station to the mobile station, and up indicates the transmission direction from the mobile station to the wired network. Further, the central management unit 86 communicates with the channel code decoding device 50
The control information is transmitted and received via the interface unit 84, a detailed operation mode setting and the like is instructed from the central processing unit 57, and the state information on the wireless line side is read via the quality information control unit 59. The update function of the detailed operation mode can be set by the management function of (1).

Also, the downstream wired interface unit 51 is configured as shown in FIG.
Corresponds to the downstream transmission path interface unit 11. In addition,
Although the illustrated positional relationship between the memory 62 and the check code addition multiplexing unit 61 is opposite to the flow of data, termination processing is performed on data input via the downlink cable network, and the check code addition multiplexing unit 61 is processed. Then, an error check code is added by a CRC calculation or the like, and the result is stored in the memory 62. Also in this case, the data in the data block unit or the frame unit is stored in the memory 62 and transferred to the memory 63 of the downlink encoding unit 52.

The downstream transmission path interface unit 13 shown in FIG.
1 and the upstream wired interface unit 56 corresponding to the upstream transmission line interface unit 14 in FIG. 1, the positions of the memories 71 and 79 shown in FIG. For example, the uplink radio frame separation unit 54 stores the data of the processing result by the logical channel separation deinterleave unit 72 and the synchronization detection frame separation unit 73 in the memory 71, and from this memory 71 to the memory 74 of the uplink decoding unit 55. To transfer the data. Also, the memory 77 of the upstream decoding unit 55
Then, the data is transferred to the memory 79 of the upstream wired interface unit 56 corresponding to the upstream transmission line interface unit 16 in FIG. 1, and the separation information check unit 80 performs an error check and sends the data to the upstream wired network.

The downstream encoder 52 includes a turbo convolutional encoder 64 and an information length matching interleaver 65, and performs turbo encoding or convolutional encoding on the data read out from the memory 63 in units of data blocks or frames. The information is stored in the memory 66 after performing an information length matching process and the like, and is transferred from the memory 66 to the memory 68 of the downlink radio frame multiplexing unit 53. The uplink decoding unit 55 includes an information length matching deinterleave unit 75 and a turbo Viterbi decoder 76, and performs decoding of turbo codes or Viterbi decoding in the case of only convolutional codes. That is, important data reduces the error rate by combining turbo encoding and turbo decoding,
General data can be transmitted and received by combining convolutional coding and Viterbi decoding. Such encoding and decoding methods can be applied to the CDMA method.

The central processing unit 57 includes a DSP 85 and a program memory 81.
It is used as a work area for P85. Further, the setting of the detailed operation mode of each unit from the central processing unit 57 is performed by a bold path. For example, the setting tables 67 and 78 of the downlink encoding unit 52 and the uplink decoding unit 55
In addition, information about the logical channel, such as the logical channel type and the logical channel information length, and information for determining the processing operation such as the encoding / decoding type, the physical channel information length, and the operation start timing information are set. Note that the DSP 85 can be a normal processor.

By setting the constraint length information from the central processing unit 57 to the setting table 67 of the downstream encoding unit 52,
The turbo convolutional encoder 64 can perform convolutional coding or turbo coding according to the constraint length. Also, by setting the constraint length information in the setting table 78 of the uplink decoding unit 55, the turbo Viterbi decoder 7
In step 6, Viterbi decoding or turbo decoding can be performed. Further, by setting the interleave pattern information in the setting tables 67 and 78, the interleave in the information length matching interleave section 65 and the deinterleave in the information length match deinterleave section 75 can be performed.

The quality information calculation unit 58 identifies the quality of the radio channel by calculating an error rate or the like based on the data processed by the uplink radio frame separation unit 54, and
9 and stored in the quality information memory 82. Further, the alarm monitoring unit 83 can send an alarm when the error rate exceeds a predetermined value, for example. Central processing unit 5
7 collects the state information of each unit along the dotted line route, and when it is determined that the operation of each unit needs to be changed, the setting can be updated along the above-mentioned thick line route. Central processing unit 5
7, the operation start time and the like can be set, so that the operation of each unit can be started from the operation start time after the setting information is updated. Therefore, it is possible to shift to an optimal process according to the communication state and the like.

The central management unit 86 can perform call control, resource management, and the like.
To the central processing unit 57 via the PC or the quality information control unit 5
9 can be transmitted and received. According to the result, the central processing unit 57 can instruct the updating of the setting information to each unit.

FIG. 4 is an explanatory diagram of downloading a program according to the embodiment of the present invention. The same reference numerals as in FIG. 3 denote the same parts, and 87 denotes a program group storage memory. The programs stored in the program group storage memory 87 are programs for determining the operation, control, sequence, and the like of the central processing unit 57, and store a plurality of programs each having different contents.

Then, under the control of the central management unit 86, the selected program is read from the program group storage memory 87 and downloaded to the program memory 81 of the central processing unit 57. After the download process, the DSP 85 of the central processing unit 57 performs settings for each unit and sequence control according to the contents of the program memory 81. That is, by changing the program of the central processing unit 57, it becomes possible to change the function of channel processing and the sequence control, and even if the capacity of the program memory 81 is reduced, it is possible to easily cope with desired functions. become.

FIG. 5 is an explanatory diagram of downloading from a higher-level device according to the embodiment of the present invention. The same reference numerals as in FIG. 3 denote the same parts, and reference numeral 90 denotes a higher-level device in a mobile communication system. There are a plurality of base stations under the control of the higher-level device 90, so that a plurality of other channel code decoding devices 50 not shown are connected. That is, a program according to the operation change is downloaded from the host device 90 to the program memory 81 of the central processing unit 57 via the central management unit 86 and the interface unit 84 due to a system change or the like.

When it is necessary to change the setting information for each unit based on the downloaded program, the central processing unit 57 changes the setting as described with reference to FIG. , The processing according to the updated setting information is started. Therefore, the program can be downloaded so that the channel code decoding device in the system performs the same processing operation.

FIG. 6 is an explanatory view of transmission and reception of test patterns according to the embodiment of the present invention. The same reference numerals as those in FIG. 3 denote the same parts, 91 denotes a test pattern generator, 92 denotes a test pattern checker, and 93a and 93a. Reference numerals 93b, 94a, and 94b denote folding circuits formed equivalently. Test pattern generator 91
Generates a test pattern in accordance with an instruction from the DSP 85 of the central processing unit 57 and sends out the test pattern along the path indicated by the thick arrow. Also in this case, the test pattern is transferred to the memory 63 of the downstream encoding unit 52 at the next stage via the memory 62.
The receiving side, not shown, can confirm the normality of the downlink wireless network by checking the reception of the test pattern.

The test pattern check unit 92 receives and checks a test pattern from a transmitting side (not shown). In this case, too, the memory 7 of the uplink decoding unit 55
7 to the memory 79 of the upstream wired interface unit 56, the test pattern stored in the memory 79 is checked by the test pattern check unit 92, and the normality of the upstream wireless network can be confirmed.

In transferring data between the memories, the read / write of the memories in accordance with the sequence control of the central processing unit 57, etc.
By the write control and the address control, for example, the memory 6
2 can be written into the memory 79 via the folding circuit 93a. That is, the first and second memories 62 and 63 and the seventh and eighth memories 77 and 79 are connected to each other by a bus, and the use timing of this bus and the control of the read address and the write address for the memory are controlled. In addition, it is possible to form folding circuits 93a, 93b, 94a, and 94b for transferring arbitrary data to an arbitrary memory.

For example, at the timing of the test pattern read from the first memory 62, the second
The test pattern is written from the first memory 62 to the eighth memory 79 by adding the enable signal and the write address to the eighth memory 79 of the upstream wired interface unit 56 without adding the enable signal to the memory 63 of the first embodiment. be able to. That is, the test pattern data can be turned back through the turn-back circuit 93a.

That is, since the data is transferred between the units via the memory, the memory control allows
It is easy to write data read from one memory to another memory. Thereby, the test pattern generation unit 91
Since the test pattern can be turned back at a desired position and checked by the test pattern check unit 92, the normality of each unit can be confirmed and the fault can be isolated.

FIG. 7 is an explanatory diagram of frame multiplexing according to the embodiment of the present invention. The DSP 85, the third memory (RAM 3) 66 of the downstream encoding unit 52, and the fourth memory of the downstream radio frame multiplexing unit 53. A memory (RAM4) 68 is shown, and the memories 66 and 68 are connected by a bus.
By transferring from a certain address of the memory 66 to a certain address of the memory 68 by the address control by the SP 85, it is possible to store the multiplexed data in the area of the memory 68 corresponding to the physical channel.

For example, as shown in FIG. 8, when the frames 1 to 4 processed in the downlink encoder 52 are multiplexed in the downlink radio frame multiplexer 53, the third When the frames 1 to 4 are sequentially read from the memory No. 1 and written into one physical channel area of the fourth memory and multiplexed, the data is shown as frame multiplexed data 1. Further, when the reading order of the frames 1 to 4 is changed, the read order becomes the frame multiplexed data 2.

Like frame multiplexed data 3 in which only frames 1 and 2 are written in one physical channel area and multiplexed, or only frames 3 and 4 are written in one physical channel area and multiplexed. It is also possible to extract and multiplex an arbitrary frame. That is, pattern multiplexing can be performed according to the processing program of the DSP 85.

The third memory 66 and the downlink radio frame multiplexing unit 5 of the
By the address control of the third fourth memory 68, frame switching and copying can be easily performed. For example, as shown in FIG.
To CH4), the frames 1 to 4 can be sorted as shown in the upper part, or can be sorted in reverse order as shown in the middle part. Also, as shown in the lower section,
Frame 1 is copied and the transmission channels (CH1 to CH
The same frame 1 can be sorted to 4). Such memory control can be easily realized by address control and timing control by the program processing of the DSP 85.

FIG. 10 is an explanatory diagram of the frame separation process according to the embodiment of the present invention. The DSP 85, the fifth memory (RAM5) 71 of the upstream radio frame separation unit 54, and the sixth memory of the upstream decoding unit 55 are described. The memory (RAM 6) 74 shown in FIG.
6 and 68, the bus connection is used.
The transfer control is performed so that the frame is separated from the memory 71 to the memory 74 by the address control by the address 5.

For example, the frame multiplexed data 1 shown in FIG.
, Various kinds of separation as shown in FIG. 11 are possible. That is, frame separation 1 for separating frames 1 to 4 according to the arrangement order of frames 1 to 4,
4, the frame separation 2 for separating the upstream frames 1 to 4 in the reverse order, the frame separation 3 for copying the frame 1 to the upstream frames 1 to 4, the frame 1 for the upstream frame 1, the frames 2 and 3 for the upstream frame 2, Also, separation patterns such as a frame separation 4 for separating the upstream frame 3 into frames 3 and 4 and an upstream frame 4 into frames 4 can be easily realized.

FIG. 12 is an explanatory diagram of the processing type changing configuration according to the embodiment of the present invention.
2 shows a third memory (RAM3) 66, a fourth memory (RAM4) 68 of the downlink radio frame multiplexing unit 53, and a timing control unit 95. The timing control unit 95 has a function of performing timing control at the time of changing the processing type. This function is a function of the DSP 85, but the downlink encoding unit 52 and the downlink radio frame multiplexing unit 5
3 is shown as a separate configuration for the description of the timing control with respect to FIG. The memories 66 and 68 are connected by a bus.

The desired multiplexing is performed by transferring the frame stored in the memory 66 of the downstream encoder 52 to an area corresponding to the physical channel of the memory 68 of the downstream radio frame multiplexer 53 under the control of the DSP 85. Things
Various multiplexing processes as described with reference to FIGS. 7, 8 and 9 can be performed. When such a processing type is changed, as described above, the central processing unit 57 (see FIG. 3)
The setting information of the program memory 81 is changed, and the function of the timing control unit 95 is used to compare the system timing with the change timing to control the process type change timing.

FIG. 13 is an explanatory diagram of a process type changing operation according to the embodiment of the present invention. The system timing input to the timing control unit 95, the change timing, the multiplex setting as setting information, and the downlink radio frame multiplexing unit 53, for example, when the contents of a counter for counting system timing are 8, 9, 10,
When the system timing changes, as shown by the arrow at the time of the system timing 9, the multiplex processing in the order of the frames 1 to 4 of the multiplex setting is performed as the DSP setting change. When the setting for changing to the multiplex processing in order is performed, the timing control unit 95 sets the change timing to 10 next to the current system timing 9.

It should be noted that it is also possible to set a change timing to the next 11 in consideration of the processing time of the multiplex processing or the like. Then, the set change timing is compared with the count content of the system timing, and when they match, the multiplexing process is changed using the timing of the arrow of the component factor operation change as the process type change timing.

Therefore, when the count value of the system timing reaches 10, the frame multiplexed output is changed from the multiplexing process of frames 1 to 4 to the Changed to multiple processing. In this case, it is possible to change the processing type while maintaining the continuity of the multiplex processing.

FIG. 14 is an explanatory diagram of a processing type changing configuration according to the embodiment of the present invention. The DSP 85, the fifth memory (RAM5) 71 of the uplink radio frame separation unit 54, and the fifth decoding unit 55 of the uplink decoding unit 55 6 shows a memory (RAM 6) 74 and a timing control section 96. The timing control section 96 corresponds to the timing control section 95 in FIG. 12, and shows a part of the function of the DSP 85 separately. The memories 71 and 74 are connected by a bus.

Memory 71 of uplink radio frame separation section 54
The operation of transferring the data from the region corresponding to the physical channel to the memory 74 of the uplink decoding unit 55 under the control of the DSP 85 and performing the separation process is the same as, for example, the case shown in FIG.
Then, when the process type of the separation process is changed, the timing control unit 96 sets the change timing based on the system timing and performs the timing control.

FIG. 15 is an explanatory diagram of the separation processing change operation according to the embodiment of the present invention. The figure shows the system timing, the change timing, the separation setting, and the frame separation output. The system timing is counted by the same function as the control unit 95,
The change timing is set according to the setting change. For example, when the DSP setting change of the arrow occurs when the count content of the system timing is 9, the next 10 of the count content 9 is set as the change timing and compared with the count content of the system timing.

Therefore, when the count value of the system timing becomes 10, it coincides with the set change timing of 10. Therefore, the separation setting is changed as shown by the change in the constituent factor operation of the arrow, and the frame 2 is changed from the frame 1, 3 to the frame 2. , 4 are changed.

Also in this separation processing, it is possible to set the change timing based on the system timing by the timing control section 96, control the change of the processing type, and make the change while maintaining the continuity of the separation processing. it can.

FIG. 16 is an explanatory diagram of the downlink encoder according to the embodiment of the present invention. The same reference numerals as those in FIG.
101 is a code processing unit, 102 is an information length control processing unit, 10
3 is an interleave processing unit, 104 is a turbo RAM interleave table RAM, 105 is an information length matching table RAM, 106 is an interleave table RAM,
07 is a turbo convolutional encoder, 108 is a control information interface, 109 is a table RAM interface, 1
Reference numeral 10 denotes an information insertion / deletion enable control unit, 111 denotes a control information interface, 112 denotes a table RAM interface, 113 denotes an address generation unit, 114 denotes a control information interface, and 115 denotes a table RAM interface.

Each table RAM 104, 105, 106
Corresponds to the setting table 67 in FIG. The code processing unit 101 corresponds to the turbo convolutional encoder 64 in FIG. 3, and the information length matching processing unit 102 and the interleave processing unit 103 are different from the information length matching interleave unit 6 in FIG.
Equivalent to 5.

The central processing unit 57 stores interleave pattern information in turbo coding, constraint length information in convolutional coding, etc. in the table RAM 104 and control information such as insertion, deletion, and enable for information length matching. To Table R
The interleave pattern information for interleaving after the information length matching process is stored in the table RAM 10.
6 respectively. Control information interface 10
The processing information amount (data block length or frame length or the amount of information stored in the memory) is set via 8, 111, and 114, respectively.

Based on such setting information, the code processing unit 1
01 reads information according to the amount of processing information from the memory (RAM 3) 63, and the turbo convolutional encoder 107 reads the table R via the table RAM interface 109.
Turbo coding is performed by performing convolutional coding with the constraint length according to the setting information of the AM 104 and interleaving processing according to the interleave pattern information to perform convolutional coding.

The information insertion / deletion enable control section 110 of the information length matching processing section 102 performs an insertion, deletion, or enable / disable operation according to the setting information of the table RAM 105 via the table RAM interface 112.
The information length matching process is performed by invalidation control or the like, and the
M3) Write to 66. In this case, the address generation unit 113 of the interleave processing unit 103
6 is written to the third memory 66 in accordance with the interleave pattern of the setting information of No. 6 and the information of the amount of setting processing information (data block length or frame length) stored in this memory 66 is written to the third 4 (RAM4) 66 (see FIG. 3).

FIG. 17 is an explanatory diagram of an uplink decoding unit according to an embodiment of the present invention. The same reference numerals as those in FIG. 3 denote the same parts,
121 is an information length control processing unit, 122 is a decoding processing unit, 12
3 is a deinterleave processing unit, 124 is a turbo decoder deinterleave table RAM, 125 is an information length matching table RAM, and 126 is a deinterleave table RA.
M and 127 are information insertion / deletion enable controllers, 128
129 is a control information interface, 129 is a table RAM interface, 130 is a Turbo / Viterbi decoder, 131
Is a control information interface, 132 is a table RAM interface, 133 is a read address generator, 134
Indicates a control information interface, and 135 indicates a table RAM interface.

Each table RAM 124, 125, 126
Corresponds to the setting table 78 in FIG. The information length matching processing section 121 and the deinterleave processing section 123 correspond to the information length matching deinterleave section 75 in FIG. 3, and the decoding processing section 122 corresponds to the turbo Viterbi decoder 76 in FIG. Equivalent to.

The central processing unit 57 stores the deinterleave pattern information in the table RAM 126 and the control information such as insertion, deletion and enable for information length matching in the table RAM 126.
125, and control information relating to turbo code decoding is set in the table RAM 124. Also, the processing information amount (data block length or frame length or the amount of information stored in the memory) is set via the control information interfaces 128, 131, and 134, respectively.

The read address generation unit 133 of the deinterleave processing unit 123
An address for deinterleaving the memory (RAM 6) 74 is generated on the basis of the setting information of the table RAM 126 read via the control information interface 35 and the amount of processing information via the control information interface 134. As a result, the information deinterleaved from the memory 74 is input to the information length matching processing unit 121, and is deleted, inserted, or enabled based on the setting information in the table RAM 125 and the processing information amount via the control information interface 128. Effectiveness,
Perform invalidation control, etc.

The processed data for which the information length matching process has been completed is applied to the turbo Viterbi decoder 1 of the decoding processing unit 122.
Reference numeral 30 denotes a turbo code decoding process based on setting information such as constraint length information and interleave information set in the table RAM 124 and a processing information amount via the control information interface 131, or Vidabi decoding of a convolutional code. Processing, and outputs the decryption processing result to a seventh memory (RAM 7) 7
7, and from this memory 77, an eighth memory (RAM 8) 79 (FIG.
Transfer).

Accordingly, with respect to interleaving and deinterleaving, pattern information can be set in the table RAMs 106 and 126 and updated and settable, so that any interleave pattern can be handled. Various matching methods are also known in the information length matching processing when transmitting to a wireless line. However, by updating the setting information in the table RAMs 105 and 125, any matching processing can be performed. Various types of turbo codes have already been proposed, but these can be flexibly dealt with by using control information such as a convolution constraint length and an interleave pattern set in the table RAMs 104 and 124. Further, even when the processing information amount such as the data block length and the frame length is changed, it can be easily dealt with by setting from the central processing unit 57.

FIG. 18 is an explanatory diagram of a multiplexing configuration according to an embodiment of the present invention. The same reference numerals as those in FIGS. 3 and 6 denote the same parts. Each part has a multiplexed configuration, and is mutually connected in the form of a bus. The central processing unit 57 and the work memory 60 are shared by the multiplexed units, and are provided between the first and second memories 62 and 63 and the third and fourth memories 66 and 68.
Between the fifth and sixth memories 71 and 74, and between the seventh and eighth memories 71 and 74.
For example, multiplexing and demultiplexing as shown in FIGS. 8, 9 and 11 are performed by controlling the transfer between the memories 77 and 79 by controlling the timing of the bus connecting the memories and the address of the memories. be able to.

Therefore, it is possible to easily cope with a change in the number of processing channels, and to control an increase in processing load so as to perform distributed processing among the same functional blocks. The return circuits 93a, 93b, 94a, and 94b by buses for interconnecting the memories are formed by timing control and memory address control, thereby confirming the normality of each unit and isolating a fault location. A turn-back test can be performed. In this case, the test pattern generation section and the test pattern check section can be provided in one place by controlling the timing of the bus connection configuration.

FIG. 19 is an explanatory diagram of a duplicated channel code decoding device according to an embodiment of the present invention. Duplicated channel code decoding devices 50A and 50B each have the configuration shown in FIG. The same parts are shown. Then, the central management unit 86 can give various settings and control instructions to the central processing unit 57 via the respective interface units 84. Further, a large capacity base station can be configured by adding a channel code / decoding device and making it triple and quadruple. With such a multiplexing configuration, it is also possible to improve the reliability by adding a switching configuration of the working and the standby such as 1: 1 or N: 1.

FIG. 20 is an explanatory diagram of the load distribution of the multiplexing configuration according to the embodiment of the present invention. The same reference numerals as in FIGS. 3, 6, 18 and the like denote the same parts.
1 and processing blocks 150-1 to 150-1 of the downlink encoding unit 52
In a multiplexing configuration including 50-n, processing block 15
The case where processing is distributed to 0-1, 150-n is shown. For example, when the processing amount in one processing block is larger than the processing amount in the downlink wireless frame multiplexing unit 53, the DSP 85 sends the downlink wireless frame multiplexing unit 53
, Channel allocation setting information A in the processing block 150-1 and channel allocation setting information A 'in the processing block 150-n.

In this case, the channel allocation setting information A, A ′
Are the same setting information, and are the processing blocks 150-1 and 150-1.
Regarding the processing data to be input to 50-n, the read address from the memory at the preceding stage is made different, and the processing data is distributed and processed in parallel, so that the load of the downstream encoding unit 52 and the like is distributed, Higher speed can be achieved.
In addition, it is also possible to process a larger number of processing blocks in parallel for one downlink radio frame multiplexing unit 53.

FIG. 21 is an explanatory diagram of load distribution in the multiplexing configuration according to the embodiment of the present invention. In FIG. 21, the same reference numerals as those in FIGS. And a processing block including a downstream encoding unit 52,
53-1 to 53-n indicate multiplexed downlink radio frame multiplexing units. This embodiment shows a case where the load on the downlink radio frame multiplexing unit is heavy, contrary to the case shown in FIG.
For example, when transmitting large-capacity data such as moving image data on the mobile station side, transmission may be performed using a plurality of channels. It can be applied in such a case. That is, D
The normal channel allocation setting information C is set in the processing block 150 from the SP 85, and the downlink radio frame multiplexing unit 53-1 is set.
And the channel assignment setting information D ′ is set in the downlink radio frame multiplexing unit 53-n.

In this case, channel assignment setting information D, D '
Are the same setting information, and only the read addresses of the memory (RAM3) 66 (see FIG. 18) of the downlink encoding unit 52 are different, and the downlink radio frame multiplexing units 53-1, 53
−n, and multiplexing processing is performed in parallel. Also in this case, it is possible to operate more downlink radio frame multiplexing units in parallel.

FIG. 22 is an explanatory diagram of the effective use of the memory according to the embodiment of the present invention. As shown in FIG. 18 or FIG.
When the multiplex configuration is adopted, the third memory (RAM3) 66
Is used by the central processing unit 57, and the area is divided and assigned according to the information processing amount of each channel.

For example, in the central processing unit 57, the amount of information to be processed in channel n is large, and conversely, channel n + 1
If the amount of information to be processed is small, the channel n + 1
Of the area of the memory 66 of the downstream encoder 52 is assigned to the channel n. Therefore, the downlink encoder 5 of channel n
2 memory 66 and the downlink encoder 52 of channel n + 1
Of the channel n, including the partial area of the memory 66 of FIG. Therefore, even if the memory 66 has a small capacity, the memory 66 can be interchanged between the channels, so that the memory can be effectively used.

FIG. 23 is an explanatory diagram of the effective use of memory according to the embodiment of the present invention. As shown in FIG. 18 or FIG.
When a multiplex configuration is adopted, the sixth memory (RAM 6) 74
Are managed in the central processing unit 57, and the area allocation control is performed in accordance with the information processing amount of each channel. For example, using the area of the memory 74 of the uplink decoding unit 55 corresponding to the channel n and a partial area of the memory 74 of the uplink decoding unit 55 corresponding to the channel n + 1, n, and the uplink decoding unit 55 corresponding to the channel n + 1 transfers the processing data to and from the uplink radio frame separation unit 54 using the remaining area of the memory 74. That is, since the empty area of the memory 74 of the uplink decoding unit 55 corresponding to each channel can be effectively used, there is an advantage that the memory 74 having a relatively small capacity is sufficient.

FIG. 24 is an explanatory diagram of frame multiplexing according to the embodiment of the present invention. In FIG. 24, the same reference numerals as those in FIGS. 18 and 19 indicate the same parts. The case where the shared memory 160 sharing the RAM 3) 66 is managed by the central processing unit 57 is shown. Also, the fourth radio frame multiplexing unit 53 corresponding to the multiplexed channel
The memory (RAM4) 68 and the shared memory 160 are connected by a multiplexed bus, and the timing control and address control, for example, encode the channel n encoded processing data into the channel n + 1 corresponding downlink radio frame multiplexing unit 53.
To the memory 68 for frame multiplexing. That is, it is possible to effectively use the memory resources in consideration of the processing amount of each unit.

The fourth memory 68 of the downstream radio frame multiplexing unit 53 is also used as a shared memory,
7, and by allocating the area of the shared memory according to the data processing amount, it is possible to effectively use the memory.

FIG. 25 is an explanatory diagram of frame separation according to the embodiment of the present invention. The same reference numerals in FIGS. 18 and 19 denote the same parts, and the fifth memory of the multiplexed upstream radio frame separation unit 54 Shared memory 1 sharing (RAM5)
A case in which 61 is managed by the central processing unit 57 is shown. Also, the shared memory 161 and the memory 7 of each uplink encoding unit 55
5 are connected by a multiplex bus, and frame separation can be distributed by timing control and address control.

Also, the sixth memory 75 of the upstream decoding unit 55 is managed as a shared memory by the central processing unit 57, and the allocation of the memory area is controlled according to the data processing amount, so that the memory can be effectively used. Can be achieved.

The present invention is not limited to the above-described embodiments, but may have a configuration corresponding to each combination. Although the encoding unit and the decoding unit are shown in the case of turbo codes, they can be configured to correspond to the encoding format in the mobile communication system. Therefore, it can be applied to base stations in various communication systems.

[0092]

As described above, according to the present invention, the downlink transmission line interface section 11 having the first memory (RAM1) 22, the second memory (RAM2) 23, the encoding processing section, and the third A downlink encoding unit 12 having a memory (RAM3) 26, a downlink transmission line interface unit 13 having a fourth memory (RAM4) 27, and an uplink transmission line interface unit 14 having a fifth memory (RAM5) 32; , An uplink decoding unit 15 having a sixth memory (RAM6) 33, a decoding processing unit and a seventh memory (RAM7) 36, and an uplink transmission line interface unit 16 having an eighth memory (RAM8) 37. And a central processing unit 17 for setting detailed operation modes of the respective units.
A decoding device and a base station using the channel code / decoding device. The central processing unit 17 can easily cope with a change in the number of channels, a change in the format, and the like by setting the detailed operation mode of each unit. There are advantages.

[0093] Further, since the respective units such as the downlink encoding unit 12 and the uplink decoding unit 15 are configured to transfer the processing result data via the memory, the data flow can be maintained even when the setting information is updated. Processing can be switched at a change timing according to the setting information without interruption. In addition, there is an advantage that high-speed processing can be performed by executing the encoding processing and the decoding processing by hardware.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a main part of a channel code decoding device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a main part of a base station according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of an embodiment of the present invention.

FIG. 4 is an explanatory diagram of downloading a program according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of downloading from a higher-level device according to the embodiment of this invention.

FIG. 6 is an explanatory diagram of transmission and reception of a test pattern according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram of a frame multiplexing process according to the embodiment of this invention.

FIG. 8 is an explanatory diagram of frame multiplexed data according to the embodiment of this invention.

FIG. 9 is an explanatory diagram of frame distribution according to the embodiment of this invention.

FIG. 10 is an explanatory diagram of a frame separation process according to the embodiment of this invention.

FIG. 11 is an explanatory diagram of frame separation according to the embodiment of this invention.

FIG. 12 is an explanatory diagram of a processing type changing configuration according to the embodiment of this invention.

FIG. 13 is an explanatory diagram of a process type changing operation according to the embodiment of this invention.

FIG. 14 is an explanatory diagram of a processing type changing configuration according to the embodiment of this invention.

FIG. 15 is an explanatory diagram of a separation processing change operation according to the embodiment of this invention.

FIG. 16 is an explanatory diagram of a downlink encoding unit according to an embodiment of the present invention.

FIG. 17 is an explanatory diagram of an uplink decoding unit according to an embodiment of the present invention.

FIG. 18 is an explanatory diagram of a multiplexing configuration according to an embodiment of the present invention.

FIG. 19 is an explanatory diagram of a duplex channel code decoding device according to an embodiment of the present invention.

FIG. 20 is an explanatory diagram of load distribution of the multiplex configuration according to the embodiment of this invention.

FIG. 21 is an explanatory diagram of load distribution in a multiplex configuration according to the embodiment of this invention.

FIG. 22 is an explanatory diagram of effective memory utilization according to the embodiment of this invention.

FIG. 23 is an explanatory diagram of effective memory utilization according to the embodiment of this invention.

FIG. 24 is an explanatory diagram of frame multiplexing according to the embodiment of this invention.

FIG. 25 is an explanatory diagram of frame separation according to the embodiment of this invention.

FIG. 26 is an explanatory diagram of a main part of a base station.

[Explanation of symbols]

Reference Signs List 11 downlink transmission line interface unit 12 downlink encoding unit 13 downlink transmission line interface unit 14 uplink transmission line interface unit 15 uplink decoding unit 16 uplink transmission line interface unit 17 central processing unit 18 quality management unit 22, 23, 26, 27th 1st to 4th memories (RAM
1 to RAM 4) 24 encoder 25 information length matching interleave unit 28 interleave frame multiplexing unit 31 frame separation deinterleave unit 32, 33, 36, 37 fifth to eighth memories (RAM)
5 to RAM 8) 34 Deinterleave information length matching unit 35 Decoder

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Kazunori Hisama 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka-shi, Fukuoka Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Tomoharu Abe Hakata-ku, Fukuoka-shi, Fukuoka Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inside of Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Keijiro Kubo 3-22-8, Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Inventor Mitsunari Mohri 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture F-term in Fujitsu Kyushu Digital Technology Co., Ltd. AA21 BB04 EE10 FF02 HH23 KK13 KK15

Claims (15)

[Claims] 1. A downlink transmission path interface unit having a first memory for storing data subjected to termination processing, and temporarily storing data transferred from the first memory to an encoding processing unit. A downstream encoding unit having a second memory and a third memory for storing data processed by the encoding processing unit; a process of storing data transferred from the third memory and transmitting the data to a downstream transmission path A downlink transmission line interface unit having a fourth memory for processing, and an uplink transmission line interface unit having a fifth memory for processing and storing data from the uplink transmission line. A sixth memory for temporarily storing the data transferred from the memory of No. 5 for input, and a seventh memory for storing data processed by the decoding processing unit; An uplink transmission line interface unit having an eighth memory for storing data transferred from the seventh memory and sending the data to an uplink transmission line; and performing transfer control between the memories and operation control of the units. A channel code decoding device comprising a central processing unit. 2. The central processing unit includes a processor and a program memory, and the processor is configured to set detailed operation mode information of each unit according to a program stored in the program memory. 2. The channel code decoding device according to claim 1, wherein: 3. An interface unit for transferring a program from a program group storage memory of a central management unit for performing call control and resource management to the program memory under the control of the central management unit. 3. The channel code decoding device according to 1 or 2. 4. The channel code according to claim 1, further comprising a quality management unit that monitors and manages the quality of transmitted data and notifies the central processing unit of the quality. -Decoding device. 5. The first and second memories and the seventh and eighth memories are connected to each other by a bus, and the third and fourth memories and the fifth and sixth memories are connected to each other. 2. A configuration in which the components are connected to each other by a bus, and a folding circuit is formed by controlling the address of a memory by the central processing unit and controlling the timing of the bus.
The channel code decoding device according to any one of claims 1 to 4. 6. The downlink encoding unit, the second memory, the third memory, a code processing unit that performs an encoding process according to encoding control information set from the central processing unit, An information length matching processing unit that performs insertion, deletion, and the like according to the information length matching control information set by the central processing unit; and an interleave processing unit that performs interleaving processing according to the interleave pattern information set by the central processing unit. The channel code decoding device according to any one of claims 1 to 5, wherein: 7. The uplink decoding unit, wherein the sixth memory, the seventh memory, a deinterleave processing unit that performs deinterleave processing according to interleave pattern information set from the central processing unit, An information length control processing unit that performs insertion and deletion according to the information length matching control information set by the central processing unit; and a decoding processing unit that performs decoding processing according to the decoding control information set by the central processing unit. The channel code decoding device according to claim 1, wherein: 8. When the setting information is updated from the central processing unit, the update is performed on the downlink encoding unit and the downlink transmission line interface unit, and on the uplink transmission line interface unit and the uplink decoding unit. 8. The channel code decoding apparatus according to claim 1, wherein a function of notifying a change timing due to setting information update is provided in the central processing unit. 9. A downlink transmission line interface unit including the first memory, a downlink encoding unit including the second and third memories, a downlink transmission line interface unit including the fourth memory, A plurality of uplink transmission line interface units including a fifth memory, a plurality of uplink transmission line interface units including the sixth and seventh memories, and a plurality of uplink transmission line interface units including the eighth memory are provided. 9. The channel code decoding apparatus according to claim 1, further comprising a multiplexing configuration in which memories are connected by a bus. 10. The apparatus according to claim 9, wherein said central processing unit controls the same functional parts of said multiplexing structure to operate in parallel according to the amount of processing information.
The channel code decoding device according to the above. 11. The channel code according to claim 9, wherein a memory of each unit of said multiplexing configuration is a shared memory, and said central processing unit performs a region allocation control corresponding to a processing amount. Decoding device. 12. A downlink transmission path interface unit having a first memory for storing data subjected to termination processing, and temporarily stores data transferred from the first memory to an encoding processing unit. A downlink encoding unit having a second memory and a third memory for storing data processed by the encoding processing unit; and a process of storing data transferred from the third memory and sending the data to a downlink transmission path. 4th to do
A downlink transmission line interface unit having a memory, an uplink transmission line interface unit having a fifth memory for processing and storing data from an uplink transmission line, and a transfer from the fifth memory to a decoding processing unit. A sixth memory for temporarily storing the input data to be input, a seventh memory for storing data processed by the decoding processing unit, and an uplink decoding unit that has been transferred from the seventh memory. A channel comprising an uplink transmission line interface unit having an eighth memory for storing data and sending the data to an uplink transmission line, and a central processing unit for controlling transfer between the memories and controlling operation of the units. A mobile station connected to a code decoding device, a downlink transmission line interface unit having the fourth memory, and an uplink transmission line interface unit having the fifth memory; A wireless transmission / reception unit that wirelessly transmits / receives data to / from, a downlink transmission line interface unit having the first memory, and a wired connection unit that connects a wired line to the uplink transmission line interface unit having the eighth memory. A base station comprising: 13. The memory device according to claim 13, wherein the channel code decoding device includes a plurality of the downlink transmission line interface units, the encoding processing unit, the uplink transmission line interface units, and the decoding processing units. The base station according to claim 12, wherein the base stations are connected by a bus to form a multiplex configuration. 14. A central management unit which communicates with a host device for a plurality of base stations and downloads detailed operation mode settings of the channel code decoding device to a program memory of the central processing unit. The base station according to claim 12, wherein: 15. The base station according to claim 12, wherein a plurality of said channel code decoding devices are connected to said wireless transmission / reception unit.