JPH10303870A - System switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely reconfigure a system with no deterioration of the transmission quality by securing the retiming of a differential pulse which shows the change of the binary information showing a working system to its own system clock, generating a delayed differential pulse for a period of an idle time slot of the relevant frame, masking its own clock between the front and rear edges of the delayed differential pulse, acquiring a shaping clock and then transferring this clock. SOLUTION: A differentiation means 12 and a clock transfer means 13 generate a delayed differential pulse via the retiming secured by its own clock and then mask this clock for a period set between the front and rear edges of the delayed differential pulse. Thus, a shaping clock is obtained. A clock relay means 14 selects one of the shaping clock and the clock of another system that is corresponding to the value of the binary information at a time point of the rear edge of the delayed differential pulse and transfers the selected clock to a subsequent transmission section as a relay clock. A data relay means 15 and a frame pulse relay means 16 send the data corresponding to the value of the binary information with timing secured by the relay clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission apparatus which relays a transmission line or an inter-station transmission line to which a standby redundancy system and a synchronous transfer mode are applied for each transmission section, and adapts to the result of system reconfiguration. System switching circuit that switches between a data signal to be relayed and a synchronization signal.

[0002]

2. Description of the Related Art In recent years, the cost of optical fiber cables has been reduced and the high-level digital transmission technology has been applied, so that the optical transmission line is combined with the transmission line of the trunk line, for example, the transmission line of the subscriber line system. It is also being applied to efficiently accommodate a large number of subscribers located at points remote from the exchange. Also, with the demand for multimedia communication, the amount of transmission information that each subscriber must send and receive is becoming enormous, and at the same time, there is a shortage of excess space in the pipelines where railroads are laid in large cities. To deal with
The optical transmission path described above is useful.

However, since a large amount of transmission information is multiplexed and transmitted in such an optical transmission line, it is possible to prevent a huge transmission line from being lost due to a failure in a transmission device or the like. In order to ensure desired reliability in this way, a standby redundant system or another redundant configuration is applied. FIG. 5 is a diagram showing a configuration of a subscriber line system for accommodating a subscriber via a duplicated transmission line.

In the figure, the concentrators 70-1 to 70-N individually connected to a plurality of subscriber lines are respectively provided with multiplex transmission lines 7.
An optical transmission line 73-1 of a full-duplex system to which a standby redundancy system is applied via 1-1 to 71-N and a subscriber line system transmission device 72.
73-2. These optical transmission paths 73-1 and
The other end of 73-2 is provided with a switching device 75 via a multiplexing transmission device 74.
, And a maintenance system device 76 is connected to a communication port of the multiplex transmission device 74.

[0005] The multiplexing transmission device 74 is provided with EO boards 77 longitudinally belonging to the optical transmission paths 73-1 and 73-2, respectively.
-1, 77-2, and interface boards 78-1U, 78-1D, 78-2U, 78-2D corresponding to the uplink and downlink of these optical transmission lines 73-1 and 73-2. Consists of
The interface boards 78-1U and 78-2U and the interface boards 78-1D and 78-2D are connected to each other, and all the interface boards 7-1D and 78-2D are connected to each other.
8-1U, 78-1D, 78-2U, 78-2D are connected to the maintenance system device 76.

The above-mentioned "downlink" is from the exchange 75 to the multiplex transmission device 74 and the optical transmission lines 73-1 and 73-.
2, subscriber line transmission device 72, multiplex transmission lines 71-1 to 71-
N and the concentrators 70-1 to 70-N means a path to a subscriber line (not shown), and "uplink" means a concentrator 70-1 to 70-N, a multiplex transmission line from these subscriber lines. 71-1 to 71-N, subscriber line transmission device 72, optical transmission line 7
This means a path to the exchange 75 via 3-1 and 73-2 and the multiplex transmission device 74.

In the conventional example having such a configuration, the interface boards 78-1U and 78-2U have optical transmission lines 73-1 and 73-2 and EO boards 77-1 and 7-2 for upstream lines, respectively.
When the state of 7-2 is individually monitored and any failure is recognized, the maintenance system unit 76 is notified of the failure, and in the case of urgency, a reconfiguration to automatically switch the own system to the standby system is performed. To do. However, when the system reconfiguration is requested from the maintenance system device 76 according to the judgment of the maintenance / person in charge or the above-mentioned notification, the interface boards 78-1U, 78-2
The U switches its own system to the active system or the standby system by preferentially responding to the request.

[0008] Of the interface boards 78-1U and 78-2U, the interface board which has become the active system corresponds to the inbound route (outbound route) of the exchange 75 and the interface board of the standby system, and its own system. The received signal (composed of a data signal, a frame pulse and a clock) received from the optical transmission line is given in parallel. On the contrary, the interface board, which is the backup system, replaces the reception signal (composed of the data signal, the frame pulse and the clock) received from the optical transmission line corresponding to the own system as described above. The received signal given from the interface board of the system is given to the corresponding incoming route (outgoing route) of the exchange 75.

That is, of the optical transmission lines 73-1 and 73-2,
Between one of the optical transmission lines corresponding to the interface board that has become the active system and the ingress path (outgoing path) of the exchange 75 corresponding to these optical transmission paths 73-1 and 73-2. , A standby redundant transmission line connected to the above-mentioned subscriber line via the concentrators 70-1 to 70-N and the subscriber line transmission device 72 is formed.

Interface boards 78-1D and 78-2D
The operation of the interface boards 78-1U, 7 except that the "downlink of the ingress path (outgoing path) connected to the exchange 75" is to be monitored instead of the optical transmission path.
Since the operation is the same as that of the 8-2U, its description is omitted here. Further, the transmission and reception of the line signal and the register signal performed in each transmission section in conformity with the call processing of the call generated on the subscriber line described above are not directly related to the present invention, and the description thereof is omitted here. I do.

[0011]

By the way, in the above-mentioned conventional example, the interface boards 78-1U, 78-1D, 78-2.
U and 78-2D are reconfigured asynchronously with the reception signals received via the transmission lines and optical transmission lines 73-1 and 73-2 laid between the multiplex transmission device 74 and the exchange 75. Had gone.

Therefore, with respect to the clock transmitted to the succeeding transmission section, the high-level or low-level period may be significantly shortened depending on the timing of switching according to the reconstruction. However, such a clock having an abnormal waveform is transmitted to the trunk or the subscriber line transmission device 72 connected to the corresponding route of the exchange 75.
The setup time (the logical value of the information to be latched is determined at the time when the latching is to be performed) to guarantee the normal operation of the flip-flop circuit provided for switching with the internally generated clock. The minimum time to be confirmed in advance) is not secured,
Encoding and decoding performed by a circuit such as a codec is not normally performed, and further, a bit error occurs in transmission information.

An object of the present invention is to provide a system switching circuit which can surely and stably realize system reconfiguration without deterioration of transmission quality.

[0014]

FIG. 1 is a block diagram showing the principle of the invention described in claims 1-5.

The invention described in claim 1 is separately provided in the first link and the second link which constitute the transmission line adapted to the synchronous transfer mode and the standby redundancy system, and is obtained from the preceding transmission section. Two link-corresponding parts 11 that individually configure two systems that respectively pass the acquired own system data signal, own system frame pulse, and own system clock as other system data signal, other system frame pulse, and other system clock, respectively-
1 and 11-2, and two link corresponding parts 11-1 and 11-
2 is a clock synchronized with the own system clock for a differential pulse which is given from the outside and indicates a change point of binary information indicating the active system when a system reconfiguration request adapted to the standby redundancy system is given. A differentiating means 12 which is generated with timing,
The differentiated pulse generated by the differentiating means 12 is retimed by the own system clock to generate a delayed differentiated pulse, and the own system clock is masked over a period sandwiched between the leading edge and the trailing edge of the delayed differentiated pulse. Of the shaped clock obtained by the clock changing means 13 and the other system clock delivered from the other system, the one corresponding to the value of the binary information is used as the differentiated pulse. A clock relay means 14 for selecting at the time of the trailing edge and transmitting it as a relay clock to a subsequent transmission section, and corresponding to the value of binary information between the own system data signal and the other system data signal delivered from another system One of them is selected at the time of the trailing edge of the delayed differential pulse, and the timing is changed by the relay clock sent by the clock relay means 14 while the timing is changed. Data relay means 15 for transmitting as a relay data signal in a transmission section, and one of the own system frame pulse and the other system frame pulse delivered from the other system corresponding to the value of the binary information after the delayed differential pulse. Frame pulse relay means 16 which is selected at the edge and is retimed by the relay clock transmitted by the clock relay means 14 and is transmitted as a relay frame pulse in the subsequent transmission section, and the configuration of the applied frame and others. Based on the system frame pulse and "the condition under which a delayed differential pulse is generated during the empty time slot of that frame"
The timing adjusting means 17 is provided to obtain a time point that satisfies the above condition and to give a request for system reconstruction to the differentiating means 12 at that time point.

According to a second aspect of the invention, in the system switching circuit according to the first aspect, two link corresponding parts 11-
The reference numerals 1 and 11-2 each include a storage unit 21 in which single or a plurality of pieces of identification information individually indicating empty time slots are stored, and the timing adjustment unit 17 uses the individual identification information stored in the storage unit 21. It is characterized in that the points satisfying the conditions are sequentially obtained for the empty time slots shown, and the system reconfiguration request is given to the differentiating means 12 at these points.

According to a third aspect of the present invention, in the system switching circuit according to the second aspect, the two link corresponding units 11-
1 and 11-2 are provided with monitoring means 31 to which the identification information of a single or a plurality of empty time slots is given by a transmission device or an exchange which opposes via a link, and which sequentially stores these identification information in a storage means 21 It is characterized by having. According to a fourth aspect of the present invention, in the system switching circuit according to the second aspect, a line signal is multiplexed on the own system data signal and the other system data signal based on a predetermined format, and two link signals are provided. The corresponding units 11-1 and 11-2 transmit the own system data signal or the other system data from the preceding transmission section based on the signal system applied to the first link and the second link and a predetermined format. By analyzing a line signal received as a signal, the identification information of a single or a plurality of empty time slots is acquired, and a monitoring means 31a for sequentially storing the identification information in the storage means 21 is provided. I do.

According to a fifth aspect of the present invention, in the system switching circuit according to any one of the second to fourth aspects, the timing adjusting means 17 provides the differentiating means 12 with a number of times for giving a system reconfiguration request. Is limited to “1” per predetermined number of consecutive frames. In the system switching circuit according to the first aspect of the present invention, the differentiating means 12 is provided in the link corresponding units 11-1 and 11-2, for example, in the link corresponding unit that operates as a standby system.
When a reconfiguration request of a system adapted to the standby redundancy system is given, a differential pulse which is given from the outside and indicates a change point of binary information indicating the working system is retimed by a clock synchronized with the own system clock. To generate. The clock transfer means 13 generates a delayed differential pulse by retiming the differential pulse with the own system clock, and further, the own system clock over a period sandwiched between the leading edge and the trailing edge of the delayed differential pulse. To generate a shaped clock.

Further, the clock relay means 14 selects one of the above-described shaping clock and the other system clock given from the other system corresponding to the value of the binary information at the trailing edge of the differential pulse. It is transmitted as a relay clock to the subsequent transmission section. The data relay means 15 selects one of the own system data signal and the other system data signal given from the other system corresponding to the value of the binary information at the trailing edge of the delayed differential pulse, and The relay clock is sent as a relay data signal to the subsequent transmission section while retiming with the relay clock sent by the means 14. The frame pulse relay means 16 selects one of the own system frame pulse and the other system frame pulse given from the other system, which corresponds to the value of the binary information at the trailing edge of the delayed differential pulse. And, while taking retiming with the above-mentioned relay clock, it transmits it to the subsequent transmission section as a relay frame pulse.

Further, the above-mentioned system reconfiguration request is obtained by referring to the frame configuration to which the timing adjusting means 17 is applied and the frame pulse of the other system as a reference. When the condition for generating the delayed differential pulse is satisfied, the differentiating means 12
Give to. That is, in each link corresponding part that has changed from the standby system to the active system or from the active system to the standby system due to the system reconfiguration, the clock sent to the subsequent transmission section immediately after the system reconfiguration. Since the single pulse in is surely masked, the period from the rising edge to the falling edge and the period from the falling edge to the rising edge are never less than the normal length.

Further, the single missing of the relay clock due to such masking does not cause the deterioration of the transmission quality and the speech quality because it occurs during the empty time slot under the structure of the frame. Note that, in the link corresponding unit that has been operating as the active system, the differentiating means 12 and the clock changing means 13 perform the same operations as described above even if the direction in which the system is reconfigured is reversed, and The means 14 selects the other system clock (that is, given from the link corresponding part which has newly become the working system) in place of the shaping clock generated by the clock transfer means 13. However, the other system clock is equal to the clock generated as the shaped clock as described above in the link corresponding unit that has newly become the active system.

Therefore, the relay data signal, the relay frame pulse and the relay clock are similarly and surely switched in both the link corresponding parts which are the active system and the standby system depending on the reconfiguration of the system. In the system switching circuit according to the invention described in claim 2, the link corresponding parts 11-1, 1
In both 1-2, single or plural pieces of identification information individually indicating empty time slots are stored in the storage means 21 in advance. Further, the timing adjusting means 17 sequentially obtains the time points that satisfy the conditions for the empty time slots indicated by the individual identification information stored in this way, and requests the differentiating means 12 to reconfigure the system at each of these time points. give.

Therefore, even when there are a plurality of empty time slots included in a unit frame, the present invention is not limited to the above embodiment.
In the same manner as in the system switching circuit described in (1), the reconfiguration of the system is reliably performed, and the larger the number of empty time slots, the sooner the reconfiguration of the system is started, thereby improving the responsiveness. In the system switching circuit according to the third aspect of the present invention, in the two link corresponding units 11-1 and 11-2, the monitoring means 31 has the identification information of a single or a plurality of empty time slots opposed via the link. Provided by the transmission device or the exchange, and these pieces of identification information are sequentially stored in the storage means 21.

Therefore, with respect to the link of the standby redundancy system composed of the first link and the second link, it is possible to flexibly apply the dynamic change of the allocation according to the call processing. In the system switching circuit according to the fourth aspect of the present invention, a line signal is multiplexed on the own system data signal and the other system data signal based on a predetermined format.

In the link corresponding units 11-1 and 11-2, the monitoring means 31a is based on the above-mentioned format and the signal system applied to the first link and the second link.
By analyzing the line signal received as the own system data signal or the other system data signal from the preceding transmission section, the identification information of a single or a plurality of empty time slots is acquired, and the identification information is sequentially stored. To store.

Therefore, the link of the standby redundancy system including the first link and the second link can be operated flexibly applied to the dynamic change of the allocation according to the call processing. In the system switching circuit according to the fifth aspect of the present invention, the timing adjusting means 17 includes the differentiating means 12.
Is limited to "1" for a predetermined number of consecutive frames.

That is, unnecessary and frequent reconfiguration of the system due to the large number of empty time slots can be avoided, so that the judgment and work related to maintenance and operation can be simplified. .

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a diagram showing an embodiment corresponding to the invention described in claims 1 to 5. In the drawing, the difference from the conventional example shown in FIG. 5 is that a multiplex transmission device 74a is provided instead of the multiplex transmission device 74, and the multiplex transmission device 74a has interface boards 78-1U, 78 -1D, 7
Interface panel 7 instead of 8-2U and 78-2D
8a-1U, 78a-1D, 78a-2U, and 78a-2D.

The interface boards 78a-1U, 78
The system switching circuits 40-1U, 40-1D, 40-2U, and 40-2D are provided in the a-1D, 78a-2U, and 78a-2D, respectively.
The system switching circuits 40-1D and 40-2D are not shown for simplicity. The system switching circuit 40
-1U and 40-2U are connected to each other as shown in FIG. 2, and the system switching circuits 40-1D and 40-2D are also connected to each other (not shown).

FIG. 3 is a diagram showing the configuration of the system switching circuit. Since the system switching circuit shown in this figure is individually provided for all of the above-mentioned interface boards 78a-1U, 78a-1D, 78a-2U, and 78a-2D, the interface board 78a-1U will be referred to as "own system" hereinafter. , And the interface board 78a-2U mutually connected to the interface board 78a-1U is called "other system", and only the system switching circuit 40-1U provided in the interface board 78a-1U is focused on. The configuration is shown.

In the own system, a data signal (hereinafter, referred to as “own system HW signal”) received from the uplink of the optical transmission line 73-1 is given to the D input of the flip-flop 41, and The non-inverted output of the above supplies the "other system HW signal" to the system switching circuit 40-2U (hereinafter, reference numeral is omitted) provided in the other system, and at the same time, one input W of the selector 43 via the flip-flop 42. Connected to. The “other system HW signal” given by the system switching circuit provided in the other system is D of the flip-flop 44.
The non-inverted output of the flip-flop 44 is supplied to the other input X of the selector 43 via the flip-flop 45. The output Y of the selector 43 is supplied to the exchange 75 via the flip-flops 46 and 47 by the "HW signal".
give.

A frame pulse (hereinafter referred to as “own system FP”) received from the uplink of the optical transmission line 73-1 is applied to the D input of the flip-flop 48, and the non-inverting of the flip-flop 48 is performed. The output gives the "other system FP" to the system switching circuit provided in the other system, and one input W of the selector 50 via the flip-flop 49.
Connected to. The “other system FP” provided by the system switching circuit provided in the other system is provided to the input of the delay circuit 51 and the D input of the flip-flop 52, and the non-inverted output of the flip-flop 52 is passed through the flip-flop 53 to the selector. The other input X of 50 is made. Selector 50
Output Y gives an "FP signal" to the exchange 75 via the flip-flops 54 and 55.

Further, a "system switching signal" is given to the D input of the flip-flop 56 by the maintenance system device 76, and the output of the delay circuit 51 is connected to the enable input E of the flip-flop 56. Flip flop 56
Is connected to the shift input D of the shift register 57 and one input of the exclusive OR gate 58.
The output Q0 of the first stage of the shift register 57 is connected to the other input of the exclusive logic gate 58 and the selection input S of the selector 59, and the output Q1 of the next stage of the shift register 57 is connected to the selection input S of the selectors 43 and 50. Connected. The output of the exclusive OR gate 58 is connected to the D input of the flip-flop 60, and the inverted output of the flip-flop 60 is connected to one input of the AND gate 61. Optical transmission line 7
The clock received from the 3-1 uplink (hereinafter,
It is called "own system HW clock". ) Is flip-flop 6
0 clock terminal CK and the other input of AND gate 61, and to other systems as "other system HW clock".

The "other system HW clock" given from another system is connected to the clock terminal CK of the flip-flops 44, 45, 52 and 53 and the other input X of the selector 59, and the output Y of the selector 59 is output. Is flip-flop 4
It is connected to the clock terminals CK of 6, 47, 54, and 55, and gives a "clock" to the exchange 75. To the clock terminals CK of the flip-flops 41, 42, 48, 49, 56 and the shift register 57, a system clock that is locally generated in the own system and has the same frequency as the own system HW clock is applied. Flip-flops 41, 4
A reset signal is supplied to the reset terminals R of 2, 44 to 49, 52 to 56, 60 and the shift register 57.

The correspondence between the present embodiment and the block diagram shown in FIG.
U, 78a-2U (78a-1D, 78a-2D) correspond to the link correspondence units 11-1, 11-2, and the flip-flop 56, the shift register 57, and the exclusive OR gate 58 correspond to the differentiating means 12. , Flip-flop 60 and AND gate 61 correspond to clock transfer means 13, and shift register 57 and selector 59 correspond to clock relay means 1.
4 corresponding to the flip-flops 41, 42, 44-4.
7, the selector 43 and the shift register 57 correspond to the data relay means 15, and include flip-flops 48, 49, 5
2 to 54, the selector 50 and the shift register 57 correspond to the frame pulse relay means 16,
1a corresponds to the timing adjusting means 17, the memory 62 corresponds to the storing means 21, and the empty slot monitoring circuit 63 corresponds to the monitoring means 31 and 31a.

FIG. 4 is an operation time chart of this embodiment corresponding to the invention described in claims 1 to 5. Hereinafter, referring to FIG. 2 to FIG. 4, claims of the present embodiment in the process of performing system reconfiguration in a state where the own system is operating as the standby system and the other system is operating as the active system The operation corresponding to the invention described in 1 will be described.

In such a state, the logical value of the system switching signal provided from the maintenance system device 76 is set to "0", the switching instruction signal obtained at the non-inverted output of the flip-flop 56, and the first stage of the shift register 57. Similarly, the logical values of the first system designating signal and the second system designating signal output from the next stage are also held at "0" (FIG. 4).
(1)). The selector 59 selects “another system HW clock” according to the logical value of the first system designation signal and gives it to the exchange 75 as a “clock”. The selector 43 outputs the “other system HW signal” given from the other system via the flip-flops 44 and 45 to the exchange 75 via the flip-flops 46 and 47 in accordance with the logical value of the second system designating signal.
As an "HW signal". Furthermore, the selector 50
In accordance with the logical value of the second system designation signal described above, the "other system FP" given from another system via the flip-flops 52 and 53 is transferred to the exchange 75 via the flip-flops 54 and 55 to the exchange 75. Give as.

Further, the delay circuit 51 generates a system switching timing signal by giving a delay over a predetermined time to the "other system FP" provided from another system.
On the other hand, when the maintenance system device 76 requests the “other system FP” to asynchronously reconfigure the system, the logical value is “1” for the system switching circuit to be the active system. A system switching signal is given, and a system switching signal having a logical value of "0" is given to a system switching circuit to be a standby system (FIG. 4 (2)).

In the flip-flop 56, when the logical value of the system switching signal thus applied is inverted and becomes "1", during the period in which the logical value of the system switching timing signal becomes "1", The switching instruction signal is generated by setting the logical value of the non-inverted output to “1” at the rising of the system clock (FIG. 4C). The shift register 57 delays the switching instruction signal over two stages while synchronizing with the system clock, and the exclusive OR gate 58 outputs the switching instruction signal between the input of the shift register 57 and the output Q0 of the first stage. By taking the exclusive OR of the logical values of, the differential pulse whose logical value temporarily becomes "1" is output (FIG. 4 (4)). Further, the flip-flop 60 samples this differential pulse at the falling timing of the "self-system HW clock" generated in the self-system as described above (FIGS. 4 (5) and (6)). A delayed differential pulse having the same pulse width as the differential pulse and the opposite logic value and delayed is generated (FIG. 4 (7)).

Further, the logical value of the first system designation signal given to the selector 59 is switched at the same time when the logical value of the output of the first stage of the shift register 57 changes from "0" to "1", so that the selector 59 is changed. "Other system HW clock"
Instead, the shaped clock given from the AND gate 61 is selected and given to the exchange 75 (FIG. 4 (8)), and the shaped clock is generated by the AND gate 61 using the "own system HW clock" and the above-mentioned delayed differential pulse. It is generated by taking the logical product.

Therefore, the clock obtained by the selector 59 selecting the shaped differential clock instead of the "other system HW clock" in accordance with the first system designating signal is shown by hatching in FIG. Since a single pulse is generated by being removed, it is possible to prevent the logical value from being illegally inverted at a short interval regardless of the phase difference between the "self system HW clock" and the "other system HW clock". Is done.

For the "own system HW signal", "other system HW signal", "own system FP" and "other system FP", flip-flops (41, 42), (44, 45),
(48, 49) and (52, 53) give a delay corresponding to two cycles of "system clock" or "other system HW clock". These "system clock" and "other system HW clock" are given. Is equal with high precision, the time becomes equal to the delay time generated in the flip-flop 56 and the shift register 57.

Further, flip-flops (46, 47),
Regarding the delay time generated at (54, 55), since the frequency of the “own system HW clock” and the frequency of the “system clock” are equal with high accuracy as described above, the flip-flop 60
And the second delay time caused by the elimination of the single pulse described above.

By the way, the delay time of the delay circuit 51 is
Period of "empty time slot that is not allocated to any of subscribers and calls and is not used as a communication link that should be used for maintenance and operation (here, it is assumed to be known)" In addition, the "timing at which the above-described single pulse is removed from the clock to be supplied to the exchange 75" is preset to a value that satisfies the condition under the frame structure of the "system HW signal".

As described above, according to this embodiment, regarding the clock to be continuously supplied to the exchange 75 in accordance with the reconfiguration of the system, the length of the period in which both the binary values of the clock are maintained. Does not become shorter than the standard length, so that the exchange 75 secures the setup time and improves the operation stability. Further, since the clock is switched during the empty time slot, even if a bit error occurs in the transmission information, the deterioration of the transmission quality and the service quality can be avoided.

Hereinafter, an embodiment corresponding to the second aspect of the present invention will be described. The difference between the present embodiment and the embodiment corresponding to the first aspect of the present invention is that, as shown in FIG. 3, a delay circuit 51a is provided instead of the delay circuit 51, and an external circuit of the delay circuit 51a is provided. The point is that the output of the memory 62 is connected to the input. Hereinafter, the operation of this embodiment according to the second aspect of the present invention will be described with reference to FIG.

In the memory 62, under the above-described frame configuration, "an empty time which is not allocated to any of the subscribers and the calls and is not used as a communication link to be provided for maintenance / operation etc." A single or a plurality of (= K) time slot numbers indicating a slot (here, it is assumed to be known) are stored in advance. The delay circuit 51a refers to the set of time slots stored in the memory 62 at the time of start-up (if necessary, at a predetermined frequency as needed), and refers to the "other system F".
By using P as a reference, the condition that “the above-described clock switching is performed during these empty time slots” is satisfied for each frame, and the system switching timing signal including a train of K pulses is satisfied. To generate.

Therefore, according to the present embodiment, even when there are a plurality of empty time slots without being continuous in time series, the time slots can be reliably determined in the same manner as the embodiment according to the first aspect of the present invention. The reconfiguration of the system is performed, and the possibility that the reconfiguration of the system is quickly started is increased as compared with the embodiment corresponding to the invention described in claim 1. Less than,
Embodiments corresponding to the third and fourth aspects of the present invention will be described.

The difference between the present embodiment and the embodiment corresponding to the invention described in claim 2 is that the output of the exclusive OR gate 58 is the delay circuit 51a as shown by the dotted line in FIG.
At the point connected to the control input. Hereinafter, the operation of the present embodiment will be described with reference to FIG. The delay circuit 51a monitors the differentiated pulse output by the exclusive OR gate 58, and when the differentiated pulse is output, the switching circuit outputs the switching timing signal over a desired period of a single frame period or more from that time. Hold output.

In other words, even if a failure or a erroneous operation of the maintenance system device 76 requires a plurality of system reconfigurations within a frame period (the logical value of the system switching signal is inverted), The reconfiguration of the system is restricted from repeating until the desired period described above has elapsed. Therefore, according to the present embodiment, unnecessary confusion of maintenance and operation due to frequent system reconfiguration is avoided.

An embodiment corresponding to the invention described in claim 5 will be described below. The difference between the present embodiment and the embodiment corresponding to the invention described in claims 3 and 4 is that the empty slot monitoring circuit 63 to which the "other system HW signal" and the "other system FP" are given from another system The output of the empty slot monitoring circuit 63 is provided and is connected to the write input of the memory 62.

Hereinafter, the operation of this embodiment will be described. The empty slot monitoring circuit 63 monitors the bit string included in each time slot indicated by the “other system HW signal” by using the “other system FP” as a reference on the time axis,
Whether or not the bit string indicates "a time slot that is not assigned to any of subscribers and calls and is not used as a communication link that should be used for maintenance and operation" like a silent pattern Is determined.

Further, the empty slot monitoring circuit 63 sequentially stores the time slot numbers indicating the time slots in the memory 62 for the time slots identified as empty time slots as a result of such determination. However, conversely, as a result of the above-mentioned discrimination, regarding "a time slot which is newly assigned to any one of the subscriber and the call, or is started to be used as a communication link to be provided for maintenance and operation", The time slot number previously stored in the memory 62 is deleted.

As described above, according to this embodiment, the delay circuit 51a can surely generate the system switching signal adapted to the dynamic allocation of the individual time slots constituting the frame, so that the transmission lines can be diversified. The invention described in claims 1 to 4 can be applied while flexibly adapting to various operation modes. In the present embodiment, an empty time slot is identified by determining whether or not a silence pattern is received for a time slot to be provided for transmission of a call signal. Format (multi-frame configuration may be applied)
, The determination as to whether or not a time slot corresponding to the relevant line signal is available may be made based on the signal system.

Further, in the present embodiment, the above-mentioned empty time slot is identified by the empty slot monitoring circuit 63. For example, a switch connected via the preceding transmission section or the succeeding transmission section, In the case where the transmission device dynamically allocates time slots, even if the identification information of an empty time slot notified by these exchanges or the transmission device via some communication link is applied instead of the identification result described above. Good.

Further, in each of the above-described embodiments, a switching circuit is provided which is individually associated with the uplink and the downlink, and the system is individually reconfigured for the uplink and the downlink. For example, the interface boards (78a-1U, 78a-1D) and the interface boards (78a-2U, 78a-2D) are paired (that is, the up link and the down link are one pair). System reconfiguration may be performed (in pairs).

In each of the embodiments described above, the present invention is applied to the transmission line of the subscriber line system. However, the present invention can be similarly applied to the transmission line between stations. further,
In each of the embodiments described above, the duplicated optical transmission line 73-
Although the present invention is applied to the multiplex transmission device 74a disposed between the switch 73 and the switching device 75-2, the present invention is not limited to such an optical transmission line, but includes a metallic transmission line and a wireless transmission line. If the standby redundancy system is applied to the transmission line, it can be similarly applied.

[0059]

As described above, according to the first aspect of the invention, when the system is reconfigured, the clock sent to the subsequent transmission section has a period from the rising edge to the falling edge and a period from the falling edge to the rising edge. The cause that the length becomes shorter than the standard length and the transmission quality and the call quality deteriorate is eliminated.

According to the invention described in claim 2, the system reconfiguration is surely performed in the same manner as the system switching circuit according to claim 1 even when there are a plurality of empty time slots included in a unit frame. And the larger the number of empty time slots, the sooner the system reconfiguration is started and the higher the responsiveness. Further, in the inventions according to claims 3 and 4, the operation in which the transmission line of the standby redundancy system composed of the first link and the second link is flexibly applied to the dynamic change of the allocation according to the traffic. Becomes possible.

Further, in the invention described in claim 5, it is possible to simplify the judgment and work involved in maintenance and operation. Therefore, in the transmission system to which these inventions are applied, malfunctions of the transmission device and the exchange due to system reconfiguration are avoided while adapting to call processing and various signal systems, and reliability and quality of service are further improved. In addition, the running cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the invention described in claims 1 to 5.

FIG. 2 is a diagram showing an embodiment corresponding to the invention described in claims 1 to 5.

FIG. 3 is a diagram illustrating a configuration of a system switching configuration circuit.

FIG. 4 is an operation time chart of the present embodiment corresponding to the first to fifth aspects of the present invention.

FIG. 5 is a diagram showing a configuration of a subscriber line system that accommodates subscribers via a duplicated transmission path.

[Explanation of symbols]

11 Link Corresponding Section 12 Differentiation Means 13 Clock Transfer Means 14 Clock Relay Means 15 Data Relay Means 16 Frame Pulse Relay Means 17 Timing Adjusting Means 21 Storage Means 31, 31a Monitoring Means 40 Switching Circuits 41, 42, 44-49, 52-56 , 60 flip-flop 43, 50, 59 selector 51, 51a delay circuit 57 shift register 58 exclusive OR gate 61 AND gate 62 memory 63 empty slot monitoring circuit 70 concentrator 71 multiplex transmission line 72 subscriber line transmission device 73 optical transmission Route 74, 74a Multiplex transmission device 75 Switch 76 Maintenance system device 77 EO board 78 Interface board

Claims (5)

[Claims] 1. A self-system data signal obtained from a preceding transmission section, which is separately provided on a first link and a second link which constitute a transmission line adapted to a synchronous transfer mode and a standby redundancy system, Two link correspondence units each independently configuring two systems for mutually passing the own system frame pulse and the own system clock as the other system data signal, the other system frame pulse, and the other system clock, respectively. When a system reconfiguration request adapted to the standby redundancy system is given, a differential pulse, which is given from the outside and indicates a change point of binary information indicating the active system, is a clock synchronized with the own system clock. Differentiating means for generating while retiming, and generating a delayed differentiated pulse by retiming the differentiated pulse generated by the differentiating means with the own system clock,
Clock changing means for obtaining a shaped clock by masking this own system clock over a period sandwiched between the leading edge and the trailing edge of the delayed differential pulse; a shaping clock obtained by the clock changing means and another system. Out of the other system clock delivered from
Clock relay means for selecting one corresponding to the value of the value information at the time of the trailing edge of the differential pulse and sending it as a relay clock to the subsequent transmission section, and the other data passed from the own system data signal and the other system. Of the system data signals, one corresponding to the value of the binary information is selected at the time of the trailing edge of the delayed differential pulse, and is followed by retiming with the relay clock sent by the clock relay means. Data delay means for sending as a relay data signal in the transmission section, and one of the own system frame pulse and the other system frame pulse delivered from the other system corresponding to the value of the binary information is the delayed differential pulse. Selected at the time of the trailing edge of the relay frame pulse, and while retiming with the relay clock transmitted by the clock relaying means, Frame pulse relaying means for transmitting as a reference, the applied frame configuration and the other system frame pulse as a reference, the time point at which the "condition for generating the delayed differential pulse during the empty time slot of the frame" is satisfied. A system switching circuit, comprising: a timing adjusting unit that obtains a request for reconfiguring the system to the differentiating unit at that time. 2. The system switching circuit according to claim 1, wherein the two link corresponding units include a storage unit in which single or a plurality of pieces of identification information individually indicating the empty time slots are stored, and the timing adjustment unit. Is sequentially obtained time points satisfying the conditions for the empty time slot indicated by the individual identification information stored in the storage means,
A system switching circuit characterized in that a system reconfiguration request is given to the differentiating means at these times. 3. The system switching circuit according to claim 2, wherein the two link corresponding parts are provided with identification information of a single or a plurality of empty time slots by a transmission device or a switch which opposes via a link, A system switching circuit comprising a monitoring means for sequentially storing the identification information of the above in a storage means. 4. The system switching circuit according to claim 2, wherein a line signal is multiplexed into the own system data signal and the other system data signal based on a predetermined format, and the two link corresponding parts are: A line signal received from the preceding transmission section as the own system data signal or the other system data signal based on the signal system applied to the first link and the second link and the predetermined format. A system switching circuit comprising a monitoring means for acquiring identification information of a single or a plurality of empty time slots by analyzing the above and sequentially storing the identification information in a storage means. 5. The system switching circuit according to claim 2, wherein the timing adjusting means sets a predetermined number of consecutive times of giving the system reconfiguration request to the differentiating means. A system switching circuit comprising means for limiting the number to "1" per frame.