JP2000295263A - Lan switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify and accelerate the initializing processing in a LAN switch. SOLUTION: On application of power to the LAN switch, a CPU 1 starts execution of a main program, issues an initializing command to an initializing control section 10 and issues and operation parameter and an initializing instruction to each processing program. The initializing control section 10 waits until the initializing end signal of each processing program is set, and outputs an operation start signal to each processing block when all the signals are set to instruct operation start and allows a status register to indicate the end of the initialization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a LAN switch having a plurality of communication ports and exchanging data between the ports.

[0002]

2. Description of the Related Art In general, a LAN switch has a plurality of processing blocks (often an LSI), which share functions, operate in parallel according to setting and control by software, and continuously operate between processing blocks. By exchanging data, data exchange processing of a plurality of ports is performed at high speed. Each of these processing blocks is individually initialized by software when an operation such as power-on is started, and sequentially starts operation after initialization processing is internally completed. Each of these processing blocks has a failure detection function in the data transfer interface, and monitors the presence / absence of a failure of a connection partner so that some failures do not stop the operation of the entire LAN switch.

[0003]

The state before the completion of the initialization of these processing blocks often looks like a failure state to the failure detection function. Therefore, the software
During the initialization process for the entire LAN switch, you must take steps to prevent or avoid erroneous failure detection due to the mixture of processing blocks before initialization and processing blocks that have been initialized. . The complexities of such erroneous failure detection measures and avoidance processing increase development costs. Further, such an initialization procedure using software has a disadvantage that the time required for the entire LAN switch to start operating becomes long.

An object of the present invention is to provide a LAN switch that can perform an initialization procedure easily and at high speed.

[0005]

In the LAN switch of the present invention, each of the internal processing blocks is instructed to be initialized by software, outputs an initialization completion signal when the initialization is completed, and outputs an operation start instruction signal. It has means for starting operation upon receipt, and when an initialization command is issued from the software, waits for the initialization completion signal of each processing block to be turned on, and all initialization completion signals are turned on. When it is confirmed that the process has been completed, an initialization control means for outputting an operation start signal to each processing block is provided.

The initialization of the LAN switch is speeded up by performing the initialization processing of each processing block of the LAN switch in parallel.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, an embodiment of the present invention is shown.
The LAN switch includes a CPU 1, a main memory 2, a flash memory 3, a console interface 4, a local memory 5, an initialization control unit 10, switches 20, 21, address resolution / routing processing circuits 30, 31, and MAC control circuits 51-5.
8 and physical layer circuits 61 to 68.

The flash memory 3, which is a nonvolatile storage element, stores an initialization program for the LAN switch, a main program for controlling the entire LAN switch, and operation setting information. The main memory 2 is composed of a DRAM, and the main program and operation setting information stored in the flash memory 3 are developed as a control table. The CPU 1 is a microprocessor that executes a program stored in the flash memory 3 or the main memory 2, and executes the program to initialize a LAN switch and control data exchange processing. The console interface 4 is a console connection interface control circuit for performing initial setting and maintenance of the LAN switch. The local memory 3 is a memory for temporarily storing data when the CPU 1 transmits data or receives data from a communication port. The physical layer circuits 61 to 68 control the physical interface with the Ethernet. The MAC control circuits 51 to 58 are circuits for controlling a MAC level interface with the Ethernet. The address resolution / routing processing circuit 30 analyzes the header of received data and rewrites it according to the information in the routing memory 31, passes the received data with the switching information to the switch 20, and retrieves the data sent from the switch 20. To the appropriate communication port. Information such as an output destination of received data and rewriting of a header is written in the routing memory 31 by software, and is referred to each time the address resolution / routing processing circuit 30 receives data. The address resolution / routing circuit 40 and the routing memory 41 operate similarly to the address resolution / routing circuit 30 and the routing memory 31, respectively. The switch 20 receives the received data to which the switching information is added from the address resolution / routing circuit 30 or 40, temporarily stores the received data in the memory 21,
At the same time, it outputs the data stored in the memory 21 to the address resolution / routing processing circuit 30 or 40 so as to output the data to the designated communication port in the order according to the switching information.

[0010] The initialization control unit 10 switches the address resolution and address according to a command from software.
Routing processing circuits 30, 40, MAC control circuits 51-
58, monitoring the completion of the initialization processing of the physical layer circuits 61 to 68,
And an operation start instruction, and notifies the software of the completion of initialization. The status register 11 is means for reporting the completion of initialization of all processing blocks to software.

The connection between the switch 20 and the address resolution / routing processing circuits 30 and 40 constantly monitors each other for failures. When a failure is detected, the failure is reported to software and the subsequent processing is performed. Stop passing data during that time. Data sent from the failed party is not collected, and data passed to the failed party is discarded, etc., so that the data exchange processing of the entire LAN switch does not stay due to a partial failure. Address resolution / routing processing circuit 30 and MAC control circuits 51 to 54;
Similar failure monitoring processing is performed between the routing processing circuit 40 and the MAC control circuits 55 to 58.

The switch 20, the address resolution / routing processing circuits 30, 40, the MAC control circuits 51 to 58, and the physical layer circuits 61 to 68 (hereinafter collectively referred to as processing blocks) are each initialized by software as initialization processing. The operation parameters are given by the conversion instruction, and the internal state is set. When the power is turned on, for example, each processing block receives an initialization instruction from software, and after performing internal initialization processing, enters an operable state. When the operation is started, each processing block also starts the above-described failure monitoring processing.

FIG. 2 shows signals transmitted and received between each processing block and the ICNT 10.

Here, switch 2 of the processing blocks
0, address resolution / routing processing circuits 30, 40,
Although only the MAC 51 is shown, the same applies to other processing blocks. Signals BRDY20, BRDY30, BR indicating completion of initialization from the switch 20, the address resolution / routing processing circuits 30, 40, and the MAC control circuit 51 to the initialization control unit 10.
There are DY40 and BRDY51. Also, from the initialization control unit 10 to the switch 20, the address resolution / routing processing circuit 3
0, 40, and signals BSTTA20, BSTA30, BSTA40, and BSTA51 indicating an operation start instruction to the MAC control circuit 51.

FIG. 3 shows the connection relationship between each processing block and the ICNT 10 and the timing of the signal.

In an initial state such as immediately after power-on, the signal BSTA
20, BSTA30, BSTA40, BSTA51 and BRDY20,
BRDY30, BRDY40, and BRDY51 are all off.

The operation of the present embodiment will be described with reference to FIGS.

The processing when the power of the LAN switch is turned on from off to start operation will be described. Immediately after the power is turned on, each circuit in the LAN switch is reset to an initial state. The CPU 1 executes an initial program in the flash memory 3, initializes the main memory 2, the control interface 4, and the local memory 5,
Is expanded in the main memory 2 and the main program is switched to the main program. The CPU 1 starts executing the main program, first issues an initialization monitoring command to the initialization control unit 10, and subsequently issues an initialization instruction to each processing block together with an operation parameter. After instructing all the processing blocks to be initialized, the software monitors the status register 11 of the initialization control unit 10 and confirms that all the processing blocks have been initialized. When the initialization of all the processing blocks is completed in the status register 11 of the initialization control unit 10, the LAN switch is in the operation start state,
Data can be exchanged between a plurality of communication ports.

The operation of the initialization control unit 10 and each processing block during the above initialization processing will be described with reference to the timing chart of FIG. In the initial state, the initialization control unit 10 operates the operation start instruction signals BSTA20, BSTA30, BSTA4 for each processing block.
0, BSTA 51 is off. When an initialization command is issued from software, the initialization control unit 10 initializes the processing completion signals BRDY20, BRDY30, BRDY4 of each processing block.
0, wait for BRDY 51 to turn on. Each processing block is instructed to be initialized by software, and when the internal initialization is completed, initialization completion signals BRDY20, BRDY30, BRDY30,
Turn on BRDY40 and BRDY51. The initialization control unit 10 initializes the completion signals BRDY20, BRDY30, BRDY40, BRDY5.
1 When it is confirmed that all are turned on, the operation start signal BS
TA20, BSTA30, BSTA40, and BSTA51 are turned on at the same time to instruct each processing block to start operation at the same time, and the status register 11 displays the completion of initialization.

As described above, there is no particular limitation or condition on the order of initialization of each processing block from software, and the completion of initialization of each processing block is confirmed after issuing the initialization instruction. No need, it's simple. Further, the initialization processing of each processing block can be executed in parallel.

[0021]

As described above, according to the present invention, the initialization processing of the software is simple, the complicated control of the failure detection function during the initialization processing is not required, and the development man-hour is small. Further, by performing the initialization processing of each processing block in parallel, the initialization time of the entire LAN switch can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a LAN switch according to an embodiment of the present invention.

FIG. 2 is a diagram showing signals between an initialization control unit 10 and each processing block.

FIG. 3 is a timing chart showing the operation of the LAN switch of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Main memory 3 Flash memory 4 Console interface 5 Local memory 10 Initialization control unit 11 Status register 20 Switch 21 Memory 30, 40 Address resolution / routing processing circuit 31, 41 Routing memory 51-58 MAC control circuit 61-68 Physical Layer circuit BSTA 20, 30, 40, 51 Operation start signal BRDY 20, 30, 40, 51 Initialization completion signal

Claims (3)

[Claims] In a LAN switch having a plurality of communication ports and exchanging data between the ports, each internal processing block is instructed to initialize by software, and when the initialization is completed, an initialization completion signal is transmitted. Output, and when receiving the operation start instruction signal, has means for starting the operation,
Further, when an initialization command is issued from the software, the process waits for the initialization completion signal of each processing block to be turned on, and confirms that all initialization completion signals have been turned on. A LAN switch having initialization control means for outputting an operation start signal to the LAN switch. 2. When all initialization completion signals are turned on,
2. The LAN switch according to claim 1, further comprising means for notifying the software of completion of initialization. 3. A physical layer circuit for controlling a physical interface with Ethernet, and a MAC for controlling a MAC level interface with the Ethernet.
A control circuit, a switch that receives the received information to which the switching information is added, temporarily stores the information in a memory, and outputs the data stored in the memory; and performs header analysis and rewriting of the received data to perform switching information. 3. The LAN switch according to claim 1, further comprising: an address resolution / routing processing circuit that passes the received data to which the data is added to the switch, and that receives the data output from the switch and transmits the data to an appropriate communication port.