JP2000294736A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a technology for reducing the power consumption and the noise of a semiconductor integrated circuit device when no high-speed operation is required. SOLUTION: A semiconductor integrated circuit device is provided with detecting means R12-R16 for detecting a clamping voltage supplied to an internal module, a comparing means 52 which compares the detected results of the detecting means R12-R16 with a reference voltage, and a transistor Q30 which adjusts the level of the clamping voltage based on the compared results of the comparing means 52. The integrated circuit is also provided with a clamping circuit incorporating an external terminal connected to the output node of the clamping voltage. The integrated circuit forms a prescribed clamping voltage supplied to the internal module by clamping a voltage supplied from the outside. Therefore, the power consumption and noise of the integrated circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
Further, the present invention relates to a technology for reducing noise in the technology, for example, a technology effective when applied to a single-chip microcomputer (hereinafter simply referred to as a “microcomputer”).

[0002]

2. Description of the Related Art A microcomputer, which is an example of a semiconductor integrated circuit, has a port for input / output control of various signals, a central processing unit (CPU) for performing arithmetic processing according to a predetermined program, and a CPU. Random access memory (RAM) that enables random access, serial communication interface (SC) that enables serial communication with the outside of the chip
I), an A / D converter or a D / A converter for performing conversion between an analog signal and a digital signal, and a bus controller for determining bus specifications such as a bus width of an address space and the number of access states. BUSC), a read-only memory (ROM) for reading only, a timer (TMR) for time measurement, a clock pulse generator (CPG) 39 for supplying a clock signal to an internal module of the chip, Various modules such as an interrupt controller (INT) for performing interrupt control for an interrupt request are provided.

As an example of a document describing a microcomputer, there is a "Microcomputer Handbook (pp. 157-)" issued by Ohm Co., Ltd. on December 25, 1985.

[0004]

In a semiconductor integrated circuit such as the microcomputer described above, the ability to process a large amount of information at high speed is required. However, when the drive capability of the transistor is increased to realize high-speed operation, power consumption increases, and noise radiated from the semiconductor integrated circuit tends to increase. Further, it has been found by the present inventor that in a microcomputer application system, when high-speed operation of the microcomputer is not required, the drive capability of the transistor becomes excessive.

An object of the present invention is to provide a technique for reducing power consumption and noise of a semiconductor integrated circuit when high-speed operation is not required.

Another object of the present invention is to provide a technique for selectively realizing a noise reduction mode and a high-speed operation mode.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, detecting means (R12 to R1) for detecting the clamp voltage supplied to the internal module.
6) a comparing means (52) for comparing the detection result of the detecting means with a reference voltage; a transistor (Q30) for adjusting the clamp voltage level based on the comparison result of the comparing means; And a clamp circuit including an external terminal that conducts to an output node of the clamp voltage.

According to the above means, the clamp circuit comprises:
An external supply voltage supplied from outside is clamped to form a predetermined clamp voltage supplied to the internal module. This achieves low power consumption and low noise. The transistor adjusts the clamp voltage level based on a comparison result of the comparison means. When an external supply voltage is applied to an external terminal conducting to the output node of the clamp voltage, the clamp voltage level is adjusted based on the comparison result of the comparison means, and the output voltage of the clamp circuit becomes the external supply voltage level. Is supplied to the internal module at a level advantageous for high-speed operation. This selectively realizes the noise reduction mode and the high-speed operation mode.

The detecting means can be easily constituted by a plurality of resistors connected in series to each other.

Further, the control circuit changes the voltage dividing ratio by the plurality of resistors according to the control signal. This allows adjustment of the clamp voltage level. At this time, a register for setting the logic of the control signal or a mask ROM rewriting layer selection circuit for setting the logic of the control signal can be provided.

[0012]

FIG. 2 shows a microcomputer as an example of a semiconductor integrated circuit according to the present invention.

A microcomputer 10 shown in FIG.
Although 0 is not particularly limited, it is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

A microcomputer 10 shown in FIG.
0 is the clamp voltage (VC
L) includes a supply block and an external voltage (Vcc) supply block surrounding the supply block. The clamp voltage supply block has a clamp voltage VCL as an operating voltage.
Is supplied to the external voltage supply block, and an external voltage Vcc is supplied as an operation voltage.

A plurality of internal modules each having a predetermined function are arranged in the clamp voltage supply block. Port (POR) for input / output control of various signals
T) 25 to 28, a system controller (SYSC) 31 for controlling various operation modes (such as a normal operation mode and a low power consumption mode), and a central processing unit (CPU) 32 for performing arithmetic processing according to a predetermined program. ,
A random access memory (RAM) 33 which can be randomly accessed by the CPU 32, a serial communication interface (SCI) 34 which enables serial communication with the outside of the chip, and a converter for converting between an analog signal and a digital signal. A / D converter and D / A converter 35, a bus controller (BUSC) 36 for determining bus specifications such as a bus width of an address space and the number of access states, a read-only memory (ROM) for reading only 37, a timer (TMR) 38 for measuring time, a clock pulse generator (CPG) 39 for supplying a clock signal to a module inside the chip, and an interrupt controller (IC) for controlling an interrupt request for an interrupt request from outside the chip I
NT) 40.

The external voltage supply block is provided with level shifters 21 to 24 for converting various signals of the clamp voltage VCL level from the clamp voltage supply block to the external supply voltage Vcc level, and an external voltage supplied via a Vcc terminal. The clamp voltage V is determined based on the supply voltage Vcc.
It includes a clamp circuit 45 for forming CL, and input / output buffers 41 to 44 for interfacing with the outside of the chip.

The operation of the clamp circuit 45 is controlled by a control signal from the system controller 31. Further, a VCLMON terminal is provided, and the clamp circuit 4 is provided.
5 can be monitored.

FIG. 1 shows a configuration example of the clamp circuit 45.

A reference voltage generating circuit 51 for generating a reference voltage, a plurality of resistors R12 to R15 forming detection means for detecting a clamp voltage, and a resistor R12
An operational amplifier (abbreviated as “op-amp”) 52 as a comparing means for comparing the detection result obtained through R15 with the reference voltage, and a p for adjusting the clamp voltage level based on the comparison result of the op-amp 52.
A channel type MOS transistor Q30 is provided.

P-channel type MOS transistor Q30
Is applied with an external supply voltage Vcc. p
The drain electrode of the channel type MOS transistor Q30 is connected to a clamp voltage supply block or a p-channel type MOS transistor.
Coupled to the source electrodes of transistors Q16-Q19. P-channel type MOS transistors Q16 to Q19
Are connected to the resistors R12 to R12 connected in series with each other.
It is connected to each node of R16. p-channel type M
The OS transistors Q16 to Q19 are selectively turned on by the control circuit 66. The potential of the series connection node of the resistors R15 and R16 is fed back to the inverting input terminal of the operational amplifier 52 as a clamp voltage detection result. Thereby, in the operational amplifier 52, the clamp voltage detection result is compared with the reference voltage, and the p-channel MOS transistor Q30 is controlled based on the comparison result, thereby stabilizing the clamp voltage VCL at the node N11. Can be The node N11 is connected to the clamp voltage VCL
, And is conducted to the VCLMON terminal.
By providing the VCLMON terminal, the clamp voltage can be monitored from outside the chip. Also,
By externally connecting the capacitor C17 to the VCLMON terminal, the operation of the operational amplifier 52 can be stabilized.

A bias circuit 50 for supplying a bias voltage to the operational amplifier 52 is provided.

The clamp circuit 45 includes control signals SIG20 to SIG output from the system controller 31.
The operation is controlled by 22. An inverter 63 for inverting the logic of the control signal SIG20 is provided, and the control signal SIG20 is supplied to each unit via the inverter 63.

The detailed configuration of each unit will be described.

The operational amplifier 52 is configured as follows.

Depletion type n-channel type MO
The S transistor Q22 and the depletion type n-channel MOS transistor Q26 are differentially coupled. The non-inverting input terminal of the operational amplifier 52 is drawn from the gate electrode of the n-channel MOS transistor Q22. The reference voltage generated by the reference voltage generation circuit 51 is supplied to the non-inverting input terminal. The inverting input terminal of this operational amplifier is drawn out from the gate electrode of the n-channel MOS transistor Q26. The potential of the series connection node of the resistors R15 and R16 is supplied to this inverting input terminal. The source electrodes of the n-channel MOS transistors Q22 and Q26 are
It is coupled to ground GND via OS transistor Q23. The n-channel MOS transistor Q23 is
By being biased by the bias voltage output from the bias circuit 50, it functions as a constant current source. n
The external supply voltage Vcc is supplied to the drain electrode of the channel type MOS transistor Q22 via the p-channel type MOS transistor Q24. n-channel type M
An external supply voltage Vcc is supplied to a drain electrode of the OS transistor Q26 via a p-channel MOS transistor Q25 mirror-coupled to the p-channel MOS transistor Q24. p-channel type MOS
A differential output signal is obtained from the series connection of the transistors Q25 and Q26. This differential output signal is output via the subsequent-stage p-channel MOS transistor Q28.
An external supply voltage Vcc is applied to a source electrode of the p-channel MOS transistor Q28. The drain electrode of the p-channel MOS transistor Q28 is connected to the ground GN via the n-channel MOS transistor Q29.
D. n-channel MOS transistor Q
29 functions as a constant current source by being biased by the bias voltage output from the bias circuit 50. A p-channel MOS transistor Q27 is provided for fixing the p-channel MOS transistor Q28 to the off state when the operation of the operational amplifier 52 is stopped. This p-channel type M
The control signal SIG20 is transmitted to the gate electrode of the OS transistor Q27 via the inverters 63 and 65. When the control signal SIG20 is at the low level, the p-channel MOS transistor Q27 is turned on, and the gate electrode of the p-channel MOS transistor Q28 is fixed at the high level. An n-channel MOS transistor Q31 is provided between the gate electrode of the p-channel MOS transistor Q30 and the ground. When the control signal SIG20 is at a low level, the n-channel MOS transistor Q31 is turned on. As a result, the gate electrode of the p-channel MOS transistor Q30 is fixed at a low level.

The control circuit 66 is configured as follows.

The three-input NAND gates 53, 55, 57,
60 are provided. The NAND gate 53 is connected to the inverter 6
The NAND logic of the control signal SIG20 transmitted through the control signals 3 and 64 and the control signals SIG21 and SIG22 is obtained.
This NAND logic is a p-channel MOS transistor Q
It is transmitted to 16 gate electrodes. An inverter 54 for inverting the logic of the control signal SIG21 is provided. The NAND gate 55 obtains a NAND logic of the output signal of the inverter 54, the output signal of the inverter 64, and the control signal SIG22. This NAND logic is a p-channel type MO
The signal is transmitted to the gate electrode of S transistor Q17. Inverter 58 for inverting the logic of control signal SIG21
And an inverter 59 for inverting the logic of the control signal SIG22. The NAND gate 60 obtains the NAND logic of each output signal of the inverters 58, 59, 64. This NAND logic is transmitted to the gate electrode of p-channel MOS transistor Q19.

The bias circuit 50 is configured as follows.

Depletion type n-channel type MO
S transistors Q1 and Q2 are connected in series, and p
A channel type MOS transistor Q3 is connected in series. An n-channel MOS transistor Q6 is connected in series to the p-channel MOS transistor Q5. The p-channel type MOS transistor Q3 has a p-channel type M
The OS transistor Q5 is mirror-coupled, and the n-channel MOS transistor Q2 is mirror-coupled to the n-channel MOS transistor Q6. p-channel type MO
The external supply voltage V is applied to the source electrodes of the S transistors Q3 and Q5 via the p-channel MOS transistor Q4.
cc is supplied. The control signal SIG20 is transmitted to the gate electrode of the p-channel MOS transistor Q4 via the inverter 63.

The reference voltage generating circuit 51 is configured as follows.

P-channel type MOS transistor Q1
2, n-channel type MOS transistors Q11, Q1
0 and Q8 are connected in series. The n-channel type MOS transistors Q10 and Q11 are of a depletion type. p-channel type MOS transistors Q12, Q13
Is applied with an external supply voltage Vcc. p
Channel MOS transistor Q13 is mirror-coupled to p-channel MOS transistor Q12, and n-channel MOS transistor Q11 is mirror-coupled to n-channel MOS transistor Q14. An output node N2 of the reference voltage generation circuit 51 is drawn out from a series connection of the p-channel MOS transistor Q13 and the n-channel MOS transistor Q14. This output node N2 is provided with a p-channel MOS transistor Q15 for supplying external supply voltage Vcc. This p-channel type MOS transistor Q
15. The control signal SIG20 is applied to the gate electrodes of the n-channel MOS transistors Q8 and Q9 so that the control signal SIG20 can be controlled by the control signal SIG20.
3, 66.

Next, the operation will be described.

FIG. 3 shows an operation mode truth table.

As shown in FIG. 3, the control signal SIG2
When 0 is at the low (0) level, the operation mode is the low power consumption mode. When the output logic of the inverter 63 is set to the high level, the n-channel MOS transistor Q7 is turned on. MO
When the S transistors Q23 and Q29 are turned off, the operation of the operational amplifier 52 is stopped (OFF). That is,
In this mode, no clamping operation is performed. Therefore, the external supply voltage Vcc is applied to each module in the clamp voltage supply block. When the control signal SIG20 is at the low level, in the operational amplifier 52, the p-channel MOS transistor Q27 is turned on, and the gate electrode of the p-channel MOS transistor Q28 is fixed at the high level. As described above, when the control signal SIG20 is at the low (0) level, the operation of the circuit having the through current path (the bias circuit 50, the reference voltage generation circuit 51, and the operational amplifier 52) is stopped, so that the current consumption is reduced. Is achieved.

When the control signal SIG20 is at the high (1) level, the normal operation mode is set, and the bias circuit 50, the reference voltage generation circuit 51, and the operational amplifier 52 operate (O).
N) state. The n-channel MOS transistor Q31 is turned off, and the p-channel MOS transistor Q31 is turned off.
Transistor Q30 is turned on.

FIG. 4 shows a clamp voltage control truth table.

When the control signal SIG20 is at a high level, the control signal SIG22 is at a low level and the control signal S
When IG21 is at a low level, p-channel MOS transistor Q19 is selectively turned on. At this time, V
The voltage of the CLMON terminal is the voltage of the node N2 × (R15
+ R16) / R16.

When the control signal SIG20 is at a high level, the control signal SIG22 is at a low level and the control signal S
When IG21 is at a high level, p-channel MOS transistor Q18 is selectively turned on. At this time, V
The voltage of the CLMON terminal is the voltage of the node N2 × (R14
+ R15 + R16) / R16, which is slightly higher than when the p-channel MOS transistor Q19 is selectively turned on.

When the control signal SIG20 is at a high level, the control signal SIG22 is at a high level and the control signal S
When IG21 is at a low level, p-channel MOS transistor Q17 is turned on. At this time, VCLMO
The voltage of the N terminal is the voltage of the node N2 × (R13 + R14
+ R15 + R16) / R16, which is slightly higher than when the p-channel MOS transistor Q18 is selectively turned on.

When the control signal SIG20 is at a high level, the control signal SIG22 is at a high level and the control signal S
When IG21 is at high level, p-channel MOS transistor Q16 is turned on. At this time, VCLMO
The voltage of the N terminal is the voltage of the node N2 × (R12 + R13
+ R14 + R15 + R16) / R16.
This is slightly higher than when the channel type MOS transistor Q17 is selectively turned on.

As described above, the control signals SIG22, SIG
VCL by changing the combination of logics
The voltage of the MON terminal, that is, the clamp voltage can be changed.

The control signals SIG21 and SIG22 are set in registers (not shown). Therefore, by rewriting this register, the control signal SI
The user can appropriately change the logic of G21 and SIG22 as needed.

FIG. 5 shows an output voltage characteristic diagram of the clamp circuit 45.

For example, when the control signal SIG22 is at a low level and the control signal SIG21 is at a low level while the control signal SIG20 is at a high level, the p-channel type M
OS transistor Q19 is selectively turned on, and VCLM
The voltage of the ON terminal is the voltage of the node N2 × (R15 + R1
6) This level is represented by / R16, and is made substantially constant by feedback control regardless of the load fluctuation in the clamp voltage supply block (L2).

On the other hand, outside the chip, the power supply 70 for obtaining the external supply voltage Vcc is set to VCLMON.
A switch SW that can be coupled to the terminal is provided, and this switch S
When W is turned on and the external supply voltage Vcc is supplied to the node 11 via the VCLMON terminal, the level is detected by the resistors R12 to R16, transmitted to the operational amplifier 52 and feedback-controlled, and The voltage level of N11 is equal to the external supply voltage Vcc.
(L1). Therefore, in a system in which this microcomputer is mounted, a high-speed operation mode in which high-speed processing is prioritized and a noise reduction mode can be easily realized. That is, in a system in which the microcomputer 100 is mounted, the VCL
By coupling the MON terminal and the power supply 70, a mode in which processing speed is prioritized is realized, and by releasing the coupling between the VCLMON terminal and the Vcc terminal, a noise reduction mode can be realized.

According to the above-described example, the following effects can be obtained.

(1) The provision of the clamp circuit 45 clamps an externally supplied voltage supplied from the outside and forms a predetermined clamp voltage supplied to the internal module, thereby achieving low power consumption. As a result, noise reduction is achieved. The clamp voltage level is adjusted by the p-channel MOS transistor Q30, so that the clamp voltage VCL is stabilized. In addition, V is conducted to the output node of the clamp voltage.
When the external supply voltage Vcc is applied to the CLMON terminal,
Since the clamp voltage level is adjusted based on the comparison result of the comparison means, the output voltage of the clamp circuit becomes equal to the external supply voltage level, and a voltage at a level advantageous for high-speed operation is supplied to the internal module. You. For this reason, outside the semiconductor integrated circuit, it is possible to switch between the noise reduction mode and the high-speed operation mode in which high-speed processing is prioritized.

(2) A plurality of resistors R connected in series to each other
It can be easily configured by 12 to R16. At this time, by providing a control circuit 66 for changing the voltage division ratio by the plurality of resistors according to the control signal,
Adjustment of the clamp voltage level is enabled.

(3) In a low power consumption mode such as a standby mode, noise is originally small. Therefore, as shown in FIG. 3, the control signal SIG20 is set to low level to stop the operation of the through current path and perform clamping. Not to be. Since no through current flows, this is advantageous in reducing power consumption.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, in the above example, the control signal SIG2
1 and SIG22 are respectively set in registers (not shown), but the clamp voltage value may be changed by a mask ROM rewriting layer.

For example, in the clamp circuit shown in FIG. 1, the mask ROM rewriting layer selecting circuit 7 shown in FIG.
1 is provided. This mask ROM rewriting layer selection circuit 71
The output signal from the output node N31 is supplied to the control signals SIG21 and SIG2 in the clamp circuit shown in FIG.
2 is supplied to each part.

In the mask ROM, the threshold value of the MOS transistor is changed depending on whether or not an implantation is performed in the rewriting layer process. Here, when you hit the implant,
It is assumed that the threshold value is high.

The mask ROM rewriting layer selection circuit 71
It is configured as follows.

P-channel type MOS transistor Q4
0, n channel type MOS transistors Q41, Q42
Are connected in series. The control signal SIG23 is input to the gate electrode of the p-channel MOS transistor Q40. Further, the n-channel type MOS transistor Q41,
An external supply voltage Vcc is applied to the gate electrode of Q42. A p-channel MOS transistor Q43 and an n-channel MOS transistor Q44 are connected in series. Inverter 72 for inverting the logic of node N29 connected in series between p-channel MOS transistor Q43 and n-channel MOS transistor Q44 is provided, and inverter 73 for inverting the logic of output node N30 of inverter 72 is provided. Can be The logic of the node N30 is a p-channel MOS transistor Q
The signal is transmitted to the gate electrode 43. The control signal S is applied to the gate electrode of the n-channel type MOS transistor Q44.
IG23 is transmitted.

Since the present circuit has a through current path, the control signal 23 is set to the high level (Vcc level) in the low power consumption mode, and in this case, the output node N31 is set to the low level.

N-channel type MOS transistor Q4
An implant is applied to any one of Q1 and Q42 in the mask ROM rewriting layer process.

For example, when implantation is performed on the n-channel MOS transistor Q41, the threshold value becomes high, so that almost no current flows in the n-channel MOS transistor Q41. Therefore, the node N29 goes low, the node N30 goes high, and the output node N31 goes low.

On the other hand, when implantation is performed on n-channel MOS transistor Q42, almost no current flows through n-channel MOS transistor Q42, and the level of node N29 changes from Vcc level to n-channel MOS transistor Q42. It is equal to the value obtained by subtracting the threshold value of the transistor Q41. Although the node N29 has an intermediate potential, by setting the VLT (logic threshold) of the inverter 72 low, the node N30
Goes low, p-channel MOS transistor Q43 is turned on, and node N29 is pulled up to the Vcc level. At this time, the output node N31 is at a high level.

In the case of general-purpose products, since the operating frequency differs depending on the customer, it is necessary to perform testing with all clamp voltages that can be selected by a register. However, mask RO
Since the M version is for a specific customer and has a clear operating frequency, it is sufficient to apply only the desired clamp voltage by applying the circuit shown in FIG.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is the field of application as the background has been described. However, the present invention is not limited to this, and various types of semiconductor integrated circuits can be used. It can be widely applied to circuits.

The present invention can be applied on condition that an internal module having at least a predetermined function is provided.

[0063]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by clamping the external supply voltage supplied from the outside and forming a predetermined clamp voltage supplied to the internal module, low power consumption and low noise are achieved. . By adjusting the clamp voltage level based on the comparison result of the comparison means, the stabilization of the clamp voltage is achieved. When an external supply voltage is applied to an external terminal conducting to the output node of the clamp voltage, the clamp voltage level is adjusted based on the comparison result of the comparison means, so that the output voltage of the clamp circuit is Since the voltage becomes equal to the external supply voltage level and is supplied to the internal module at a level advantageous for high-speed operation, the noise reduction mode and the high-speed operation mode can be selectively realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a clamp circuit included in a microcomputer that is an example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram illustrating an overall configuration example of the microcomputer.

FIG. 3 is an explanatory diagram of an operation mode truth value table of the clamp circuit.

FIG. 4 is an explanatory diagram of a voltage control truth table of the clamp circuit.

FIG. 5 is an output voltage characteristic diagram of the clamp circuit.

FIG. 6 is a circuit diagram of a main part in another configuration example of the clamp circuit.

[Explanation of symbols]

 45 clamp circuit 50 bias circuit 51 reference voltage generating circuit 52 operational amplifier 66 control circuit 100 microcomputer Q30 p-channel MOS transistor

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Masaru Iwabuchi 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5F038 AV06 AV18 BB01 BB05 BB08 BG06 DF04 DF08 EZ20 5F064 BB05 BB07 BB09 BB10 BB13 BB15 BB18 BB24 BB27 BB28 BB33 CC09 CC22 FF04 FF46

Claims (5)

[Claims] An internal module having a predetermined function;
A clamp circuit for clamping a voltage supplied from the outside to form a clamp voltage supplied to the internal module, wherein the clamp circuit detects a clamp voltage. A comparing means for comparing the detection result of the detecting means with a reference voltage; a transistor for adjusting the clamp voltage level based on the comparison result of the comparing means; A semiconductor integrated circuit, comprising: 2. The semiconductor integrated circuit according to claim 1, wherein said detecting means includes a plurality of resistors connected in series to each other. 3. The semiconductor integrated circuit according to claim 2, further comprising a control circuit for changing a voltage dividing ratio by said plurality of resistors according to a control signal. 4. The semiconductor integrated circuit according to claim 3, further comprising a register for setting a logic of said control signal. 5. The semiconductor integrated circuit according to claim 3, further comprising a mask ROM rewriting layer selection circuit for setting a logic of said control signal.