JP2000286722A - Interleaver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the hardware scale in comparison with a memory configuration and to enhance the processing speed by configuring an interleaver with (N+1) sets of counters and N sets of adders, where N is number of stages by the MIL method, without the need for many number of memories. SOLUTION: This interleaver is provided with an address generating section consisting of counters 12, 13, 16, 19 that can set counts 14, 17, 20 and offsets 15, 18, 21 of count-up without the need for a plurality of memory areas and of adders 22, 23, 24 summing outputs of the counters to allow a memory 11 to provide an output of data bits according to a generated address, and the interleaver obtains an interleave output where data units being divisions of transmission data are rearranged according to prescribed rules.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-stage interleave method (MIL method: Multi-s) for improving the effect of correcting a communication error in a transmission / reception section of a radio communication device.
The present invention relates to a channel interleaver using a tag interleave method.

[0002]

2. Description of the Related Art In data communication, when an error occurs during transmission, an error correction process is performed to correct data of the error portion by using neighboring normally received data. However, such an error correction process is effective for a random error in which an error occurs in a discrete portion of data, but is effective for a burst error in which errors are concentrated in a large portion of the data. The correction effect is extremely reduced.

[0003] Conventionally, a technique has been used in which transmission data is divided into a plurality of data units by an interleaver, and these data units are rearranged according to a predetermined rule and transmitted. As a result, even if a burst error occurs, if the data unit is returned in the original data, the error portion in the data is dispersed like a random error, and the error can be corrected effectively. As a configuration of the interleaver, a MIL method for rearranging data units in a plurality of stages is known, and an interleave using the MIL method will be described below.

FIG. 4 shows an example in which the input data is 11
An outline of interleaving by a three-stage in the case of 51 bits is shown. First, in the first stage, (72 × 16) block interleaving is performed on input data, and in the second stage, (9 × 8) block interleaving is performed for each column of the first stage. In the stage, (3 × 3) block interleaving is performed for each column of the second stage. Thus, the final interleaved output is (0,384,768,128).
..), And a sufficient inter-symbol distance (that is, an interval between data bits) is obtained, so that the effect of randomizing burst errors in a communication line improves the error correction effect on the receiving side.

Conventionally, such an interleave process using the MIL method has been performed as shown in FIG.
In the interleaver using the MIL method, since a final output is obtained by performing the block interleaving a plurality of times as described above, a plurality of memory areas 2 to 4 are prepared as shown in FIG. The interleaving is performed by repeating writing and reading for the number of stages. Specifically, the input data (transmitted data) before interleaving is written into the memory 1, the data read from the memory 1 is written into the memory area 2 of the first stage, and the data is read out from the memory area 2 of the first stage for each column. Writing data to the memory area 3 of the second stage,
The data read for each column from the memory area 3 of the second stage is written to the memory area 4 of the third stage, and the data read for each column from the memory area 4 of the third stage is written to the output data memory 5.

Here, since the interleave pattern is determined from the channel type and transmission rate of the input data,
The memory area of each stage is divided according to the pattern for the data to be interleaved. Then, data is read from the head of the input data memory 1 and data is written from the head of each area divided into the memory area 2 of the first stage. In this example, each bit of data is written into each area of the memory area 2, that is, the original data is divided into bits and rearranged to some extent. Then, the same operation is performed for each of the areas divided up to the third stage, and all data is finally written in the output data memory 5. By performing the above operation, an output after interleaving is obtained.

[0007]

In the above-mentioned conventional interleaver, since interleaving is performed by reading and writing of memories, reading and writing operations between memories corresponding to the number of stages are required, and at least the interleaving is required as a memory area. Requires a memory area twice as many as the number of data to be read, and the processing speed is slow due to read and write operations to the memory. Also, in channel interleaving, the number of interleaved bits usually differs depending on the channel type and data transmission rate. Therefore, in the MIL method, the number of interleaving stages and the depth of each block interleave differ. When channels with different interleaving parameters are performed by the same interleaver, there is a problem in that control of the control becomes very complicated because the division of the memory area needs to be changed according to the parameters.

The present invention has been made in view of the above-mentioned conventional circumstances, and has as its object to reduce the number of memories used in the MIL method and to solve the above-mentioned problems.

[0009]

In an interleaver applied to the MIL method according to the present invention, a counter capable of setting a counter value and a count-up offset value as parameters without using a plurality of memory areas, and an output of each counter. The provision of the address generation unit constituted by the adder for adding reduces the hardware scale and realizes interleaving of different channels with the same hardware.

More specifically, the interleaver applied to the MIL method according to the present invention is an interleaver for rearranging data units obtained by dividing transmission data according to a predetermined rule by a multi-stage interleave method. And a read address generation unit that generates a read address of the data stored in the memory. As the data unit, a bit unit of the transmission data, a data block unit obtained by dividing the transmission data into blocks, and the like are used.

The read address generation unit includes a counter N that outputs the carry-out of the interleave length of the final stage N as a counter value, and a count value setting register for the counter N that sets the counter value of the counter N as a parameter. A counter N offset setting register for setting an offset value added by one count of the counter N as a parameter, and an interleave length of the N-1 stage as a counter value, and counting up by a carry-out output of the final stage N. A counter N-1 for outputting the carry-out, and a counter N
A counter value setting register for the counter N-1 for setting a counter value of -1 as a parameter, an offset setting register for the counter N-1 for setting an offset value added by one count of the counter N-1 as a parameter, And an adder for adding a counter output for each stage and outputting a read address. The number of counters is equal to the number of stages of the multi-stage interleaving method to be applied and connected in a stepwise manner.

As described above, the interleaver according to the present invention using the address generating section constituted by the counter and the adder for adding the output of each counter has the following regularity in the interleave output to which the MIL is applied. It was invented by paying attention to a certain point. FIG. 3 shows the interleaved bit number of 1151 bits, the interleaved output of the first stage (72 × 16), the second stage (9 × 8), and the third stage (3 × 3). ,
The data bits are divided into three by (3 × 3) in the third stage, each has an offset of 384 between the data bits, and when the three data bits are considered as a set,
Each adjacent pair has 1 between the first data bits of the pair.
28 each. Further, when three sets of nine data bits are considered as one set, 16 bits are set between the first data bits.
With an offset of By focusing on such regularity, MIL can be performed without using a large number of memories as in the related art.
Interleaving by the method is realized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An interleaver according to an embodiment of the present invention has a number of interleaved bits of 1151 bits, a first stage (72.times.16), and a second stage (9.times.16).
8), the case of the third stage (3 × 3) will be described as an example. FIG. 1 shows the configuration of an interleaver according to the present embodiment. Reference numeral 11 denotes a memory that stores input data before interleaving, 12 denotes a counter that counts a row of interleaving in the first stage, and a counter 13 that will be described later. This is a counter that operates using the carry-out output as a clock.

Reference numeral 13 denotes a counter for counting the interleaving columns of the second stage.
The count-up is performed using the carry-out output of No. 6 as a clock. The carry-out output of the counter 13 is input to the clock of the counter 12. 14 is a count value setting register for setting the counter value of the counter 13,
Reference numeral 15 denotes an offset register for setting a count-up value for one count of the counter 13.

Counters 16 and 19 count the columns and rows of the interleaver in the final stage, respectively.
Reference numerals 7 and 20 denote count value setting registers of the counters 16 and 19, respectively.
6 and 19 are offset setting registers. 22, 2
Reference numerals 3 and 24 denote adders for adding the outputs of the respective counters. The output of the adder 24 at the final stage becomes the read address value from the memory 11, and the read data bit string becomes the interleaved data.

Next, a case where the interleaver having the above configuration is applied to the example of interleaving of the 1151-bit data shown in FIG. 3 by the MIL method will be described with reference to FIG.
FIG. 2 shows only the configuration of the address generator of the interleaver, and the interleave of each stage is (7
2 × 16), (9 × 8), and (3 × 3). First, as initialization, the counter 12 is set to “16”, which is the number of interleaving columns in the first stage.
From each of the count value setting registers 14 and 17,
The number of columns in the second and third stages is “8” and “3” in 3, 16
Is set as the count value. For the counter 19, the number of rows of the third stage "3" is set as a count value from the register 20. Further, as initialization, an offset value to be added by one count of each of the counters 13, 16, and 19 is set from each of the offset setting registers 15, 18, and 21.

By the above initial setting, the counter 12 is a hexadecimal counter that counts up by (+1), the counter 13 is an (+16) octal counter, the counter 16 is a (+128) ternary counter, and the counter 19 is (+38).
4) is the ternary counter. Since the parameters of the count value and the offset value of each counter can be calculated in advance from the MIL interleave pattern, the settings can be changed according to the channel type and the data transmission rate.

After the initialization of each counter, when the storage of all transmission data in the input data storage memory 11 is completed,
Start interleave operation. At the start of the operation, the values of the respective counters are all "0", the output from the adder 24 is "0", the read address from the memory 11 is "0", and the 0th bit of the input data is the memory 11 Output from Next, the counter 19 counts up by the clock input, and the output of the counter 19 becomes “38”.
4 ". The other counters do not operate at this stage because they carry out the counter operation using the carry-out output of the preceding counter as a clock. Therefore, the output from the adder 24 (that is, the read address) is" 384 ". ,
The 384th data bit of the input data is output from the memory 11.

Similarly, in the next cycle by the clock input, "768" is output only from the counter 19,
The 768th data bit is output from the memory 11. Next, when the ternary counter 19 returns to “0”,
The carry-out is output from the counter 19 to the counter 16, and the counter 16 operates using the clock as a clock, so that the output is "128". Since the other counter outputs are “0”, the output address from the adder 24 is “128”, and the 128th data bit is output from the memory 11.

Similarly, every time the clock input cycle advances, "128 (output of counter 16) +384 (output of counter 19) = 512", "128 (counter 1
6 output) +768 (counter 19 output) = 89
6 "," 256 (output of counter 16) "," 256
(Output of counter 16) +384 (output of counter 19) = 640 "," 256 (output of counter 16) +7
68 (output of counter 19) = 1024 "," 16 (output of counter 13) "," 16 (output of counter 13) +384 (output of counter 19) = 400 ",.
As described above, the interleave output from the memory 11 is performed in the order of the addresses shown in FIG.

[0021]

As described above, according to the interleaver of the present invention, when a large number of memories are not required and the number of stages of the MIL method is N, (N + 1) counters and N adders are used. Therefore, the hardware scale can be reduced and the processing speed can be improved as compared with the case of using a memory. In addition, since the counter value and offset value of each counter can be set as a parameter by a register, the same hardware can easily cope with a change in the interleave pattern at different channel types and transmission rates.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an interleaver according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an address generation unit according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of an interleaved output by the MIL method.

FIG. 4 is a conceptual diagram illustrating an outline of the MIL method.

FIG. 5 is a conceptual diagram illustrating a conventional MIL method.

[Explanation of symbols]

 11: memory, 12, 13, 16, 19: counter, 14, 17, 20: count value setting register, 15, 18, 21: counter offset register, 22, 23, 24: adder,

Claims (1)

[Claims] An interleaver for rearranging data units obtained by dividing transmission data by a multi-stage interleave method according to a predetermined rule, comprising: a memory for storing data to be transmitted at an address in data unit order; A read address generation unit that generates a data read address, wherein the read address generation unit uses the interleave length of the final stage N as a counter value,
A counter N for outputting the carry-out, a counter value setting register for the counter N for setting the counter value of the counter N as a parameter, and an offset setting for the counter N for setting the offset value added by one count of the counter N as a parameter The register and the interleave length of the (N-1) stage are used as a counter value,
The counter N counts up by the carry-out output of the final stage N and outputs the carry-out.
-1; a counter value setting register for the counter N-1 for setting the counter value of the counter N-1 as a parameter; and a counter N-1 for setting the offset value added by one count of the counter N-1 as a parameter. An offset setting register and an adder for adding a counter output of each stage and outputting a read address are provided, and are configured by connecting stepwise counters for the number of stages of the multistage interleaving method to be applied. An interleaver characterized by that: